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1 | /****************************************************************************** |
2 | * | |
3 | * This source code has been made available to you by IBM on an AS-IS | |
4 | * basis. Anyone receiving this source is licensed under IBM | |
5 | * copyrights to use it in any way he or she deems fit, including | |
6 | * copying it, modifying it, compiling it, and redistributing it either | |
7 | * with or without modifications. No license under IBM patents or | |
8 | * patent applications is to be implied by the copyright license. | |
9 | * | |
10 | * Any user of this software should understand that IBM cannot provide | |
11 | * technical support for this software and will not be responsible for | |
12 | * any consequences resulting from the use of this software. | |
13 | * | |
14 | * Any person who transfers this source code or any derivative work | |
15 | * must include the IBM copyright notice, this paragraph, and the | |
16 | * preceding two paragraphs in the transferred software. | |
17 | * | |
18 | * COPYRIGHT I B M CORPORATION 1995 | |
19 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M | |
20 | * | |
21 | *****************************************************************************/ | |
22 | #include <config.h> | |
23 | #include <ppc4xx.h> | |
24 | ||
25 | #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ | |
26 | ||
27 | #include <ppc_asm.tmpl> | |
28 | #include <ppc_defs.h> | |
29 | ||
30 | #include <asm/cache.h> | |
31 | #include <asm/mmu.h> | |
32 | ||
33 | #define LI32(reg,val) \ | |
34 | addis reg,0,val@h;\ | |
35 | ori reg,reg,val@l | |
36 | ||
37 | #define WDCR_EBC(reg,val) \ | |
38 | addi r4,0,reg;\ | |
39 | mtdcr ebccfga,r4;\ | |
40 | addis r4,0,val@h;\ | |
41 | ori r4,r4,val@l;\ | |
42 | mtdcr ebccfgd,r4 | |
43 | ||
44 | #define WDCR_SDRAM(reg,val) \ | |
45 | addi r4,0,reg;\ | |
46 | mtdcr memcfga,r4;\ | |
47 | addis r4,0,val@h;\ | |
48 | ori r4,r4,val@l;\ | |
49 | mtdcr memcfgd,r4 | |
50 | ||
51 | /****************************************************************************** | |
52 | * Function: ext_bus_cntlr_init | |
53 | * | |
54 | * Description: Configures EBC Controller and a few basic chip selects. | |
55 | * | |
56 | * CS0 is setup to get the Boot Flash out of the addresss range | |
57 | * so that we may setup a stack. CS7 is setup so that we can | |
58 | * access and reset the hardware watchdog. | |
59 | * | |
60 | * IMPORTANT: For pass1 this code must run from | |
61 | * cache since you can not reliably change a peripheral banks | |
62 | * timing register (pbxap) while running code from that bank. | |
63 | * For ex., since we are running from ROM on bank 0, we can NOT | |
64 | * execute the code that modifies bank 0 timings from ROM, so | |
65 | * we run it from cache. | |
66 | * | |
67 | * Notes: Does NOT use the stack. | |
68 | *****************************************************************************/ | |
69 | .section ".text" | |
70 | .align 2 | |
71 | .globl ext_bus_cntlr_init | |
72 | .type ext_bus_cntlr_init, @function | |
73 | ext_bus_cntlr_init: | |
74 | mflr r0 | |
75 | /******************************************************************** | |
76 | * Prefetch entire ext_bus_cntrl_init function into the icache. | |
77 | * This is necessary because we are going to change the same CS we | |
78 | * are executing from. Otherwise a CPU lockup may occur. | |
79 | *******************************************************************/ | |
80 | bl ..getAddr | |
81 | ..getAddr: | |
82 | mflr r3 /* get address of ..getAddr */ | |
83 | ||
84 | /* Calculate number of cache lines for this function */ | |
6d0f6bcf | 85 | addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) |
cd0a9de6 WD |
86 | mtctr r4 |
87 | ..ebcloop: | |
88 | icbt r0, r3 /* prefetch cache line for addr in r3*/ | |
6d0f6bcf | 89 | addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ |
cd0a9de6 WD |
90 | bdnz ..ebcloop /* continue for $CTR cache lines */ |
91 | ||
92 | /******************************************************************** | |
93 | * Delay to ensure all accesses to ROM are complete before changing | |
94 | * bank 0 timings. 200usec should be enough. | |
95 | * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. | |
96 | *******************************************************************/ | |
97 | addis r3, 0, 0x0 | |
98 | ori r3, r3, 0xA000 /* wait 200us from reset */ | |
99 | mtctr r3 | |
100 | ..spinlp: | |
101 | bdnz ..spinlp /* spin loop */ | |
102 | ||
103 | /******************************************************************** | |
104 | * SETUP CPC0_CR0 | |
105 | *******************************************************************/ | |
106 | LI32(r4, 0x007000c0) | |
107 | mtdcr cntrl0, r4 | |
108 | ||
109 | /******************************************************************** | |
110 | * Setup CPC0_CR1: Change PCIINT signal to PerWE | |
111 | *******************************************************************/ | |
112 | mfdcr r4, cntrl1 | |
113 | ori r4, r4, 0x4000 | |
114 | mtdcr cntrl1, r4 | |
115 | ||
116 | /******************************************************************** | |
117 | * Setup External Bus Controller (EBC). | |
118 | *******************************************************************/ | |
119 | WDCR_EBC(epcr, 0xd84c0000) | |
120 | /******************************************************************** | |
121 | * Memory Bank 0 (Intel 28F128J3 Flash) initialization | |
122 | *******************************************************************/ | |
123 | /*WDCR_EBC(pb0ap, 0x02869200)*/ | |
124 | WDCR_EBC(pb0ap, 0x07869200) | |
125 | WDCR_EBC(pb0cr, 0xfe0bc000) | |
126 | /******************************************************************** | |
127 | * Memory Bank 1 (Holtek HT6542B PS/2) initialization | |
128 | *******************************************************************/ | |
129 | WDCR_EBC(pb1ap, 0x1f869200) | |
130 | WDCR_EBC(pb1cr, 0xf0818000) | |
131 | /******************************************************************** | |
132 | * Memory Bank 2 (Epson S1D13506) initialization | |
133 | *******************************************************************/ | |
134 | WDCR_EBC(pb2ap, 0x05860300) | |
135 | WDCR_EBC(pb2cr, 0xf045a000) | |
136 | /******************************************************************** | |
137 | * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization | |
138 | *******************************************************************/ | |
139 | WDCR_EBC(pb3ap, 0x0387d200) | |
140 | WDCR_EBC(pb3cr, 0xf021c000) | |
141 | /******************************************************************** | |
142 | * Memory Bank 4-7 (Unused) initialization | |
143 | *******************************************************************/ | |
144 | WDCR_EBC(pb4ap, 0) | |
145 | WDCR_EBC(pb4cr, 0) | |
146 | WDCR_EBC(pb5ap, 0) | |
147 | WDCR_EBC(pb5cr, 0) | |
148 | WDCR_EBC(pb6ap, 0) | |
149 | WDCR_EBC(pb6cr, 0) | |
150 | WDCR_EBC(pb7ap, 0) | |
151 | WDCR_EBC(pb7cr, 0) | |
152 | ||
153 | /* We are all done */ | |
154 | mtlr r0 /* Restore link register */ | |
155 | blr /* Return to calling function */ | |
156 | .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init | |
157 | /* end ext_bus_cntlr_init() */ | |
158 | ||
159 | /****************************************************************************** | |
160 | * Function: sdram_init | |
161 | * | |
162 | * Description: Configures SDRAM memory banks. | |
163 | * | |
164 | * Notes: Does NOT use the stack. | |
165 | *****************************************************************************/ | |
166 | .section ".text" | |
167 | .align 2 | |
168 | .globl sdram_init | |
169 | .type sdram_init, @function | |
170 | sdram_init: | |
171 | ||
172 | /* | |
173 | * Disable memory controller to allow | |
174 | * values to be changed. | |
175 | */ | |
176 | WDCR_SDRAM(mem_mcopt1, 0x00000000) | |
177 | ||
178 | /* | |
179 | * Configure Memory Banks | |
180 | */ | |
181 | WDCR_SDRAM(mem_mb0cf, 0x00084001) | |
182 | WDCR_SDRAM(mem_mb1cf, 0x00000000) | |
183 | WDCR_SDRAM(mem_mb2cf, 0x00000000) | |
184 | WDCR_SDRAM(mem_mb3cf, 0x00000000) | |
185 | ||
186 | /* | |
187 | * Set up SDTR1 (SDRAM Timing Register) | |
188 | */ | |
189 | WDCR_SDRAM(mem_sdtr1, 0x00854009) | |
190 | ||
191 | /* | |
192 | * Set RTR (Refresh Timing Register) | |
193 | */ | |
194 | WDCR_SDRAM(mem_rtr, 0x10000000) | |
195 | /* WDCR_SDRAM(mem_rtr, 0x05f00000) */ | |
196 | ||
197 | /******************************************************************** | |
198 | * Delay to ensure 200usec have elapsed since reset. Assume worst | |
199 | * case that the core is running 200Mhz: | |
200 | * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles | |
201 | *******************************************************************/ | |
202 | addis r3, 0, 0x0000 | |
203 | ori r3, r3, 0xA000 /* Wait >200us from reset */ | |
204 | mtctr r3 | |
205 | ..spinlp2: | |
206 | bdnz ..spinlp2 /* spin loop */ | |
207 | ||
208 | /******************************************************************** | |
209 | * Set memory controller options reg, MCOPT1. | |
210 | *******************************************************************/ | |
211 | WDCR_SDRAM(mem_mcopt1,0x80800000) | |
212 | ||
213 | ..sdri_done: | |
214 | blr /* Return to calling function */ | |
215 | .Lfe1: .size sdram_init,.Lfe1-sdram_init | |
216 | /* end sdram_init() */ |