]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/engicam/icorem6/icorem6.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i.MX6Q: icore: Add SPL_OF_CONTROL support
[people/ms/u-boot.git] / board / engicam / icorem6 / icorem6.c
CommitLineData
f4b7532f
JT		 1/*
2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
f4b7532f
JT		 10
11#include <asm/io.h>
12#include <asm/gpio.h>
13#include <linux/sizes.h>
14
15#include <asm/arch/clock.h>
58413366 16#include <asm/arch/crm_regs.h>
f4b7532f
JT		 17#include <asm/arch/iomux.h>
18#include <asm/arch/mx6-pins.h>
19#include <asm/arch/sys_proto.h>
552a848e
SB		 20#include <asm/mach-imx/iomux-v3.h>
21#include <asm/mach-imx/video.h>
f4b7532f 22
ac880e77
JT		 23#include "../common/board.h"
24
f4b7532f
JT		 25DECLARE_GLOBAL_DATA_PTR;
26
023ff2f7
JT		 27#ifdef CONFIG_NAND_MXS
28
29#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
30#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
31 PAD_CTL_SRE_FAST)
32#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
33
34iomux_v3_cfg_t gpmi_pads[] = {
35 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
36 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
37 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
38 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
39 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
40 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
41 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
42 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
43 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
44 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
45 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
46 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
47 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
48 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
49 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
50};
51
ac880e77 52void setup_gpmi_nand(void)
023ff2f7
JT		 53{
54 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
55
56 /* config gpmi nand iomux */
57 SETUP_IOMUX_PADS(gpmi_pads);
58
59 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
60 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
61
62 /* config gpmi and bch clock to 100 MHz */
63 clrsetbits_le32(&mxc_ccm->cs2cdr,
64 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
65 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
66 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
67 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
68 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
69 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
70
71 /* enable ENFC_CLK_ROOT clock */
72 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
73
74 /* enable gpmi and bch clock gating */
75 setbits_le32(&mxc_ccm->CCGR4,
76 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
77 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
78 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
79 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
80 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
81
82 /* enable apbh clock gating */
83 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
84}
85#endif
86
ca7463c9
JT		 87#if defined(CONFIG_VIDEO_IPUV3)
88static iomux_v3_cfg_t const rgb_pads[] = {
89 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
90 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
91 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
92 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
93 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
94 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
95 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
96 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
97 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
98 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
99 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
100 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
101 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
102 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
103 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
104 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
105 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
106 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
107 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
108 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
109 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
110 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
111};
112
113static void enable_rgb(struct display_info_t const *dev)
114{
115 SETUP_IOMUX_PADS(rgb_pads);
116}
117
118struct display_info_t const displays[] = {
119 {
120 .bus = -1,
121 .addr = 0,
122 .pixfmt = IPU_PIX_FMT_RGB666,
123 .detect = NULL,
124 .enable = enable_rgb,
125 .mode = {
126 .name = "Amp-WD",
127 .refresh = 60,
128 .xres = 800,
129 .yres = 480,
130 .pixclock = 30000,
131 .left_margin = 30,
132 .right_margin = 30,
133 .upper_margin = 5,
134 .lower_margin = 5,
135 .hsync_len = 64,
136 .vsync_len = 20,
137 .sync = FB_SYNC_EXT,
138 .vmode = FB_VMODE_NONINTERLACED
139 }
140 },
141};
142
143size_t display_count = ARRAY_SIZE(displays);
144
ac880e77 145void setup_display(void)
ca7463c9
JT		 146{
147 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
148 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
149 int reg;
150
151 enable_ipu_clock();
152
153 /* Turn on LDB0,IPU,IPU DI0 clocks */
154 reg = __raw_readl(&mxc_ccm->CCGR3);
155 reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
156 writel(reg, &mxc_ccm->CCGR3);
157
158 /* set LDB0, LDB1 clk select to 011/011 */
159 reg = readl(&mxc_ccm->cs2cdr);
160 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
161 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
162 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
163 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
164 writel(reg, &mxc_ccm->cs2cdr);
165
166 reg = readl(&mxc_ccm->cscmr2);
167 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
168 writel(reg, &mxc_ccm->cscmr2);
169
170 reg = readl(&mxc_ccm->chsccdr);
171 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
172 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
173 writel(reg, &mxc_ccm->chsccdr);
174
175 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
176 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
177 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
178 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
179 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
180 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
181 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
182 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
183 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
184 writel(reg, &iomux->gpr[2]);
185
186 reg = readl(&iomux->gpr[3]);
187 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
188 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
189 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
190 writel(reg, &iomux->gpr[3]);
191}
192#endif /* CONFIG_VIDEO_IPUV3 */
"Das U-Boot" Source Tree