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icorem6: Add modeboot env via board_late_init
[people/ms/u-boot.git] / board / engicam / icorem6 / icorem6.c
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f4b7532f
JT		 1/*
2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
f4b7532f
JT		 10
11#include <asm/io.h>
12#include <asm/gpio.h>
13#include <linux/sizes.h>
14
15#include <asm/arch/clock.h>
58413366 16#include <asm/arch/crm_regs.h>
f4b7532f
JT		 17#include <asm/arch/iomux.h>
18#include <asm/arch/mx6-pins.h>
19#include <asm/arch/sys_proto.h>
20#include <asm/imx-common/iomux-v3.h>
ca7463c9 21#include <asm/imx-common/video.h>
f4b7532f
JT		 22
23DECLARE_GLOBAL_DATA_PTR;
24
25#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
28
f4b7532f
JT		 29static iomux_v3_cfg_t const uart4_pads[] = {
30 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
31 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
32};
33
023ff2f7
JT		 34#ifdef CONFIG_NAND_MXS
35
36#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
37#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
38 PAD_CTL_SRE_FAST)
39#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
40
41iomux_v3_cfg_t gpmi_pads[] = {
42 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
43 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
44 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
45 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
46 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
47 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
48 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
49 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
50 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
51 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
52 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
53 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
54 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
55 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
56 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
57};
58
59static void setup_gpmi_nand(void)
60{
61 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
62
63 /* config gpmi nand iomux */
64 SETUP_IOMUX_PADS(gpmi_pads);
65
66 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
67 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
68
69 /* config gpmi and bch clock to 100 MHz */
70 clrsetbits_le32(&mxc_ccm->cs2cdr,
71 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
72 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
73 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
74 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
75 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
76 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
77
78 /* enable ENFC_CLK_ROOT clock */
79 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
80
81 /* enable gpmi and bch clock gating */
82 setbits_le32(&mxc_ccm->CCGR4,
83 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
84 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
85 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
86 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
87 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
88
89 /* enable apbh clock gating */
90 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
91}
92#endif
93
ca7463c9
JT		 94#if defined(CONFIG_VIDEO_IPUV3)
95static iomux_v3_cfg_t const rgb_pads[] = {
96 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
97 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
98 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
99 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
100 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
101 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
102 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
103 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
104 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
105 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
106 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
107 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
108 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
109 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
110 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
111 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
112 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
113 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
114 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
115 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
116 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
117 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
118};
119
120static void enable_rgb(struct display_info_t const *dev)
121{
122 SETUP_IOMUX_PADS(rgb_pads);
123}
124
125struct display_info_t const displays[] = {
126 {
127 .bus = -1,
128 .addr = 0,
129 .pixfmt = IPU_PIX_FMT_RGB666,
130 .detect = NULL,
131 .enable = enable_rgb,
132 .mode = {
133 .name = "Amp-WD",
134 .refresh = 60,
135 .xres = 800,
136 .yres = 480,
137 .pixclock = 30000,
138 .left_margin = 30,
139 .right_margin = 30,
140 .upper_margin = 5,
141 .lower_margin = 5,
142 .hsync_len = 64,
143 .vsync_len = 20,
144 .sync = FB_SYNC_EXT,
145 .vmode = FB_VMODE_NONINTERLACED
146 }
147 },
148};
149
150size_t display_count = ARRAY_SIZE(displays);
151
152static void setup_display(void)
153{
154 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
155 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
156 int reg;
157
158 enable_ipu_clock();
159
160 /* Turn on LDB0,IPU,IPU DI0 clocks */
161 reg = __raw_readl(&mxc_ccm->CCGR3);
162 reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
163 writel(reg, &mxc_ccm->CCGR3);
164
165 /* set LDB0, LDB1 clk select to 011/011 */
166 reg = readl(&mxc_ccm->cs2cdr);
167 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
168 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
169 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
170 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
171 writel(reg, &mxc_ccm->cs2cdr);
172
173 reg = readl(&mxc_ccm->cscmr2);
174 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
175 writel(reg, &mxc_ccm->cscmr2);
176
177 reg = readl(&mxc_ccm->chsccdr);
178 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
179 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
180 writel(reg, &mxc_ccm->chsccdr);
181
182 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
183 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
184 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
185 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
186 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
187 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
188 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
189 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
190 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
191 writel(reg, &iomux->gpr[2]);
192
193 reg = readl(&iomux->gpr[3]);
194 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
195 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
196 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
197 writel(reg, &iomux->gpr[3]);
198}
199#endif /* CONFIG_VIDEO_IPUV3 */
200
f4b7532f
JT		 201int board_early_init_f(void)
202{
203 SETUP_IOMUX_PADS(uart4_pads);
204
205 return 0;
206}
207
98f56610
JT		 208int board_late_init(void)
209{
210 switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
211 IMX6_BMODE_SHIFT) {
212 case IMX6_BMODE_SD:
213 case IMX6_BMODE_ESD:
214 setenv("modeboot", "mmcboot");
215 break;
216 case IMX6_BMODE_NAND:
217 setenv("modeboot", "nandboot");
218 break;
219 default:
220 setenv("modeboot", "");
221 break;
222 }
223
224 return 0;
225}
226
f4b7532f
JT		 227int board_init(void)
228{
229 /* Address of boot parameters */
230 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
231
023ff2f7
JT		 232#ifdef CONFIG_NAND_MXS
233 setup_gpmi_nand();
234#endif
ca7463c9
JT		 235
236#ifdef CONFIG_VIDEO_IPUV3
237 setup_display();
238#endif
239
f4b7532f
JT		 240 return 0;
241}
242
243int dram_init(void)
244{
245 gd->ram_size = imx_ddr_size();
246
247 return 0;
248}
249
250#ifdef CONFIG_SPL_BUILD
251#include <libfdt.h>
252#include <spl.h>
253
254#include <asm/arch/crm_regs.h>
255#include <asm/arch/mx6-ddr.h>
256
f160c5c8
JT		 257/* MMC board initialization is needed till adding DM support in SPL */
258#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
259#include <mmc.h>
260#include <fsl_esdhc.h>
261
262#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
263 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
264 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
265
266static iomux_v3_cfg_t const usdhc1_pads[] = {
267 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
268 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
269 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
270 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
271 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
272 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
273 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
274};
275
276#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
277
278struct fsl_esdhc_cfg usdhc_cfg[1] = {
279 {USDHC1_BASE_ADDR, 0, 4},
280};
281
282int board_mmc_getcd(struct mmc *mmc)
283{
284 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
285 int ret = 0;
286
287 switch (cfg->esdhc_base) {
288 case USDHC1_BASE_ADDR:
289 ret = !gpio_get_value(USDHC1_CD_GPIO);
290 break;
291 }
292
293 return ret;
294}
295
296int board_mmc_init(bd_t *bis)
297{
298 int i, ret;
299
300 /*
301 * According to the board_mmc_init() the following map is done:
302 * (U-boot device node) (Physical Port)
303 * mmc0 USDHC1
304 */
305 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
306 switch (i) {
307 case 0:
308 SETUP_IOMUX_PADS(usdhc1_pads);
309 gpio_direction_input(USDHC1_CD_GPIO);
310 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
311 break;
312 default:
313 printf("Warning - USDHC%d controller not supporting\n",
314 i + 1);
315 return 0;
316 }
317
318 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
319 if (ret) {
320 printf("Warning: failed to initialize mmc dev %d\n", i);
321 return ret;
322 }
323 }
324
325 return 0;
326}
327#endif
328
f4b7532f
JT		 329/*
330 * Driving strength:
331 * 0x30 == 40 Ohm
332 * 0x28 == 48 Ohm
333 */
334
335#define IMX6DQ_DRIVE_STRENGTH 0x30
336#define IMX6SDL_DRIVE_STRENGTH 0x28
337
338/* configure MX6Q/DUAL mmdc DDR io registers */
339static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
340 .dram_sdqs0 = 0x28,
341 .dram_sdqs1 = 0x28,
342 .dram_sdqs2 = 0x28,
343 .dram_sdqs3 = 0x28,
344 .dram_sdqs4 = 0x28,
345 .dram_sdqs5 = 0x28,
346 .dram_sdqs6 = 0x28,
347 .dram_sdqs7 = 0x28,
348 .dram_dqm0 = 0x28,
349 .dram_dqm1 = 0x28,
350 .dram_dqm2 = 0x28,
351 .dram_dqm3 = 0x28,
352 .dram_dqm4 = 0x28,
353 .dram_dqm5 = 0x28,
354 .dram_dqm6 = 0x28,
355 .dram_dqm7 = 0x28,
356 .dram_cas = 0x30,
357 .dram_ras = 0x30,
358 .dram_sdclk_0 = 0x30,
359 .dram_sdclk_1 = 0x30,
360 .dram_reset = 0x30,
361 .dram_sdcke0 = 0x3000,
362 .dram_sdcke1 = 0x3000,
363 .dram_sdba2 = 0x00000000,
364 .dram_sdodt0 = 0x30,
365 .dram_sdodt1 = 0x30,
366};
367
368/* configure MX6Q/DUAL mmdc GRP io registers */
369static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
370 .grp_b0ds = 0x30,
371 .grp_b1ds = 0x30,
372 .grp_b2ds = 0x30,
373 .grp_b3ds = 0x30,
374 .grp_b4ds = 0x30,
375 .grp_b5ds = 0x30,
376 .grp_b6ds = 0x30,
377 .grp_b7ds = 0x30,
378 .grp_addds = 0x30,
379 .grp_ddrmode_ctl = 0x00020000,
380 .grp_ddrpke = 0x00000000,
381 .grp_ddrmode = 0x00020000,
382 .grp_ctlds = 0x30,
383 .grp_ddr_type = 0x000c0000,
384};
385
386/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
387struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
388 .dram_sdclk_0 = 0x30,
389 .dram_sdclk_1 = 0x30,
390 .dram_cas = 0x30,
391 .dram_ras = 0x30,
392 .dram_reset = 0x30,
393 .dram_sdcke0 = 0x30,
394 .dram_sdcke1 = 0x30,
395 .dram_sdba2 = 0x00000000,
396 .dram_sdodt0 = 0x30,
397 .dram_sdodt1 = 0x30,
398 .dram_sdqs0 = 0x28,
399 .dram_sdqs1 = 0x28,
400 .dram_sdqs2 = 0x28,
401 .dram_sdqs3 = 0x28,
402 .dram_sdqs4 = 0x28,
403 .dram_sdqs5 = 0x28,
404 .dram_sdqs6 = 0x28,
405 .dram_sdqs7 = 0x28,
406 .dram_dqm0 = 0x28,
407 .dram_dqm1 = 0x28,
408 .dram_dqm2 = 0x28,
409 .dram_dqm3 = 0x28,
410 .dram_dqm4 = 0x28,
411 .dram_dqm5 = 0x28,
412 .dram_dqm6 = 0x28,
413 .dram_dqm7 = 0x28,
414};
415
416/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
417struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
418 .grp_ddr_type = 0x000c0000,
419 .grp_ddrmode_ctl = 0x00020000,
420 .grp_ddrpke = 0x00000000,
421 .grp_addds = 0x30,
422 .grp_ctlds = 0x30,
423 .grp_ddrmode = 0x00020000,
424 .grp_b0ds = 0x28,
425 .grp_b1ds = 0x28,
426 .grp_b2ds = 0x28,
427 .grp_b3ds = 0x28,
428 .grp_b4ds = 0x28,
429 .grp_b5ds = 0x28,
430 .grp_b6ds = 0x28,
431 .grp_b7ds = 0x28,
432};
433
434/* mt41j256 */
435static struct mx6_ddr3_cfg mt41j256 = {
436 .mem_speed = 1066,
437 .density = 2,
438 .width = 16,
439 .banks = 8,
440 .rowaddr = 13,
441 .coladdr = 10,
442 .pagesz = 2,
443 .trcd = 1375,
444 .trcmin = 4875,
445 .trasmin = 3500,
446 .SRT = 0,
447};
448
449static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
450 .p0_mpwldectrl0 = 0x000E0009,
451 .p0_mpwldectrl1 = 0x0018000E,
452 .p1_mpwldectrl0 = 0x00000007,
453 .p1_mpwldectrl1 = 0x00000000,
454 .p0_mpdgctrl0 = 0x43280334,
455 .p0_mpdgctrl1 = 0x031C0314,
456 .p1_mpdgctrl0 = 0x4318031C,
457 .p1_mpdgctrl1 = 0x030C0258,
458 .p0_mprddlctl = 0x3E343A40,
459 .p1_mprddlctl = 0x383C3844,
460 .p0_mpwrdlctl = 0x40404440,
461 .p1_mpwrdlctl = 0x4C3E4446,
462};
463
464/* DDR 64bit */
465static struct mx6_ddr_sysinfo mem_q = {
466 .ddr_type = DDR_TYPE_DDR3,
467 .dsize = 2,
468 .cs1_mirror = 0,
469 /* config for full 4GB range so that get_mem_size() works */
470 .cs_density = 32,
471 .ncs = 1,
472 .bi_on = 1,
473 .rtt_nom = 2,
474 .rtt_wr = 2,
475 .ralat = 5,
476 .walat = 0,
477 .mif3_mode = 3,
478 .rst_to_cke = 0x23,
479 .sde_to_rst = 0x10,
480};
481
482static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
483 .p0_mpwldectrl0 = 0x001F0024,
484 .p0_mpwldectrl1 = 0x00110018,
485 .p1_mpwldectrl0 = 0x001F0024,
486 .p1_mpwldectrl1 = 0x00110018,
487 .p0_mpdgctrl0 = 0x4230022C,
488 .p0_mpdgctrl1 = 0x02180220,
489 .p1_mpdgctrl0 = 0x42440248,
490 .p1_mpdgctrl1 = 0x02300238,
491 .p0_mprddlctl = 0x44444A48,
492 .p1_mprddlctl = 0x46484A42,
493 .p0_mpwrdlctl = 0x38383234,
494 .p1_mpwrdlctl = 0x3C34362E,
495};
496
497/* DDR 64bit 1GB */
498static struct mx6_ddr_sysinfo mem_dl = {
499 .dsize = 2,
500 .cs1_mirror = 0,
501 /* config for full 4GB range so that get_mem_size() works */
502 .cs_density = 32,
503 .ncs = 1,
504 .bi_on = 1,
505 .rtt_nom = 1,
506 .rtt_wr = 1,
507 .ralat = 5,
508 .walat = 0,
509 .mif3_mode = 3,
510 .rst_to_cke = 0x23,
511 .sde_to_rst = 0x10,
512};
513
514/* DDR 32bit 512MB */
515static struct mx6_ddr_sysinfo mem_s = {
516 .dsize = 1,
517 .cs1_mirror = 0,
518 /* config for full 4GB range so that get_mem_size() works */
519 .cs_density = 32,
520 .ncs = 1,
521 .bi_on = 1,
522 .rtt_nom = 1,
523 .rtt_wr = 1,
524 .ralat = 5,
525 .walat = 0,
526 .mif3_mode = 3,
527 .rst_to_cke = 0x23,
528 .sde_to_rst = 0x10,
529};
530
531static void ccgr_init(void)
532{
533 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
534
535 writel(0x00003F3F, &ccm->CCGR0);
536 writel(0x0030FC00, &ccm->CCGR1);
537 writel(0x000FC000, &ccm->CCGR2);
538 writel(0x3F300000, &ccm->CCGR3);
539 writel(0xFF00F300, &ccm->CCGR4);
540 writel(0x0F0000C3, &ccm->CCGR5);
541 writel(0x000003CC, &ccm->CCGR6);
542}
543
544static void gpr_init(void)
545{
546 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
547
548 /* enable AXI cache for VDOA/VPU/IPU */
549 writel(0xF00000CF, &iomux->gpr[4]);
550 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
551 writel(0x007F007F, &iomux->gpr[6]);
552 writel(0x007F007F, &iomux->gpr[7]);
553}
554
555static void spl_dram_init(void)
556{
557 if (is_mx6solo()) {
558 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
559 mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);
560 } else if (is_mx6dl()) {
561 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
562 mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256);
563 } else if (is_mx6dq()) {
564 mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
565 mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
566 }
567
568 udelay(100);
569}
570
571void board_init_f(ulong dummy)
572{
573 ccgr_init();
574
575 /* setup AIPS and disable watchdog */
576 arch_cpu_init();
577
578 gpr_init();
579
580 /* iomux */
581 board_early_init_f();
582
583 /* setup GP timer */
584 timer_init();
585
586 /* UART clocks enabled and gd valid - init serial console */
587 preloader_console_init();
588
589 /* DDR initialization */
590 spl_dram_init();
591
592 /* Clear the BSS. */
593 memset(__bss_start, 0, __bss_end - __bss_start);
594
595 /* load/boot image from boot device */
596 board_init_r(NULL, 0);
597}
598#endif
"Das U-Boot" Source Tree