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f4b7532f JT |
1 | /* |
2 | * Copyright (C) 2016 Amarula Solutions B.V. | |
3 | * Copyright (C) 2016 Engicam S.r.l. | |
4 | * Author: Jagan Teki <jagan@amarulasolutions.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #include <common.h> | |
4bbd4059 | 10 | #include <mmc.h> |
f4b7532f JT |
11 | |
12 | #include <asm/io.h> | |
13 | #include <asm/gpio.h> | |
14 | #include <linux/sizes.h> | |
15 | ||
16 | #include <asm/arch/clock.h> | |
58413366 | 17 | #include <asm/arch/crm_regs.h> |
f4b7532f JT |
18 | #include <asm/arch/iomux.h> |
19 | #include <asm/arch/mx6-pins.h> | |
20 | #include <asm/arch/sys_proto.h> | |
21 | #include <asm/imx-common/iomux-v3.h> | |
ca7463c9 | 22 | #include <asm/imx-common/video.h> |
f4b7532f JT |
23 | |
24 | DECLARE_GLOBAL_DATA_PTR; | |
25 | ||
26 | #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
27 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | |
28 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
29 | ||
f4b7532f JT |
30 | static iomux_v3_cfg_t const uart4_pads[] = { |
31 | IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
32 | IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
33 | }; | |
34 | ||
023ff2f7 JT |
35 | #ifdef CONFIG_NAND_MXS |
36 | ||
37 | #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) | |
38 | #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ | |
39 | PAD_CTL_SRE_FAST) | |
40 | #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) | |
41 | ||
42 | iomux_v3_cfg_t gpmi_pads[] = { | |
43 | IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
44 | IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
45 | IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
46 | IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)), | |
47 | IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
48 | IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
49 | IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
50 | IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
51 | IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
52 | IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
53 | IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
54 | IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
55 | IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
56 | IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
57 | IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)), | |
58 | }; | |
59 | ||
60 | static void setup_gpmi_nand(void) | |
61 | { | |
62 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
63 | ||
64 | /* config gpmi nand iomux */ | |
65 | SETUP_IOMUX_PADS(gpmi_pads); | |
66 | ||
67 | /* gate ENFC_CLK_ROOT clock first,before clk source switch */ | |
68 | clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
69 | ||
70 | /* config gpmi and bch clock to 100 MHz */ | |
71 | clrsetbits_le32(&mxc_ccm->cs2cdr, | |
72 | MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | | |
73 | MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | | |
74 | MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, | |
75 | MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | | |
76 | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | | |
77 | MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); | |
78 | ||
79 | /* enable ENFC_CLK_ROOT clock */ | |
80 | setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); | |
81 | ||
82 | /* enable gpmi and bch clock gating */ | |
83 | setbits_le32(&mxc_ccm->CCGR4, | |
84 | MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | | |
85 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | | |
86 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | | |
87 | MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | | |
88 | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); | |
89 | ||
90 | /* enable apbh clock gating */ | |
91 | setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); | |
92 | } | |
93 | #endif | |
94 | ||
ca7463c9 JT |
95 | #if defined(CONFIG_VIDEO_IPUV3) |
96 | static iomux_v3_cfg_t const rgb_pads[] = { | |
97 | IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), | |
98 | IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), | |
99 | IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), | |
100 | IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), | |
101 | IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), | |
102 | IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), | |
103 | IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), | |
104 | IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), | |
105 | IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), | |
106 | IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), | |
107 | IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), | |
108 | IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), | |
109 | IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), | |
110 | IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), | |
111 | IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), | |
112 | IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), | |
113 | IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), | |
114 | IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), | |
115 | IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), | |
116 | IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), | |
117 | IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), | |
118 | IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), | |
119 | }; | |
120 | ||
121 | static void enable_rgb(struct display_info_t const *dev) | |
122 | { | |
123 | SETUP_IOMUX_PADS(rgb_pads); | |
124 | } | |
125 | ||
126 | struct display_info_t const displays[] = { | |
127 | { | |
128 | .bus = -1, | |
129 | .addr = 0, | |
130 | .pixfmt = IPU_PIX_FMT_RGB666, | |
131 | .detect = NULL, | |
132 | .enable = enable_rgb, | |
133 | .mode = { | |
134 | .name = "Amp-WD", | |
135 | .refresh = 60, | |
136 | .xres = 800, | |
137 | .yres = 480, | |
138 | .pixclock = 30000, | |
139 | .left_margin = 30, | |
140 | .right_margin = 30, | |
141 | .upper_margin = 5, | |
142 | .lower_margin = 5, | |
143 | .hsync_len = 64, | |
144 | .vsync_len = 20, | |
145 | .sync = FB_SYNC_EXT, | |
146 | .vmode = FB_VMODE_NONINTERLACED | |
147 | } | |
148 | }, | |
149 | }; | |
150 | ||
151 | size_t display_count = ARRAY_SIZE(displays); | |
152 | ||
153 | static void setup_display(void) | |
154 | { | |
155 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
156 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
157 | int reg; | |
158 | ||
159 | enable_ipu_clock(); | |
160 | ||
161 | /* Turn on LDB0,IPU,IPU DI0 clocks */ | |
162 | reg = __raw_readl(&mxc_ccm->CCGR3); | |
163 | reg |= (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff); | |
164 | writel(reg, &mxc_ccm->CCGR3); | |
165 | ||
166 | /* set LDB0, LDB1 clk select to 011/011 */ | |
167 | reg = readl(&mxc_ccm->cs2cdr); | |
168 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | | |
169 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); | |
170 | reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | | |
171 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); | |
172 | writel(reg, &mxc_ccm->cs2cdr); | |
173 | ||
174 | reg = readl(&mxc_ccm->cscmr2); | |
175 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; | |
176 | writel(reg, &mxc_ccm->cscmr2); | |
177 | ||
178 | reg = readl(&mxc_ccm->chsccdr); | |
179 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << | |
180 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); | |
181 | writel(reg, &mxc_ccm->chsccdr); | |
182 | ||
183 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | | |
184 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH | | |
185 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | | |
186 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | | |
187 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | | |
188 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | | |
189 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | | |
190 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED | | |
191 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; | |
192 | writel(reg, &iomux->gpr[2]); | |
193 | ||
194 | reg = readl(&iomux->gpr[3]); | |
195 | reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | | |
196 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << | |
197 | IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); | |
198 | writel(reg, &iomux->gpr[3]); | |
199 | } | |
200 | #endif /* CONFIG_VIDEO_IPUV3 */ | |
201 | ||
f4b7532f JT |
202 | int board_early_init_f(void) |
203 | { | |
204 | SETUP_IOMUX_PADS(uart4_pads); | |
205 | ||
206 | return 0; | |
207 | } | |
208 | ||
4bbd4059 JT |
209 | #ifdef CONFIG_ENV_IS_IN_MMC |
210 | static void mmc_late_init(void) | |
211 | { | |
212 | char cmd[32]; | |
213 | char mmcblk[32]; | |
214 | u32 dev_no = mmc_get_env_dev(); | |
215 | ||
216 | setenv_ulong("mmcdev", dev_no); | |
217 | ||
218 | /* Set mmcblk env */ | |
219 | sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); | |
220 | setenv("mmcroot", mmcblk); | |
221 | ||
222 | sprintf(cmd, "mmc dev %d", dev_no); | |
223 | run_command(cmd, 0); | |
224 | } | |
225 | #endif | |
226 | ||
98f56610 JT |
227 | int board_late_init(void) |
228 | { | |
229 | switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >> | |
230 | IMX6_BMODE_SHIFT) { | |
231 | case IMX6_BMODE_SD: | |
232 | case IMX6_BMODE_ESD: | |
4bbd4059 JT |
233 | #ifdef CONFIG_ENV_IS_IN_MMC |
234 | mmc_late_init(); | |
235 | #endif | |
98f56610 JT |
236 | setenv("modeboot", "mmcboot"); |
237 | break; | |
238 | case IMX6_BMODE_NAND: | |
239 | setenv("modeboot", "nandboot"); | |
240 | break; | |
241 | default: | |
242 | setenv("modeboot", ""); | |
243 | break; | |
244 | } | |
245 | ||
6f1f3f59 JT |
246 | if (is_mx6dq()) |
247 | setenv("fdt_file", "imx6q-icore.dtb"); | |
248 | else if(is_mx6dl() || is_mx6solo()) | |
249 | setenv("fdt_file", "imx6dl-icore.dtb"); | |
250 | ||
98f56610 JT |
251 | return 0; |
252 | } | |
253 | ||
f4b7532f JT |
254 | int board_init(void) |
255 | { | |
256 | /* Address of boot parameters */ | |
257 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
258 | ||
023ff2f7 JT |
259 | #ifdef CONFIG_NAND_MXS |
260 | setup_gpmi_nand(); | |
261 | #endif | |
ca7463c9 JT |
262 | |
263 | #ifdef CONFIG_VIDEO_IPUV3 | |
264 | setup_display(); | |
265 | #endif | |
266 | ||
f4b7532f JT |
267 | return 0; |
268 | } | |
269 | ||
270 | int dram_init(void) | |
271 | { | |
272 | gd->ram_size = imx_ddr_size(); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | #ifdef CONFIG_SPL_BUILD | |
278 | #include <libfdt.h> | |
279 | #include <spl.h> | |
280 | ||
281 | #include <asm/arch/crm_regs.h> | |
282 | #include <asm/arch/mx6-ddr.h> | |
283 | ||
f160c5c8 JT |
284 | /* MMC board initialization is needed till adding DM support in SPL */ |
285 | #if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) | |
286 | #include <mmc.h> | |
287 | #include <fsl_esdhc.h> | |
288 | ||
289 | #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
290 | PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ | |
291 | PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
292 | ||
293 | static iomux_v3_cfg_t const usdhc1_pads[] = { | |
294 | IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
295 | IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
296 | IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
297 | IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
298 | IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
299 | IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
300 | IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */ | |
301 | }; | |
302 | ||
303 | #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) | |
304 | ||
305 | struct fsl_esdhc_cfg usdhc_cfg[1] = { | |
306 | {USDHC1_BASE_ADDR, 0, 4}, | |
307 | }; | |
308 | ||
309 | int board_mmc_getcd(struct mmc *mmc) | |
310 | { | |
311 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
312 | int ret = 0; | |
313 | ||
314 | switch (cfg->esdhc_base) { | |
315 | case USDHC1_BASE_ADDR: | |
316 | ret = !gpio_get_value(USDHC1_CD_GPIO); | |
317 | break; | |
318 | } | |
319 | ||
320 | return ret; | |
321 | } | |
322 | ||
323 | int board_mmc_init(bd_t *bis) | |
324 | { | |
325 | int i, ret; | |
326 | ||
327 | /* | |
328 | * According to the board_mmc_init() the following map is done: | |
329 | * (U-boot device node) (Physical Port) | |
330 | * mmc0 USDHC1 | |
331 | */ | |
332 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { | |
333 | switch (i) { | |
334 | case 0: | |
335 | SETUP_IOMUX_PADS(usdhc1_pads); | |
336 | gpio_direction_input(USDHC1_CD_GPIO); | |
337 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); | |
338 | break; | |
339 | default: | |
340 | printf("Warning - USDHC%d controller not supporting\n", | |
341 | i + 1); | |
342 | return 0; | |
343 | } | |
344 | ||
345 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); | |
346 | if (ret) { | |
347 | printf("Warning: failed to initialize mmc dev %d\n", i); | |
348 | return ret; | |
349 | } | |
350 | } | |
351 | ||
352 | return 0; | |
353 | } | |
354 | #endif | |
355 | ||
bc1fe900 JT |
356 | #ifdef CONFIG_SPL_LOAD_FIT |
357 | int board_fit_config_name_match(const char *name) | |
358 | { | |
359 | if (is_mx6dq() && !strcmp(name, "imx6q-icore")) | |
360 | return 0; | |
361 | else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore")) | |
362 | return 0; | |
363 | else | |
364 | return -1; | |
365 | } | |
366 | #endif | |
367 | ||
f4b7532f JT |
368 | /* |
369 | * Driving strength: | |
370 | * 0x30 == 40 Ohm | |
371 | * 0x28 == 48 Ohm | |
372 | */ | |
373 | ||
374 | #define IMX6DQ_DRIVE_STRENGTH 0x30 | |
375 | #define IMX6SDL_DRIVE_STRENGTH 0x28 | |
376 | ||
377 | /* configure MX6Q/DUAL mmdc DDR io registers */ | |
378 | static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { | |
379 | .dram_sdqs0 = 0x28, | |
380 | .dram_sdqs1 = 0x28, | |
381 | .dram_sdqs2 = 0x28, | |
382 | .dram_sdqs3 = 0x28, | |
383 | .dram_sdqs4 = 0x28, | |
384 | .dram_sdqs5 = 0x28, | |
385 | .dram_sdqs6 = 0x28, | |
386 | .dram_sdqs7 = 0x28, | |
387 | .dram_dqm0 = 0x28, | |
388 | .dram_dqm1 = 0x28, | |
389 | .dram_dqm2 = 0x28, | |
390 | .dram_dqm3 = 0x28, | |
391 | .dram_dqm4 = 0x28, | |
392 | .dram_dqm5 = 0x28, | |
393 | .dram_dqm6 = 0x28, | |
394 | .dram_dqm7 = 0x28, | |
395 | .dram_cas = 0x30, | |
396 | .dram_ras = 0x30, | |
397 | .dram_sdclk_0 = 0x30, | |
398 | .dram_sdclk_1 = 0x30, | |
399 | .dram_reset = 0x30, | |
400 | .dram_sdcke0 = 0x3000, | |
401 | .dram_sdcke1 = 0x3000, | |
402 | .dram_sdba2 = 0x00000000, | |
403 | .dram_sdodt0 = 0x30, | |
404 | .dram_sdodt1 = 0x30, | |
405 | }; | |
406 | ||
407 | /* configure MX6Q/DUAL mmdc GRP io registers */ | |
408 | static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { | |
409 | .grp_b0ds = 0x30, | |
410 | .grp_b1ds = 0x30, | |
411 | .grp_b2ds = 0x30, | |
412 | .grp_b3ds = 0x30, | |
413 | .grp_b4ds = 0x30, | |
414 | .grp_b5ds = 0x30, | |
415 | .grp_b6ds = 0x30, | |
416 | .grp_b7ds = 0x30, | |
417 | .grp_addds = 0x30, | |
418 | .grp_ddrmode_ctl = 0x00020000, | |
419 | .grp_ddrpke = 0x00000000, | |
420 | .grp_ddrmode = 0x00020000, | |
421 | .grp_ctlds = 0x30, | |
422 | .grp_ddr_type = 0x000c0000, | |
423 | }; | |
424 | ||
425 | /* configure MX6SOLO/DUALLITE mmdc DDR io registers */ | |
426 | struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { | |
427 | .dram_sdclk_0 = 0x30, | |
428 | .dram_sdclk_1 = 0x30, | |
429 | .dram_cas = 0x30, | |
430 | .dram_ras = 0x30, | |
431 | .dram_reset = 0x30, | |
432 | .dram_sdcke0 = 0x30, | |
433 | .dram_sdcke1 = 0x30, | |
434 | .dram_sdba2 = 0x00000000, | |
435 | .dram_sdodt0 = 0x30, | |
436 | .dram_sdodt1 = 0x30, | |
437 | .dram_sdqs0 = 0x28, | |
438 | .dram_sdqs1 = 0x28, | |
439 | .dram_sdqs2 = 0x28, | |
440 | .dram_sdqs3 = 0x28, | |
441 | .dram_sdqs4 = 0x28, | |
442 | .dram_sdqs5 = 0x28, | |
443 | .dram_sdqs6 = 0x28, | |
444 | .dram_sdqs7 = 0x28, | |
445 | .dram_dqm0 = 0x28, | |
446 | .dram_dqm1 = 0x28, | |
447 | .dram_dqm2 = 0x28, | |
448 | .dram_dqm3 = 0x28, | |
449 | .dram_dqm4 = 0x28, | |
450 | .dram_dqm5 = 0x28, | |
451 | .dram_dqm6 = 0x28, | |
452 | .dram_dqm7 = 0x28, | |
453 | }; | |
454 | ||
455 | /* configure MX6SOLO/DUALLITE mmdc GRP io registers */ | |
456 | struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { | |
457 | .grp_ddr_type = 0x000c0000, | |
458 | .grp_ddrmode_ctl = 0x00020000, | |
459 | .grp_ddrpke = 0x00000000, | |
460 | .grp_addds = 0x30, | |
461 | .grp_ctlds = 0x30, | |
462 | .grp_ddrmode = 0x00020000, | |
463 | .grp_b0ds = 0x28, | |
464 | .grp_b1ds = 0x28, | |
465 | .grp_b2ds = 0x28, | |
466 | .grp_b3ds = 0x28, | |
467 | .grp_b4ds = 0x28, | |
468 | .grp_b5ds = 0x28, | |
469 | .grp_b6ds = 0x28, | |
470 | .grp_b7ds = 0x28, | |
471 | }; | |
472 | ||
473 | /* mt41j256 */ | |
474 | static struct mx6_ddr3_cfg mt41j256 = { | |
475 | .mem_speed = 1066, | |
476 | .density = 2, | |
477 | .width = 16, | |
478 | .banks = 8, | |
479 | .rowaddr = 13, | |
480 | .coladdr = 10, | |
481 | .pagesz = 2, | |
482 | .trcd = 1375, | |
483 | .trcmin = 4875, | |
484 | .trasmin = 3500, | |
485 | .SRT = 0, | |
486 | }; | |
487 | ||
488 | static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { | |
489 | .p0_mpwldectrl0 = 0x000E0009, | |
490 | .p0_mpwldectrl1 = 0x0018000E, | |
491 | .p1_mpwldectrl0 = 0x00000007, | |
492 | .p1_mpwldectrl1 = 0x00000000, | |
493 | .p0_mpdgctrl0 = 0x43280334, | |
494 | .p0_mpdgctrl1 = 0x031C0314, | |
495 | .p1_mpdgctrl0 = 0x4318031C, | |
496 | .p1_mpdgctrl1 = 0x030C0258, | |
497 | .p0_mprddlctl = 0x3E343A40, | |
498 | .p1_mprddlctl = 0x383C3844, | |
499 | .p0_mpwrdlctl = 0x40404440, | |
500 | .p1_mpwrdlctl = 0x4C3E4446, | |
501 | }; | |
502 | ||
503 | /* DDR 64bit */ | |
504 | static struct mx6_ddr_sysinfo mem_q = { | |
505 | .ddr_type = DDR_TYPE_DDR3, | |
506 | .dsize = 2, | |
507 | .cs1_mirror = 0, | |
508 | /* config for full 4GB range so that get_mem_size() works */ | |
509 | .cs_density = 32, | |
510 | .ncs = 1, | |
511 | .bi_on = 1, | |
512 | .rtt_nom = 2, | |
513 | .rtt_wr = 2, | |
514 | .ralat = 5, | |
515 | .walat = 0, | |
516 | .mif3_mode = 3, | |
517 | .rst_to_cke = 0x23, | |
518 | .sde_to_rst = 0x10, | |
519 | }; | |
520 | ||
521 | static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { | |
522 | .p0_mpwldectrl0 = 0x001F0024, | |
523 | .p0_mpwldectrl1 = 0x00110018, | |
524 | .p1_mpwldectrl0 = 0x001F0024, | |
525 | .p1_mpwldectrl1 = 0x00110018, | |
526 | .p0_mpdgctrl0 = 0x4230022C, | |
527 | .p0_mpdgctrl1 = 0x02180220, | |
528 | .p1_mpdgctrl0 = 0x42440248, | |
529 | .p1_mpdgctrl1 = 0x02300238, | |
530 | .p0_mprddlctl = 0x44444A48, | |
531 | .p1_mprddlctl = 0x46484A42, | |
532 | .p0_mpwrdlctl = 0x38383234, | |
533 | .p1_mpwrdlctl = 0x3C34362E, | |
534 | }; | |
535 | ||
536 | /* DDR 64bit 1GB */ | |
537 | static struct mx6_ddr_sysinfo mem_dl = { | |
538 | .dsize = 2, | |
539 | .cs1_mirror = 0, | |
540 | /* config for full 4GB range so that get_mem_size() works */ | |
541 | .cs_density = 32, | |
542 | .ncs = 1, | |
543 | .bi_on = 1, | |
544 | .rtt_nom = 1, | |
545 | .rtt_wr = 1, | |
546 | .ralat = 5, | |
547 | .walat = 0, | |
548 | .mif3_mode = 3, | |
549 | .rst_to_cke = 0x23, | |
550 | .sde_to_rst = 0x10, | |
551 | }; | |
552 | ||
553 | /* DDR 32bit 512MB */ | |
554 | static struct mx6_ddr_sysinfo mem_s = { | |
555 | .dsize = 1, | |
556 | .cs1_mirror = 0, | |
557 | /* config for full 4GB range so that get_mem_size() works */ | |
558 | .cs_density = 32, | |
559 | .ncs = 1, | |
560 | .bi_on = 1, | |
561 | .rtt_nom = 1, | |
562 | .rtt_wr = 1, | |
563 | .ralat = 5, | |
564 | .walat = 0, | |
565 | .mif3_mode = 3, | |
566 | .rst_to_cke = 0x23, | |
567 | .sde_to_rst = 0x10, | |
568 | }; | |
569 | ||
570 | static void ccgr_init(void) | |
571 | { | |
572 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
573 | ||
574 | writel(0x00003F3F, &ccm->CCGR0); | |
575 | writel(0x0030FC00, &ccm->CCGR1); | |
576 | writel(0x000FC000, &ccm->CCGR2); | |
577 | writel(0x3F300000, &ccm->CCGR3); | |
578 | writel(0xFF00F300, &ccm->CCGR4); | |
579 | writel(0x0F0000C3, &ccm->CCGR5); | |
580 | writel(0x000003CC, &ccm->CCGR6); | |
581 | } | |
582 | ||
583 | static void gpr_init(void) | |
584 | { | |
585 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
586 | ||
587 | /* enable AXI cache for VDOA/VPU/IPU */ | |
588 | writel(0xF00000CF, &iomux->gpr[4]); | |
589 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ | |
590 | writel(0x007F007F, &iomux->gpr[6]); | |
591 | writel(0x007F007F, &iomux->gpr[7]); | |
592 | } | |
593 | ||
594 | static void spl_dram_init(void) | |
595 | { | |
596 | if (is_mx6solo()) { | |
597 | mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); | |
598 | mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); | |
599 | } else if (is_mx6dl()) { | |
600 | mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); | |
601 | mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); | |
602 | } else if (is_mx6dq()) { | |
603 | mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); | |
604 | mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); | |
605 | } | |
606 | ||
607 | udelay(100); | |
608 | } | |
609 | ||
610 | void board_init_f(ulong dummy) | |
611 | { | |
612 | ccgr_init(); | |
613 | ||
614 | /* setup AIPS and disable watchdog */ | |
615 | arch_cpu_init(); | |
616 | ||
617 | gpr_init(); | |
618 | ||
619 | /* iomux */ | |
620 | board_early_init_f(); | |
621 | ||
622 | /* setup GP timer */ | |
623 | timer_init(); | |
624 | ||
625 | /* UART clocks enabled and gd valid - init serial console */ | |
626 | preloader_console_init(); | |
627 | ||
628 | /* DDR initialization */ | |
629 | spl_dram_init(); | |
630 | ||
631 | /* Clear the BSS. */ | |
632 | memset(__bss_start, 0, __bss_end - __bss_start); | |
633 | ||
634 | /* load/boot image from boot device */ | |
635 | board_init_r(NULL, 0); | |
636 | } | |
637 | #endif |