[people/ms/u-boot.git] / board / engicam / icorem6 / icorem6.c

/*
 * Copyright (C) 2016 Amarula Solutions B.V.
 * Copyright (C) 2016 Engicam S.r.l.
 * Author: Jagan Teki <jagan@amarulasolutions.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>

#include <asm/io.h>
#include <asm/gpio.h>
#include <linux/sizes.h>

#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/video.h>

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_NAND_MXS

#define GPMI_PAD_CTRL0	(PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1	(PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
			PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2	(GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)

iomux_v3_cfg_t gpmi_pads[] = {
	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07	| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
};

static void setup_gpmi_nand(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* config gpmi nand iomux */
	SETUP_IOMUX_PADS(gpmi_pads);

	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);

	/* config gpmi and bch clock to 100 MHz */
	clrsetbits_le32(&mxc_ccm->cs2cdr,
			MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
			MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
			MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
			MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
			MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));

	/* enable ENFC_CLK_ROOT clock */
	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);

	/* enable gpmi and bch clock gating */
	setbits_le32(&mxc_ccm->CCGR4,
		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);

	/* enable apbh clock gating */
	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
#endif

#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const rgb_pads[] = {
	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
};

static void enable_rgb(struct display_info_t const *dev)
{
	SETUP_IOMUX_PADS(rgb_pads);
}

struct display_info_t const displays[] = {
	{
		.bus	= -1,
		.addr	= 0,
		.pixfmt	= IPU_PIX_FMT_RGB666,
		.detect	= NULL,
		.enable	= enable_rgb,
		.mode	= {
			.name           = "Amp-WD",
			.refresh        = 60,
			.xres           = 800,
			.yres           = 480,
			.pixclock       = 30000,
			.left_margin    = 30,
			.right_margin   = 30,
			.upper_margin   = 5,
			.lower_margin   = 5,
			.hsync_len      = 64,
			.vsync_len      = 20,
			.sync           = FB_SYNC_EXT,
			.vmode          = FB_VMODE_NONINTERLACED
		}
	},
};

size_t display_count = ARRAY_SIZE(displays);

static void setup_display(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
	int reg;

	enable_ipu_clock();

	/* Turn on LDB0,IPU,IPU DI0 clocks */
	reg = __raw_readl(&mxc_ccm->CCGR3);
	reg |=  (MXC_CCM_CCGR3_LDB_DI0_MASK | 0xffff);
	writel(reg, &mxc_ccm->CCGR3);

	/* set LDB0, LDB1 clk select to 011/011 */
	reg = readl(&mxc_ccm->cs2cdr);
	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
		MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
	reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
		(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->cs2cdr);

	reg = readl(&mxc_ccm->cscmr2);
	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
	writel(reg, &mxc_ccm->cscmr2);

	reg = readl(&mxc_ccm->chsccdr);
	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
		MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
	writel(reg, &mxc_ccm->chsccdr);

	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
		IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
		IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
		IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
		IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
		IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
		IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
		IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
		IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
	writel(reg, &iomux->gpr[2]);

	reg = readl(&iomux->gpr[3]);
	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) |
		(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
		IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
	writel(reg, &iomux->gpr[3]);
}
#endif /* CONFIG_VIDEO_IPUV3 */

#ifdef CONFIG_ENV_IS_IN_MMC
static void mmc_late_init(void)
{
	char cmd[32];
	char mmcblk[32];
	u32 dev_no = mmc_get_env_dev();

	setenv_ulong("mmcdev", dev_no);

	/* Set mmcblk env */
	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
	setenv("mmcroot", mmcblk);

	sprintf(cmd, "mmc dev %d", dev_no);
	run_command(cmd, 0);
}
#endif

int board_late_init(void)
{
	switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
			IMX6_BMODE_SHIFT) {
	case IMX6_BMODE_SD:
	case IMX6_BMODE_ESD:
#ifdef CONFIG_ENV_IS_IN_MMC
		mmc_late_init();
#endif
		setenv("modeboot", "mmcboot");
		break;
	case IMX6_BMODE_NAND:
		setenv("modeboot", "nandboot");
		break;
	default:
		setenv("modeboot", "");
		break;
	}

	if (is_mx6dq())
		setenv("fdt_file", "imx6q-icore.dtb");
	else if(is_mx6dl() || is_mx6solo())
		setenv("fdt_file", "imx6dl-icore.dtb");

	return 0;
}

int board_init(void)
{
	/* Address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_NAND_MXS
	setup_gpmi_nand();
#endif

#ifdef CONFIG_VIDEO_IPUV3
	setup_display();
#endif

	return 0;
}

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

#ifdef CONFIG_SPL_BUILD
/* MMC board initialization is needed till adding DM support in SPL */
#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
#include <mmc.h>
#include <fsl_esdhc.h>

#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

static iomux_v3_cfg_t const usdhc1_pads[] = {
	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
};

#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 1)

struct fsl_esdhc_cfg usdhc_cfg[1] = {
	{USDHC1_BASE_ADDR, 0, 4},
};

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		ret = !gpio_get_value(USDHC1_CD_GPIO);
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int i, ret;

	/*
	* According to the board_mmc_init() the following map is done:
	* (U-boot device node)    (Physical Port)
	* mmc0				USDHC1
	*/
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			SETUP_IOMUX_PADS(usdhc1_pads);
			gpio_direction_input(USDHC1_CD_GPIO);
			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
			break;
		default:
			printf("Warning - USDHC%d controller not supporting\n",
			       i + 1);
			return 0;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret) {
			printf("Warning: failed to initialize mmc dev %d\n", i);
			return ret;
		}
	}

	return 0;
}
#endif

#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
	if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
		return 0;
	else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
		return 0;
	else
		return -1;
}
#endif
#endif /* CONFIG_SPL_BUILD */
Commit	Line	Data
f4b7532f JT	1	/*
	2	* Copyright (C) 2016 Amarula Solutions B.V.
	3	* Copyright (C) 2016 Engicam S.r.l.
	4	* Author: Jagan Teki <jagan@amarulasolutions.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <common.h>
4bbd4059	10	#include <mmc.h>
f4b7532f JT	11
	12	#include <asm/io.h>
	13	#include <asm/gpio.h>
	14	#include <linux/sizes.h>
	15
	16	#include <asm/arch/clock.h>
58413366	17	#include <asm/arch/crm_regs.h>
f4b7532f JT	18	#include <asm/arch/iomux.h>
	19	#include <asm/arch/mx6-pins.h>
	20	#include <asm/arch/sys_proto.h>
	21	#include <asm/imx-common/iomux-v3.h>
ca7463c9	22	#include <asm/imx-common/video.h>
f4b7532f JT	23
	24	DECLARE_GLOBAL_DATA_PTR;
	25
023ff2f7 JT	26	#ifdef CONFIG_NAND_MXS
	27
	28	#define GPMI_PAD_CTRL0 (PAD_CTL_PKE \| PAD_CTL_PUE \| PAD_CTL_PUS_100K_UP)
	29	#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm \| PAD_CTL_SPEED_MED \| \
	30	PAD_CTL_SRE_FAST)
	31	#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 \| GPMI_PAD_CTRL1)
	32
	33	iomux_v3_cfg_t gpmi_pads[] = {
	34	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	35	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	36	IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	37	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
	38	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	39	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	40	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	41	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	42	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	43	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	44	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	45	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	46	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	47	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	48	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 \| MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
	49	};
	50
	51	static void setup_gpmi_nand(void)
	52	{
	53	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	54
	55	/* config gpmi nand iomux */
	56	SETUP_IOMUX_PADS(gpmi_pads);
	57
	58	/* gate ENFC_CLK_ROOT clock first,before clk source switch */
	59	clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
	60
	61	/* config gpmi and bch clock to 100 MHz */
	62	clrsetbits_le32(&mxc_ccm->cs2cdr,
	63	MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK \|
	64	MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK \|
	65	MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
	66	MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) \|
	67	MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) \|
	68	MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
	69
	70	/* enable ENFC_CLK_ROOT clock */
	71	setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
	72
	73	/* enable gpmi and bch clock gating */
	74	setbits_le32(&mxc_ccm->CCGR4,
	75	MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK \|
	76	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK \|
	77	MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK \|
	78	MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK \|
	79	MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
	80
	81	/* enable apbh clock gating */
	82	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
	83	}
	84	#endif
	85
ca7463c9 JT	86	#if defined(CONFIG_VIDEO_IPUV3)
	87	static iomux_v3_cfg_t const rgb_pads[] = {
	88	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
	89	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15),
	90	IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02),
	91	IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03),
	92	IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
	93	IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
	94	IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
	95	IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
	96	IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
	97	IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
	98	IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
	99	IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
	100	IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
	101	IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
	102	IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
	103	IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
	104	IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
	105	IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
	106	IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
	107	IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
	108	IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
	109	IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
	110	};
	111
	112	static void enable_rgb(struct display_info_t const *dev)
	113	{
	114	SETUP_IOMUX_PADS(rgb_pads);
	115	}
	116
	117	struct display_info_t const displays[] = {
	118	{
	119	.bus = -1,
	120	.addr = 0,
	121	.pixfmt = IPU_PIX_FMT_RGB666,
	122	.detect = NULL,
	123	.enable = enable_rgb,
	124	.mode = {
	125	.name = "Amp-WD",
	126	.refresh = 60,
	127	.xres = 800,
	128	.yres = 480,
	129	.pixclock = 30000,
	130	.left_margin = 30,
	131	.right_margin = 30,
	132	.upper_margin = 5,
	133	.lower_margin = 5,
	134	.hsync_len = 64,
	135	.vsync_len = 20,
	136	.sync = FB_SYNC_EXT,
	137	.vmode = FB_VMODE_NONINTERLACED
	138	}
	139	},
	140	};
	141
	142	size_t display_count = ARRAY_SIZE(displays);
	143
	144	static void setup_display(void)
	145	{
	146	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	147	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	148	int reg;
	149
150	enable_ipu_clock();
151
152	/* Turn on LDB0,IPU,IPU DI0 clocks */
153	reg = __raw_readl(&mxc_ccm->CCGR3);
154	reg \|= (MXC_CCM_CCGR3_LDB_DI0_MASK \| 0xffff);
155	writel(reg, &mxc_ccm->CCGR3);
156
157	/* set LDB0, LDB1 clk select to 011/011 */
158	reg = readl(&mxc_ccm->cs2cdr);
159	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK \|
160	MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
161	reg \|= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) \|
162	(3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
163	writel(reg, &mxc_ccm->cs2cdr);
164
165	reg = readl(&mxc_ccm->cscmr2);
166	reg \|= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
167	writel(reg, &mxc_ccm->cscmr2);
168
169	reg = readl(&mxc_ccm->chsccdr);
170	reg \|= (CHSCCDR_CLK_SEL_LDB_DI0 <<
171	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
172	writel(reg, &mxc_ccm->chsccdr);
173
174	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES \|
175	IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH \|
176	IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW \|
177	IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG \|
178	IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT \|
179	IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG \|
180	IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT \|
181	IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED \|
182	IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
183	writel(reg, &iomux->gpr[2]);
184
185	reg = readl(&iomux->gpr[3]);
186	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) \|
187	(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
188	IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
189	writel(reg, &iomux->gpr[3]);
190	}
191	#endif /* CONFIG_VIDEO_IPUV3 */
192
4bbd4059 JT	193	#ifdef CONFIG_ENV_IS_IN_MMC
	194	static void mmc_late_init(void)
	195	{
	196	char cmd[32];
	197	char mmcblk[32];
	198	u32 dev_no = mmc_get_env_dev();
	199
	200	setenv_ulong("mmcdev", dev_no);
	201
	202	/* Set mmcblk env */
	203	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
	204	setenv("mmcroot", mmcblk);
	205
	206	sprintf(cmd, "mmc dev %d", dev_no);
	207	run_command(cmd, 0);
	208	}
	209	#endif
	210
98f56610 JT	211	int board_late_init(void)
	212	{
	213	switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
	214	IMX6_BMODE_SHIFT) {
	215	case IMX6_BMODE_SD:
	216	case IMX6_BMODE_ESD:
4bbd4059 JT	217	#ifdef CONFIG_ENV_IS_IN_MMC
	218	mmc_late_init();
	219	#endif
98f56610 JT	220	setenv("modeboot", "mmcboot");
	221	break;
	222	case IMX6_BMODE_NAND:
	223	setenv("modeboot", "nandboot");
	224	break;
	225	default:
	226	setenv("modeboot", "");
	227	break;
	228	}
	229
6f1f3f59 JT	230	if (is_mx6dq())
	231	setenv("fdt_file", "imx6q-icore.dtb");
	232	else if(is_mx6dl() \|\| is_mx6solo())
	233	setenv("fdt_file", "imx6dl-icore.dtb");
	234
98f56610 JT	235	return 0;
	236	}
	237
f4b7532f JT	238	int board_init(void)
	239	{
	240	/* Address of boot parameters */
	241	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	242
023ff2f7 JT	243	#ifdef CONFIG_NAND_MXS
	244	setup_gpmi_nand();
	245	#endif
ca7463c9 JT	246
	247	#ifdef CONFIG_VIDEO_IPUV3
	248	setup_display();
	249	#endif
	250
f4b7532f JT	251	return 0;
	252	}
	253
	254	int dram_init(void)
	255	{
	256	gd->ram_size = imx_ddr_size();
	257
	258	return 0;
	259	}
	260
	261	#ifdef CONFIG_SPL_BUILD
f160c5c8 JT	262	/* MMC board initialization is needed till adding DM support in SPL */
	263	#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
	264	#include <mmc.h>
	265	#include <fsl_esdhc.h>
	266
	267	#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	268	PAD_CTL_PUS_22K_UP \| PAD_CTL_SPEED_LOW \| \
	269	PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	270
	271	static iomux_v3_cfg_t const usdhc1_pads[] = {
	272	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	273	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	274	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	275	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	276	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	277	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
	278	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 \| MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
	279	};
	280
	281	#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
	282
	283	struct fsl_esdhc_cfg usdhc_cfg[1] = {
	284	{USDHC1_BASE_ADDR, 0, 4},
	285	};
	286
	287	int board_mmc_getcd(struct mmc *mmc)
	288	{
	289	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	290	int ret = 0;
	291
	292	switch (cfg->esdhc_base) {
	293	case USDHC1_BASE_ADDR:
	294	ret = !gpio_get_value(USDHC1_CD_GPIO);
	295	break;
	296	}
	297
	298	return ret;
	299	}
	300
	301	int board_mmc_init(bd_t *bis)
	302	{
	303	int i, ret;
	304
	305	/*
	306	* According to the board_mmc_init() the following map is done:
	307	* (U-boot device node) (Physical Port)
	308	* mmc0 USDHC1
	309	*/
	310	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	311	switch (i) {
	312	case 0:
	313	SETUP_IOMUX_PADS(usdhc1_pads);
	314	gpio_direction_input(USDHC1_CD_GPIO);
	315	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	316	break;
	317	default:
	318	printf("Warning - USDHC%d controller not supporting\n",
	319	i + 1);
	320	return 0;
	321	}
	322
	323	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	324	if (ret) {
	325	printf("Warning: failed to initialize mmc dev %d\n", i);
326	return ret;
327	}
328	}
329
330	return 0;
331	}
332	#endif
333
bc1fe900 JT	334	#ifdef CONFIG_SPL_LOAD_FIT
	335	int board_fit_config_name_match(const char *name)
	336	{
	337	if (is_mx6dq() && !strcmp(name, "imx6q-icore"))
	338	return 0;
	339	else if ((is_mx6dl() \|\| is_mx6solo()) && !strcmp(name, "imx6dl-icore"))
	340	return 0;
	341	else
	342	return -1;
	343	}
	344	#endif
d8de3c73	345	#endif /* CONFIG_SPL_BUILD */