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15a08bc2 MF |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
15a08bc2 MF |
6 | */ |
7 | ||
25ddd1fb | 8 | #include <asm-offsets.h> |
15a08bc2 | 9 | #include <ppc_asm.tmpl> |
61f2b38a | 10 | #include <asm/mmu.h> |
15a08bc2 MF |
11 | #include <config.h> |
12 | ||
13 | /* | |
14 | * TLB TABLE | |
15 | * | |
16 | * This table is used by the cpu boot code to setup the initial tlb | |
17 | * entries. Rather than make broad assumptions in the cpu source tree, | |
18 | * this table lets each board set things up however they like. | |
19 | * | |
20 | * Pointer to the table is returned in r1 | |
21 | */ | |
22 | .section .bootpg,"ax" | |
23 | .globl tlbtab | |
24 | ||
25 | tlbtab: | |
26 | tlbtab_start | |
27 | ||
28 | /* | |
29 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
30 | * speed up boot process. It is patched after relocation to enable SA_I | |
31 | */ | |
cf6eb6da | 32 | tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G ) |
15a08bc2 | 33 | |
6d0f6bcf | 34 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
15a08bc2 | 35 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
cf6eb6da | 36 | tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G ) |
15a08bc2 MF |
37 | #endif |
38 | ||
39 | /* TLB-entry for PCI Memory */ | |
cf6eb6da SR |
40 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG ) |
41 | tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG ) | |
42 | tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG ) | |
43 | tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG ) | |
15a08bc2 MF |
44 | |
45 | /* TLB-entry for PCI IO */ | |
cf6eb6da | 46 | tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG ) |
15a08bc2 MF |
47 | |
48 | /* TLB-entries for EBC: CPLD, DUMEM, DUIO */ | |
cf6eb6da SR |
49 | tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG ) |
50 | tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG ) | |
51 | tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG ) | |
15a08bc2 MF |
52 | |
53 | /* TLB-entry for NAND */ | |
cf6eb6da SR |
54 | tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG ) |
55 | tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG ) | |
15a08bc2 MF |
56 | |
57 | /* TLB-entry for Internal Registers & OCM */ | |
cf6eb6da | 58 | tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I ) |
15a08bc2 MF |
59 | |
60 | /* TLB-entry PCI registers */ | |
cf6eb6da | 61 | tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG ) |
15a08bc2 MF |
62 | |
63 | /* TLB-entry for peripherals */ | |
cf6eb6da | 64 | tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG) |
15a08bc2 MF |
65 | |
66 | tlbtab_end |