[people/ms/u-boot.git] / board / etin / kvme080 / kvme080.c

/*
 * (C) Copyright 2005
 * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc824x.h>
#include <pci.h>
#include <i2c.h>
#include <netdev.h>
#include <asm/processor.h>

int checkboard(void)
{
	puts ("Board: KVME080\n");
	return 0;
}

unsigned long setdram(int m, int row, int col, int bank)
{
	int i;
	unsigned long start, end;
	uint32_t mccr1;
	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
	uint8_t mber = 0;

	CONFIG_READ_WORD(MCCR1, mccr1);
	mccr1 &= 0xffff0000;

	start = CONFIG_SYS_SDRAM_BASE;
	end = start + (1 << (col + row + 3) ) * bank - 1;

	for (i = 0; i < m; i++) {
		mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
		if (i < 4) {
			msar1  |= ((start >> 20) & 0xff) << i * 8;
			emsar1 |= ((start >> 28) & 0xff) << i * 8;
			mear1  |= ((end >> 20) & 0xff) << i * 8;
			emear1 |= ((end >> 28) & 0xff) << i * 8;
		} else {
			msar2  |= ((start >> 20) & 0xff) << (i-4) * 8;
			emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
			mear2  |= ((end >> 20) & 0xff) << (i-4) * 8;
			emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
		}
		mber |= 1 << i;
		start += (1 << (col + row + 3) ) * bank;
		end += (1 << (col + row + 3) ) * bank;
	}
	for (; i < 8; i++) {
		if (i < 4) {
			msar1  |= 0xff << i * 8;
			emsar1 |= 0x30 << i * 8;
			mear1  |= 0xff << i * 8;
			emear1 |= 0x30 << i * 8;
		} else {
			msar2  |= 0xff << (i-4) * 8;
			emsar2 |= 0x30 << (i-4) * 8;
			mear2  |= 0xff << (i-4) * 8;
			emear2 |= 0x30 << (i-4) * 8;
		}
	}

	CONFIG_WRITE_WORD(MCCR1, mccr1);
	CONFIG_WRITE_WORD(MSAR1, msar1);
	CONFIG_WRITE_WORD(EMSAR1, emsar1);
	CONFIG_WRITE_WORD(MEAR1, mear1);
	CONFIG_WRITE_WORD(EMEAR1, emear1);
	CONFIG_WRITE_WORD(MSAR2, msar2);
	CONFIG_WRITE_WORD(EMSAR2, emsar2);
	CONFIG_WRITE_WORD(MEAR2, mear2);
	CONFIG_WRITE_WORD(EMEAR2, emear2);
	CONFIG_WRITE_BYTE(MBER, mber);

	return (1 << (col + row + 3) ) * bank * m;
}

phys_size_t initdram(int board_type)
{
	unsigned int msr;
	long int size = 0;

	msr = mfmsr();
	mtmsr(msr & ~(MSR_IR | MSR_DR));
	mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
	mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
	mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
	mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
	mtmsr(msr);

	if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
		size = 0x20000000;	/* 512MB */
	else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
		size = 0x10000000;	/* 256MB */
	else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
		size = 0x10000000;	/* 256MB */
	else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
		size = 0x08000000;	/* 128MB */
	else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
		size = 0x08000000;	/* 128MB */
	else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
		size = 0x04000000;	/* 64MB */

	msr = mfmsr();
	mtmsr(msr & ~(MSR_IR | MSR_DR));
	mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
	mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
	mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
	mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
	mtmsr(msr);

	return size;
}

struct pci_controller hose;

void pci_init_board(void)
{
	pci_mpc824x_init(&hose);
}

int board_early_init_f(void)
{
	*(volatile unsigned char *)(0xff080120) = 0xfb;

	return 0;
}

int board_early_init_r(void)
{
	unsigned int msr;

	CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
	CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
	CONFIG_WRITE_WORD(ERCR4, 0x0800000e);

	msr = mfmsr();
	mtmsr(msr & ~(MSR_IR | MSR_DR));
	mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
	mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
	mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
	mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
	mtmsr(msr);

	return 0;
}

extern int multiverse_init(void);

int misc_init_r(void)
{
	multiverse_init();
	return 0;
}

void *nvram_read(void *dest, const long src, size_t count)
{
	volatile uchar *d = (volatile uchar*) dest;
	volatile uchar *s = (volatile uchar*) src;
	while(count--) {
		*d++ = *s++;
		asm volatile("sync");
	}
	return dest;
}

void nvram_write(long dest, const void *src, size_t count)
{
	volatile uchar *d = (volatile uchar*)dest;
	volatile uchar *s = (volatile uchar*)src;
	while(count--) {
		*d++ = *s++;
		asm volatile("sync");
	}
}

int board_eth_init(bd_t *bis)
{
	return pci_eth_init(bis);
}
Commit	Line	Data
53dd6ce4 WD	1	/*
	2	* (C) Copyright 2005
	3	* Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc824x.h>
	26	#include <pci.h>
	27	#include <i2c.h>
10efa024	28	#include <netdev.h>
53dd6ce4 WD	29	#include <asm/processor.h>
	30
	31	int checkboard(void)
	32	{
	33	puts ("Board: KVME080\n");
	34	return 0;
	35	}
	36
	37	unsigned long setdram(int m, int row, int col, int bank)
	38	{
	39	int i;
	40	unsigned long start, end;
	41	uint32_t mccr1;
	42	uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
	43	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
	44	uint8_t mber = 0;
	45
	46	CONFIG_READ_WORD(MCCR1, mccr1);
	47	mccr1 &= 0xffff0000;
	48
6d0f6bcf	49	start = CONFIG_SYS_SDRAM_BASE;
53dd6ce4 WD	50	end = start + (1 << (col + row + 3) ) * bank - 1;
	51
	52	for (i = 0; i < m; i++) {
	53	mccr1 \|= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
	54	if (i < 4) {
	55	msar1 \|= ((start >> 20) & 0xff) << i * 8;
	56	emsar1 \|= ((start >> 28) & 0xff) << i * 8;
	57	mear1 \|= ((end >> 20) & 0xff) << i * 8;
	58	emear1 \|= ((end >> 28) & 0xff) << i * 8;
	59	} else {
	60	msar2 \|= ((start >> 20) & 0xff) << (i-4) * 8;
	61	emsar2 \|= ((start >> 28) & 0xff) << (i-4) * 8;
	62	mear2 \|= ((end >> 20) & 0xff) << (i-4) * 8;
	63	emear2 \|= ((end >> 28) & 0xff) << (i-4) * 8;
	64	}
	65	mber \|= 1 << i;
	66	start += (1 << (col + row + 3) ) * bank;
	67	end += (1 << (col + row + 3) ) * bank;
	68	}
	69	for (; i < 8; i++) {
	70	if (i < 4) {
	71	msar1 \|= 0xff << i * 8;
	72	emsar1 \|= 0x30 << i * 8;
	73	mear1 \|= 0xff << i * 8;
	74	emear1 \|= 0x30 << i * 8;
	75	} else {
	76	msar2 \|= 0xff << (i-4) * 8;
	77	emsar2 \|= 0x30 << (i-4) * 8;
	78	mear2 \|= 0xff << (i-4) * 8;
	79	emear2 \|= 0x30 << (i-4) * 8;
	80	}
	81	}
	82
	83	CONFIG_WRITE_WORD(MCCR1, mccr1);
	84	CONFIG_WRITE_WORD(MSAR1, msar1);
	85	CONFIG_WRITE_WORD(EMSAR1, emsar1);
	86	CONFIG_WRITE_WORD(MEAR1, mear1);
	87	CONFIG_WRITE_WORD(EMEAR1, emear1);
	88	CONFIG_WRITE_WORD(MSAR2, msar2);
	89	CONFIG_WRITE_WORD(EMSAR2, emsar2);
	90	CONFIG_WRITE_WORD(MEAR2, mear2);
	91	CONFIG_WRITE_WORD(EMEAR2, emear2);
	92	CONFIG_WRITE_BYTE(MBER, mber);
	93
	94	return (1 << (col + row + 3) ) * bank * m;
	95	}
	96
9973e3c6	97	phys_size_t initdram(int board_type)
53dd6ce4 WD	98	{
	99	unsigned int msr;
	100	long int size = 0;
	101
	102	msr = mfmsr();
	103	mtmsr(msr & ~(MSR_IR \| MSR_DR));
6d0f6bcf JCPV	104	mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
	105	mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
	106	mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
	107	mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
53dd6ce4 WD	108	mtmsr(msr);
53dd6ce4 WD	109
6d0f6bcf	110	if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
53dd6ce4	111	size = 0x20000000; /* 512MB */
6d0f6bcf	112	else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
53dd6ce4	113	size = 0x10000000; /* 256MB */
6d0f6bcf	114	else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
53dd6ce4	115	size = 0x10000000; /* 256MB */
6d0f6bcf	116	else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
53dd6ce4	117	size = 0x08000000; /* 128MB */
6d0f6bcf	118	else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
53dd6ce4	119	size = 0x08000000; /* 128MB */
6d0f6bcf	120	else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
53dd6ce4 WD	121	size = 0x04000000; /* 64MB */
	122
	123	msr = mfmsr();
	124	mtmsr(msr & ~(MSR_IR \| MSR_DR));
6d0f6bcf JCPV	125	mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
	126	mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
	127	mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
	128	mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
53dd6ce4 WD	129	mtmsr(msr);
	130
	131	return size;
	132	}
	133
	134	struct pci_controller hose;
	135
	136	void pci_init_board(void)
	137	{
	138	pci_mpc824x_init(&hose);
	139	}
	140
	141	int board_early_init_f(void)
	142	{
	143	(volatile unsigned char )(0xff080120) = 0xfb;
	144
	145	return 0;
	146	}
	147
	148	int board_early_init_r(void)
	149	{
	150	unsigned int msr;
	151
	152	CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
	153	CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
	154	CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
	155
	156	msr = mfmsr();
	157	mtmsr(msr & ~(MSR_IR \| MSR_DR));
	158	mtspr(IBAT1L, 0x70000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT);
	159	mtspr(IBAT1U, 0x70000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP);
	160	mtspr(DBAT1L, 0x70000000 \| BATL_PP_10 \| BATL_CACHEINHIBIT);
	161	mtspr(DBAT1U, 0x70000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP);
	162	mtmsr(msr);
	163
	164	return 0;
	165	}
	166
	167	extern int multiverse_init(void);
	168
	169	int misc_init_r(void)
	170	{
	171	multiverse_init();
	172	return 0;
	173	}
	174
	175	void nvram_read(void dest, const long src, size_t count)
	176	{
	177	volatile uchar d = (volatile uchar) dest;
	178	volatile uchar s = (volatile uchar) src;
	179	while(count--) {
	180	d++ = s++;
	181	asm volatile("sync");
	182	}
	183	return dest;
	184	}
	185
	186	void nvram_write(long dest, const void *src, size_t count)
	187	{
	188	volatile uchar d = (volatile uchar)dest;
	189	volatile uchar s = (volatile uchar)src;
	190	while(count--) {
	191	d++ = s++;
	192	asm volatile("sync");
193	}
194	}
10efa024 BW	195
	196	int board_eth_init(bd_t *bis)
	197	{
	198	return pci_eth_init(bis);
	199	}