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ac14xx: cleanup comments in the board support
[people/ms/u-boot.git] / board / ifm / ac14xx / ac14xx.c
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fcc7fe42
AG		 1/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009 Dave Srl www.dave.eu
4 * (C) Copyright 2010 ifm ecomatic GmbH
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15#include <common.h>
16#include <asm/bitops.h>
17#include <command.h>
18#include <asm/io.h>
19#include <asm/processor.h>
20#include <asm/mpc512x.h>
21#include <fdt_support.h>
22#ifdef CONFIG_MISC_INIT_R
23#include <i2c.h>
24#endif
25
26DECLARE_GLOBAL_DATA_PTR;
27
28static void gpio_configure(void)
29{
30 immap_t *im;
31 gpio512x_t *gpioregs;
32
33 im = (immap_t *) CONFIG_SYS_IMMR;
34 gpioregs = &im->gpio;
35 out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
36 out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
37
38 /*
39 * out_be32(&gpioregs->gpdir, 0xC2293020);
b5992e77 40 * workaround for a hardware effect: configure direction in pieces,
fcc7fe42
AG		 41 * setting all outputs at once drops the reset line too low and
42 * makes us lose the MII connection (breaks ethernet for us)
43 */
44 out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
45 setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
46 udelay(10);
47 setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
48 udelay(10);
49 setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
50 udelay(10);
51 setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
52
53 /* to turn from red to yellow when U-Boot runs */
54 setbits_be32(&gpioregs->gpdat, 0x00002020);
55 out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
56 out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
57 out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
58 out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
59}
60
61/* the physical location of the pins */
62#define GPIOKEY_ROW_BITMASK 0x40000000
63#define GPIOKEY_ROW_UPPER 0
64#define GPIOKEY_ROW_LOWER 1
65
66#define GPIOKEY_COL0_BITMASK 0x20000000
67#define GPIOKEY_COL1_BITMASK 0x10000000
68#define GPIOKEY_COL2_BITMASK 0x08000000
69
70/* the logical presentation of pressed keys */
71#define GPIOKEY_BIT_FNLEFT (1 << 5)
72#define GPIOKEY_BIT_FNRIGHT (1 << 4)
73#define GPIOKEY_BIT_DIRUP (1 << 3)
74#define GPIOKEY_BIT_DIRLEFT (1 << 2)
75#define GPIOKEY_BIT_DIRRIGHT (1 << 1)
76#define GPIOKEY_BIT_DIRDOWN (1 << 0)
77
78/* the hotkey combination which starts recovery */
79#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
80 GPIOKEY_BIT_DIRDOWN)
81
82static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
83{
84
85 if (row)
86 setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
87 else
88 clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
89 udelay(10);
90}
91
92static u32 gpio_querykbd(void)
93{
94 immap_t *im;
95 gpio512x_t *gpioregs;
96 u32 keybits;
97 u32 input;
98
99 im = (immap_t *)CONFIG_SYS_IMMR;
100 gpioregs = &im->gpio;
101 keybits = 0;
102
103 /* query upper row */
104 gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
105 input = in_be32(&gpioregs->gpdat);
106 if ((input & GPIOKEY_COL0_BITMASK) == 0)
107 keybits |= GPIOKEY_BIT_FNLEFT;
108 if ((input & GPIOKEY_COL1_BITMASK) == 0)
109 keybits |= GPIOKEY_BIT_DIRUP;
110 if ((input & GPIOKEY_COL2_BITMASK) == 0)
111 keybits |= GPIOKEY_BIT_FNRIGHT;
112
113 /* query lower row */
114 gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
115 input = in_be32(&gpioregs->gpdat);
116 if ((input & GPIOKEY_COL0_BITMASK) == 0)
117 keybits |= GPIOKEY_BIT_DIRLEFT;
118 if ((input & GPIOKEY_COL1_BITMASK) == 0)
119 keybits |= GPIOKEY_BIT_DIRRIGHT;
120 if ((input & GPIOKEY_COL2_BITMASK) == 0)
121 keybits |= GPIOKEY_BIT_DIRDOWN;
122
123 /* return bit pattern for keys */
124 return keybits;
125}
126
127/* excerpt from the recovery's hw_info.h */
128
129static int eeprom_diag = 1;
130
131struct __attribute__ ((__packed__)) eeprom_layout {
132 char magic[3]; /** 'ifm' */
133 u8 len[2]; /** content length without magic/len fields */
134 u8 version[3]; /** structure version */
135 u8 type; /** type of PCB */
136 u8 reserved[0x37]; /** padding up to offset 0x40 */
137 u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
138};
139
140#define HW_COMP_MAINCPU 2
141
142static struct eeprom_layout eeprom_content;
143static int eeprom_was_read; /* has_been_read */
144static int eeprom_is_valid;
145static int eeprom_version;
146
147#define get_eeprom_field_int(name) ({ \
148 int value; \
149 int idx; \
150 value = 0; \
151 for (idx = 0; idx < sizeof(name); idx++) { \
152 value <<= 8; \
153 value |= name[idx]; \
154 } \
155 value; \
156})
157
158static int read_eeprom(void)
159{
160 int eeprom_datalen;
161 int ret;
162
163 if (eeprom_was_read)
164 return 0;
165
166 eeprom_is_valid = 0;
167 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
168 CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
169 (uchar *)&eeprom_content, sizeof(eeprom_content));
170 if (eeprom_diag) {
171 printf("DIAG: %s() read rc[%d], size[%d]\n",
172 __func__, ret, sizeof(eeprom_content));
173 }
174
175 if (ret != 0)
176 return -1;
177
178 eeprom_was_read = 1;
179
180 /*
181 * check validity of EEPROM content
182 * (check version, length, optionally checksum)
183 */
184 eeprom_is_valid = 1;
185 eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
186 eeprom_version = get_eeprom_field_int(eeprom_content.version);
187
188 if (eeprom_diag) {
189 printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
190 __func__, eeprom_content.magic[0],
191 eeprom_content.magic[1], eeprom_content.magic[2],
192 eeprom_datalen, eeprom_version, eeprom_content.type);
193 }
194 if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
195 eeprom_is_valid = 0;
196 if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
197 eeprom_is_valid = 0;
198 if ((eeprom_version != 1) && (eeprom_version != 2))
199 eeprom_is_valid = 0;
200 if (eeprom_content.type != HW_COMP_MAINCPU)
201 eeprom_is_valid = 0;
202
203 if (eeprom_diag)
204 printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
205
206 return ret;
207}
208
209int mac_read_from_eeprom(void)
210{
211 const u8 *mac;
186f9c13 212 const char *mac_txt;
fcc7fe42
AG		 213
214 if (read_eeprom()) {
215 printf("I2C EEPROM read failed.\n");
216 return -1;
217 }
218
219 if (!eeprom_is_valid) {
220 printf("I2C EEPROM content not valid\n");
221 return -1;
222 }
223
224 mac = NULL;
225 switch (eeprom_version) {
226 case 1:
227 case 2:
228 mac = (const u8 *)&eeprom_content.macaddress;
229 break;
230 }
231
232 if (mac && is_valid_ether_addr(mac)) {
233 eth_setenv_enetaddr("ethaddr", mac);
186f9c13
GS		 234 mac_txt = getenv("ethaddr");
235 if (mac_txt)
236 printf("DIAG: MAC value [%s]\n", mac_txt);
237 else
238 printf("DIAG: failed to setup MAC env\n");
fcc7fe42
AG		 239 }
240
241 return 0;
242}
243
244/*
245 * BEWARE!
246 * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
247 * which the ADS, Aria or PDM360NG boards are using
248 * (the steps outlined here refer to the Micron datasheet)
249 */
250u32 sdram_init_seq[] = {
251 /* item 6, at least one NOP after CKE went high */
252 CONFIG_SYS_DDRCMD_NOP,
253 CONFIG_SYS_DDRCMD_NOP,
254 CONFIG_SYS_DDRCMD_NOP,
255 CONFIG_SYS_DDRCMD_NOP,
256 CONFIG_SYS_DDRCMD_NOP,
257 CONFIG_SYS_DDRCMD_NOP,
258 CONFIG_SYS_DDRCMD_NOP,
259 CONFIG_SYS_DDRCMD_NOP,
260 CONFIG_SYS_DDRCMD_NOP,
261 CONFIG_SYS_DDRCMD_NOP,
262 /* item 7, precharge all; item 8, tRP (20ns) */
263 CONFIG_SYS_DDRCMD_PCHG_ALL,
264 CONFIG_SYS_DDRCMD_NOP,
265 /* item 9, extended mode register; item 10, tMRD 10ns) */
266 CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
267 CONFIG_SYS_DDRCMD_NOP,
268 /*
269 * item 11, (base) mode register _with_ reset DLL;
270 * item 12, tMRD (10ns)
271 */
272 CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
273 CONFIG_SYS_MICRON_BMODE_PARAM,
274 CONFIG_SYS_DDRCMD_NOP,
275 /* item 13, precharge all; item 14, tRP (20ns) */
276 CONFIG_SYS_DDRCMD_PCHG_ALL,
277 CONFIG_SYS_DDRCMD_NOP,
278 /*
279 * item 15, auto refresh (i.e. refresh with CKE held high);
280 * item 16, tRFC (70ns)
281 */
282 CONFIG_SYS_DDRCMD_RFSH,
283 CONFIG_SYS_DDRCMD_NOP,
284 CONFIG_SYS_DDRCMD_NOP,
285 CONFIG_SYS_DDRCMD_NOP,
286 CONFIG_SYS_DDRCMD_NOP,
287 CONFIG_SYS_DDRCMD_NOP,
288 CONFIG_SYS_DDRCMD_NOP,
289 CONFIG_SYS_DDRCMD_NOP,
290 CONFIG_SYS_DDRCMD_NOP,
291 /*
292 * item 17, auto refresh (i.e. refresh with CKE held high);
293 * item 18, tRFC (70ns)
294 */
295 CONFIG_SYS_DDRCMD_RFSH,
296 CONFIG_SYS_DDRCMD_NOP,
297 CONFIG_SYS_DDRCMD_NOP,
298 CONFIG_SYS_DDRCMD_NOP,
299 CONFIG_SYS_DDRCMD_NOP,
300 CONFIG_SYS_DDRCMD_NOP,
301 CONFIG_SYS_DDRCMD_NOP,
302 CONFIG_SYS_DDRCMD_NOP,
303 CONFIG_SYS_DDRCMD_NOP,
304 /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
305 CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
306 CONFIG_SYS_DDRCMD_NOP,
307 /*
308 * item 21, "actually done", but make sure 200 DRAM clock cycles
309 * have passed after DLL reset before READ requests are issued
310 * (200 cycles at 160MHz -> 1.25 usec)
311 */
312 /* EMPTY, optional, we don't do it */
313};
314
315phys_size_t initdram(int board_type)
316{
317 return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
318}
319
320int misc_init_r(void)
321{
322 u32 keys;
323 char *s;
324 int want_recovery;
325
326 /* we use bus I2C-0 for the on-board eeprom */
327 i2c_set_bus_num(0);
328
329 /* setup GPIO directions and initial values */
330 gpio_configure();
331
332 /*
b5992e77 333 * enforce the start of the recovery system when
fcc7fe42
AG		 334 * - the appropriate keys were pressed
335 * - a previous installation was aborted or has failed
336 * - "some" external software told us to
337 */
338 want_recovery = 0;
339 keys = gpio_querykbd();
340 printf("GPIO keyboard status [0x%08X]\n", keys);
fcc7fe42
AG		 341 if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
342 printf("GPIO keyboard requested RECOVERY\n");
fcc7fe42
AG		 343 want_recovery = 1;
344 }
345 s = getenv("install_in_progress");
346 if ((s != NULL) && (*s != '\0')) {
347 printf("previous installation aborted, running RECOVERY\n");
348 want_recovery = 1;
349 }
350 s = getenv("install_failed");
351 if ((s != NULL) && (*s != '\0')) {
352 printf("previous installation FAILED, running RECOVERY\n");
353 want_recovery = 1;
354 }
355 s = getenv("want_recovery");
356 if ((s != NULL) && (*s != '\0')) {
357 printf("running RECOVERY according to the request\n");
358 want_recovery = 1;
359 }
360
361 if (want_recovery)
362 setenv("bootcmd", "run recovery");
363
364 /*
365 * boot the recovery system without waiting; boot the
366 * production system without waiting by default, only
367 * insert a pause (to provide a chance to get a prompt)
368 * when GPIO keys were pressed during power on
369 */
370 if (want_recovery)
371 setenv("bootdelay", "0");
372 else if (!keys)
373 setenv("bootdelay", "0");
374 else
375 setenv("bootdelay", "2");
376
377 /* get the ethernet MAC from I2C EEPROM */
378 mac_read_from_eeprom();
379
380 return 0;
381}
382
383/* setup specific IO pad configuration */
384static iopin_t ioregs_init[] = {
385 { /* LPC CS3 */
386 offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
387 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
388 IO_PIN_FMUX(1) | IO_PIN_DS(2),
389 },
390 { /* LPC CS1 */
391 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
392 IO_PIN_OVER_DRVSTR,
393 IO_PIN_DS(2),
394 },
395 { /* LPC CS2 */
396 offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
397 IO_PIN_OVER_DRVSTR,
398 IO_PIN_DS(2),
399 },
400 { /* LPC CS4, CS5 */
401 offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
402 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
403 IO_PIN_FMUX(1) | IO_PIN_DS(2),
404 },
405 { /* SDHC CLK, CMD, D0, D1, D2, D3 */
406 offsetof(struct ioctrl512x, io_control_pata_ior), 6,
407 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
408 IO_PIN_FMUX(1) | IO_PIN_DS(2),
409 },
410 { /* GPIO keyboard */
411 offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
412 IO_PIN_OVER_FMUX,
413 IO_PIN_FMUX(3),
414 },
415 { /* GPIO DN1 PF, LCD power, DN2 PF */
416 offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
417 IO_PIN_OVER_FMUX,
418 IO_PIN_FMUX(3),
419 },
420 { /* GPIO reset AS-i */
421 offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
422 IO_PIN_OVER_FMUX,
423 IO_PIN_FMUX(3),
424 },
425 { /* GPIO reset safety */
426 offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
427 IO_PIN_OVER_FMUX,
428 IO_PIN_FMUX(3),
429 },
430 { /* GPIO reset netX */
431 offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
432 IO_PIN_OVER_FMUX,
433 IO_PIN_FMUX(3),
434 },
435 { /* GPIO ma2 en */
436 offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
437 IO_PIN_OVER_FMUX,
438 IO_PIN_FMUX(3),
439 },
440 { /* GPIO SD CD, SD WP */
441 offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
442 IO_PIN_OVER_FMUX,
443 IO_PIN_FMUX(3),
444 },
445 { /* FEC RX DV */
446 offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
447 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
448 IO_PIN_FMUX(2) | IO_PIN_DS(2),
449 },
450 { /* GPIO AS-i prog, AS-i done, LCD backlight */
451 offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
452 IO_PIN_OVER_FMUX,
453 IO_PIN_FMUX(3),
454 },
455 { /* GPIO AS-i wdg */
456 offsetof(struct ioctrl512x, io_control_pci_req2), 1,
457 IO_PIN_OVER_FMUX,
458 IO_PIN_FMUX(3),
459 },
460 { /* GPIO safety wdg */
461 offsetof(struct ioctrl512x, io_control_pci_req1), 1,
462 IO_PIN_OVER_FMUX,
463 IO_PIN_FMUX(3),
464 },
465 { /* GPIO netX wdg */
466 offsetof(struct ioctrl512x, io_control_pci_req0), 1,
467 IO_PIN_OVER_FMUX,
468 IO_PIN_FMUX(3),
469 },
470 { /* GPIO IRQ powerfail */
471 offsetof(struct ioctrl512x, io_control_pci_inta), 1,
472 IO_PIN_OVER_FMUX,
473 IO_PIN_FMUX(3),
474 },
475 { /* GPIO AS-i PWRD */
476 offsetof(struct ioctrl512x, io_control_pci_frame), 1,
477 IO_PIN_OVER_FMUX,
478 IO_PIN_FMUX(3),
479 },
480 { /* GPIO LED0, LED1 */
481 offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
482 IO_PIN_OVER_FMUX,
483 IO_PIN_FMUX(3),
484 },
485 { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
486 offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
487 IO_PIN_OVER_FMUX,
488 IO_PIN_FMUX(3),
489 },
490 { /* DIU clk */
491 offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
492 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
493 IO_PIN_FMUX(2) | IO_PIN_DS(2),
494 },
495 { /* FEC TX ER, CRS */
496 offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
497 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
498 IO_PIN_FMUX(1) | IO_PIN_DS(2),
499 },
500 { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
501 offsetof(struct ioctrl512x, io_control_irq0), 1,
502 IO_PIN_OVER_FMUX,
503 IO_PIN_FMUX(3),
504 },
505 { /*
506 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
507 * rdx 3-0, mdio, rx clk
508 */
509 offsetof(struct ioctrl512x, io_control_psc0_0), 15,
510 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
511 IO_PIN_FMUX(1) | IO_PIN_DS(2),
512 },
513 /* optional: make sure PSC3 remains the serial console */
514 { /* LPC CS6 */
515 offsetof(struct ioctrl512x, io_control_psc3_4), 1,
516 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
517 IO_PIN_FMUX(1) | IO_PIN_DS(2),
518 },
519 /* make sure PSC4 remains available for SPI,
520 *BUT* PSC4_1 is a GPIO kind of SS! */
521 { /* enforce drive strength on the SPI pin */
522 offsetof(struct ioctrl512x, io_control_psc4_0), 5,
523 IO_PIN_OVER_DRVSTR,
524 IO_PIN_DS(2),
525 },
526 {
527 offsetof(struct ioctrl512x, io_control_psc4_1), 1,
528 IO_PIN_OVER_FMUX,
529 IO_PIN_FMUX(3),
530 },
531 /* optional: make sure PSC5 remains available for SPI */
532 { /* enforce drive strength on the SPI pin */
533 offsetof(struct ioctrl512x, io_control_psc5_0), 5,
534 IO_PIN_OVER_DRVSTR,
535 IO_PIN_DS(1),
536 },
537 { /* LPC TSIZ1 */
538 offsetof(struct ioctrl512x, io_control_psc6_0), 1,
539 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
540 IO_PIN_FMUX(1) | IO_PIN_DS(2),
541 },
542 { /* DIU hsync */
543 offsetof(struct ioctrl512x, io_control_psc6_1), 1,
544 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
545 IO_PIN_FMUX(2) | IO_PIN_DS(1),
546 },
547 { /* DIU vsync */
548 offsetof(struct ioctrl512x, io_control_psc6_4), 1,
549 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
550 IO_PIN_FMUX(2) | IO_PIN_DS(1),
551 },
552 { /* PSC7, part of DIU RGB */
553 offsetof(struct ioctrl512x, io_control_psc7_0), 2,
554 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
555 IO_PIN_FMUX(2) | IO_PIN_DS(1),
556 },
557 { /* PSC7, safety UART */
558 offsetof(struct ioctrl512x, io_control_psc7_2), 2,
559 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
560 IO_PIN_FMUX(0) | IO_PIN_DS(1),
561 },
562 { /* DIU (part of) RGB[] */
563 offsetof(struct ioctrl512x, io_control_psc8_3), 16,
564 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
565 IO_PIN_FMUX(2) | IO_PIN_DS(1),
566 },
567 { /* DIU data enable */
568 offsetof(struct ioctrl512x, io_control_psc11_4), 1,
569 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
570 IO_PIN_FMUX(2) | IO_PIN_DS(1),
571 },
572 /* reduce LPB drive strength for improved EMI */
573 { /* LPC OE, LPC RW */
574 offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
575 IO_PIN_OVER_DRVSTR,
576 IO_PIN_DS(2),
577 },
578 { /* LPC AX03 through LPC AD00 */
579 offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
580 IO_PIN_OVER_DRVSTR,
581 IO_PIN_DS(2),
582 },
583 { /* LPC CS5 */
584 offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
585 IO_PIN_OVER_DRVSTR,
586 IO_PIN_DS(2),
587 },
588 { /* SDHC CLK */
589 offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
590 IO_PIN_OVER_DRVSTR,
591 IO_PIN_DS(2),
592 },
593 { /* SDHC DATA */
594 offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
595 IO_PIN_OVER_DRVSTR,
596 IO_PIN_DS(2),
597 },
598};
599
600int checkboard(void)
601{
602 puts("Board: ifm AC14xx\n");
603
604 /* initialize function mux & slew rate IO inter alia on IO Pins */
605 iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
606
607 return 0;
608}
609
610#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
611void ft_board_setup(void *blob, bd_t *bd)
612{
613 ft_cpu_setup(blob, bd);
614}
615#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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