projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 3313e0e2 MJ |
1 | /* |
| 2 | * (C) Copyright 2008 | |
| 3 | * Mark Jonas <mark.jonas@de.bosch.com> | |
| 4 | * | |
| 5 | * (C) Copyright 2007 | |
| 6 | * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
| 7 | * | |
| 8 | * board/mpr2/lowlevel_init.S | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or | |
| 11 | * modify it under the terms of the GNU General Public License as | |
| 12 | * published by the Free Software Foundation; either version 2 of | |
| 13 | * the License, or (at your option) any later version. | |
| 14 | * | |
| 15 | * This program is distributed in the hope that it will be useful, | |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 18 | * GNU General Public License for more details. | |
| 19 | * | |
| 20 | * You should have received a copy of the GNU General Public License | |
| 21 | * along with this program; if not, write to the Free Software | |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 23 | * MA 02111-1307 USA | |
| 24 | */ | |
| f7e78f3b | 25 | #include <asm/macro.h> |
| 3313e0e2 MJ |
26 | |
| 27 | .global lowlevel_init | |
| 28 | ||
| 29 | .text | |
| 30 | .align 2 | |
| 31 | ||
| 32 | lowlevel_init: | |
| 33 | ||
| 34 | /* | |
| 35 | * Set frequency multipliers and dividers in FRQCR. | |
| 36 | */ | |
| f7e78f3b | 37 | write16 WTCSR_A, WTCSR_D |
| 3313e0e2 | 38 | |
| f7e78f3b | 39 | write16 WTCNT_A, WTCNT_D |
| 3313e0e2 | 40 | |
| f7e78f3b | 41 | write16 FRQCR_A, FRQCR_D |
| 3313e0e2 MJ |
42 | |
| 43 | /* | |
| 44 | * Setup CS0 (Flash). | |
| 45 | */ | |
| f7e78f3b | 46 | write32 CS0BCR_A, CS0BCR_D |
| 3313e0e2 | 47 | |
| f7e78f3b | 48 | write32 CS0WCR_A, CS0WCR_D |
| 3313e0e2 MJ |
49 | |
| 50 | /* | |
| 51 | * Setup CS3 (SDRAM). | |
| 52 | */ | |
| f7e78f3b | 53 | write32 CS3BCR_A, CS3BCR_D |
| 3313e0e2 | 54 | |
| f7e78f3b | 55 | write32 CS3WCR_A, CS3WCR_D |
| 3313e0e2 | 56 | |
| f7e78f3b | 57 | write32 SDCR_A, SDCR_D1 |
| 3313e0e2 | 58 | |
| f7e78f3b | 59 | write32 RTCSR_A, RTCSR_D |
| 3313e0e2 | 60 | |
| f7e78f3b | 61 | write32 RTCNT_A, RTCNT_D |
| 3313e0e2 | 62 | |
| f7e78f3b | 63 | write32 RTCOR_A, RTCOR_D |
| 3313e0e2 | 64 | |
| f7e78f3b | 65 | write32 SDCR_A, SDCR_D2 |
| 3313e0e2 MJ |
66 | |
| 67 | mov.l SDMR3_A, r1 | |
| 68 | mov.l SDMR3_D, r0 | |
| 69 | add r0, r1 | |
| 70 | mov #0, r0 | |
| 71 | mov.w r0, @r1 | |
| 72 | ||
| 73 | rts | |
| 74 | nop | |
| 75 | ||
| 76 | .align 4 | |
| 77 | ||
| 78 | /* | |
| 79 | * Configuration for MPR2 A.3 through A.7 | |
| 80 | */ | |
| 81 | ||
| 82 | /* | |
| 83 | * PLL Settings | |
| 84 | */ | |
| 85 | FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ | |
| 86 | WTCNT_D: .long 0x5A00 /* start counting at zero */ | |
| 87 | WTCSR_D: .long 0xA507 /* divide by 4096 */ | |
| 88 | ||
| 89 | /* | |
| 90 | * Spansion S29GL256N11 @ 48 MHz | |
| 91 | */ | |
| e4430779 JCPV |
92 | /* 1 idle cycle inserted, normal space, 16 bit */ |
| 93 | CS0BCR_D: .long 0x12490400 | |
| 94 | /* tSW=0.5ck, 6 wait cycles, NO external wait, tHW=0.5ck */ | |
| 95 | CS0WCR_D: .long 0x00000340 | |
| 3313e0e2 MJ |
96 | |
| 97 | /* | |
| 98 | * Samsung K4S511632B-UL75 @ 48 MHz | |
| 99 | * Micron MT48LC32M16A2-75 @ 48 MHz | |
| 100 | */ | |
| e4430779 JCPV |
101 | /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */ |
| 102 | CS3BCR_D: .long 0x10004400 | |
| 103 | /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */ | |
| 104 | CS3WCR_D: .long 0x00000091 | |
| 105 | /* no refresh, 13 rows, 10 cols, NO bank active mode */ | |
| 106 | SDCR_D1: .long 0x00000012 | |
| 107 | SDCR_D2: .long 0x00000812 /* refresh */ | |
| 108 | RTCSR_D: .long 0xA55A0008 /* 1/4, once */ | |
| 109 | RTCNT_D: .long 0xA55A005D /* count 93 */ | |
| 110 | RTCOR_D: .long 0xa55a005d /* count 93 */ | |
| 111 | /* mode register CL2, burst read and SINGLE WRITE */ | |
| 112 | SDMR3_D: .long 0x440 | |
| 3313e0e2 MJ |
113 | |
| 114 | /* | |
| 115 | * Registers | |
| 116 | */ | |
| 117 | ||
| 118 | FRQCR_A: .long 0xA415FF80 | |
| 119 | WTCNT_A: .long 0xA415FF84 | |
| 120 | WTCSR_A: .long 0xA415FF86 | |
| 121 | ||
| 122 | #define BSC_BASE 0xA4FD0000 | |
| 123 | CS0BCR_A: .long BSC_BASE + 0x04 | |
| 124 | CS3BCR_A: .long BSC_BASE + 0x0C | |
| 125 | CS0WCR_A: .long BSC_BASE + 0x24 | |
| 126 | CS3WCR_A: .long BSC_BASE + 0x2C | |
| 127 | SDCR_A: .long BSC_BASE + 0x44 | |
| 128 | RTCSR_A: .long BSC_BASE + 0x48 | |
| 129 | RTCNT_A: .long BSC_BASE + 0x4C | |
| 130 | RTCOR_A: .long BSC_BASE + 0x50 | |
| 131 | SDMR3_A: .long BSC_BASE + 0x5000 |