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at91: nand: switch atmel_nand to generic GPIO API
[people/ms/u-boot.git] / board / ronetix / pm9263 / pm9263.c
CommitLineData
f0a2c7b4
II		 1/*
2 * (C) Copyright 2007-2008
c9e798d3 3 * Stelian Pop <stelian@popies.net>
f0a2c7b4
II		 4 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
1a459660 8 * SPDX-License-Identifier: GPL-2.0+
f0a2c7b4
II		 9 */
10
11#include <common.h>
12#include <asm/sizes.h>
684a567a 13#include <asm/io.h>
ac45bb16 14#include <asm/gpio.h>
f0a2c7b4
II		 15#include <asm/arch/at91sam9_smc.h>
16#include <asm/arch/at91_common.h>
17#include <asm/arch/at91_pmc.h>
18#include <asm/arch/at91_rstc.h>
20d98c2c 19#include <asm/arch/at91_matrix.h>
f0a2c7b4 20#include <asm/arch/clk.h>
684a567a 21#include <asm/arch/gpio.h>
f0a2c7b4
II		 22#include <lcd.h>
23#include <atmel_lcdc.h>
24#include <dataflash.h>
25#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
26#include <net.h>
27#endif
28#include <netdev.h>
29
30DECLARE_GLOBAL_DATA_PTR;
31
32/* ------------------------------------------------------------------------- */
33/*
34 * Miscelaneous platform dependent initialisations
35 */
36
37#ifdef CONFIG_CMD_NAND
38static void pm9263_nand_hw_init(void)
39{
40 unsigned long csa;
684a567a
AD		 41 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
42 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
f0a2c7b4
II		 43
44 /* Enable CS3 */
20d98c2c
AD		 45 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
46 writel(csa, &matrix->csa[0]);
f0a2c7b4
II		 47
48 /* Configure SMC CS3 for NAND/SmartMedia */
20d98c2c
AD		 49 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
50 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
51 &smc->cs[3].setup);
52
53 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
54 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
55 &smc->cs[3].pulse);
56
57 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
58 &smc->cs[3].cycle);
59
60 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
61 AT91_SMC_MODE_EXNW_DISABLE |
f0a2c7b4 62#ifdef CONFIG_SYS_NAND_DBW_16
20d98c2c 63 AT91_SMC_MODE_DBW_16 |
f0a2c7b4 64#else /* CONFIG_SYS_NAND_DBW_8 */
20d98c2c 65 AT91_SMC_MODE_DBW_8 |
f0a2c7b4 66#endif
20d98c2c
AD		 67 AT91_SMC_MODE_TDF_CYCLE(2),
68 &smc->cs[3].mode);
f0a2c7b4
II		 69
70 /* Configure RDY/BSY */
ac45bb16 71 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
f0a2c7b4
II		 72
73 /* Enable NandFlash */
ac45bb16 74 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
f0a2c7b4
II		 75}
76#endif
77
78#ifdef CONFIG_MACB
79static void pm9263_macb_hw_init(void)
80{
684a567a 81 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
20d98c2c 82
f0a2c7b4
II		 83 /*
84 * PB27 enables the 50MHz oscillator for Ethernet PHY
85 * 1 - enable
86 * 0 - disable
87 */
20d98c2c
AD		 88 at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
89 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
f0a2c7b4
II		 90
91 /* Enable clock */
684a567a 92 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
f0a2c7b4
II		 93
94 /*
95 * Disable pull-up on:
96 * RXDV (PC25) => PHY normal mode (not Test mode)
97 * ERX0 (PE25) => PHY ADDR0
98 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
99 *
100 * PHY has internal pull-down
101 */
f0a2c7b4 102
20d98c2c
AD		 103 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
104 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
105 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
f0a2c7b4
II		 106
107 /* Re-enable pull-up */
20d98c2c
AD		 108 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
109 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
110 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
f0a2c7b4
II		 111
112 at91_macb_hw_init();
113}
114#endif
115
116#ifdef CONFIG_LCD
117vidinfo_t panel_info = {
118 vl_col: 240,
119 vl_row: 320,
120 vl_clk: 4965000,
121 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
122 ATMEL_LCDC_INVFRAME_INVERTED,
123 vl_bpix: 3,
124 vl_tft: 1,
125 vl_hsync_len: 5,
126 vl_left_margin: 1,
127 vl_right_margin:33,
128 vl_vsync_len: 1,
129 vl_upper_margin:1,
130 vl_lower_margin:0,
684a567a 131 mmio: ATMEL_BASE_LCDC,
f0a2c7b4
II		 132};
133
134void lcd_enable(void)
135{
20d98c2c 136 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
f0a2c7b4
II		 137}
138
139void lcd_disable(void)
140{
20d98c2c 141 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
f0a2c7b4
II		 142}
143
144#ifdef CONFIG_LCD_IN_PSRAM
145
20d98c2c 146#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
f0a2c7b4
II		 147#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
148
149/* Initialize the PSRAM memory */
150static int pm9263_lcd_hw_psram_init(void)
151{
7a11c7f9 152 unsigned long csa;
684a567a
AD		 153 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
154 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
7a11c7f9
JCPV		 155
156 /* Enable CS3 3.3v, no pull-ups */
20d98c2c
AD		 157 csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
158 AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
159
160 writel(csa, &matrix->csa[1]);
7a11c7f9
JCPV		 161
162 /* Configure SMC1 CS0 for PSRAM - 16-bit */
20d98c2c
AD		 163 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
164 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
165 &smc->cs[0].setup);
166
167 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
168 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
169 &smc->cs[0].pulse);
170
171 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
172 &smc->cs[0].cycle);
173
174 writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
175 &smc->cs[0].mode);
f0a2c7b4
II		 176
177 /* setup PB29 as output */
20d98c2c 178 at91_set_pio_output(PSRAM_CRE_PIN, 1);
f0a2c7b4 179
20d98c2c 180 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
f0a2c7b4
II		 181
182 /* PSRAM: write BCR */
0a59b711
AG		 183 readw(PSRAM_CTRL_REG);
184 readw(PSRAM_CTRL_REG);
f0a2c7b4
II		 185 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
186 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
187
188 /* write RCR of the PSRAM */
0a59b711
AG		 189 readw(PSRAM_CTRL_REG);
190 readw(PSRAM_CTRL_REG);
f0a2c7b4
II		 191 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
192 /* set RCR; 0x10-async mode,0x90-page mode */
193 writew(0x90, PSRAM_CTRL_REG);
194
195 /*
196 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
197 * MT45W2M16B - CRE must be 0
198 * MT45W2M16A - CRE must be 1
199 */
200 writew(0x1234, PHYS_PSRAM);
201 writew(0x5678, PHYS_PSRAM + 2);
202
203 /* test if the chip is MT45W2M16B */
204 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
205 /* try with CRE=1 (MT45W2M16A) */
20d98c2c 206 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
f0a2c7b4
II		 207
208 /* write RCR of the PSRAM */
0a59b711
AG		 209 readw(PSRAM_CTRL_REG);
210 readw(PSRAM_CTRL_REG);
f0a2c7b4
II		 211 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
212 /* set RCR;0x10-async mode,0x90-page mode */
213 writew(0x90, PSRAM_CTRL_REG);
214
215
216 writew(0x1234, PHYS_PSRAM);
217 writew(0x5678, PHYS_PSRAM+2);
218 if ((readw(PHYS_PSRAM) != 0x1234)
20d98c2c 219 || (readw(PHYS_PSRAM + 2) != 0x5678))
f0a2c7b4
II		 220 return 1;
221
222 }
223
224 /* Bus matrix */
20d98c2c
AD		 225 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
226 writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
f0a2c7b4
II		 227
228 return 0;
229}
230#endif
231
232static void pm9263_lcd_hw_init(void)
233{
684a567a 234 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
20d98c2c
AD		 235
236 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
237 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
238 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
239 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
240 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
241 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
242 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
243 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
244 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
245 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
246 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
247 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
248 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
249 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
250 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
251 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
252 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
253 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
254 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
255 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
256 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
257 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
258 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
259
684a567a 260 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
f0a2c7b4
II		 261
262 /* Power Control */
20d98c2c
AD		 263 at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
264 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
f0a2c7b4
II		 265
266#ifdef CONFIG_LCD_IN_PSRAM
267 /* initialize te PSRAM */
268 int stat = pm9263_lcd_hw_psram_init();
269
684a567a 270 gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
f0a2c7b4 271#else
684a567a 272 gd->fb_base = ATMEL_BASE_SRAM0;
f0a2c7b4
II		 273#endif
274
275}
276
277#ifdef CONFIG_LCD_INFO
278#include <nand.h>
279#include <version.h>
280
281extern flash_info_t flash_info[];
282
283void lcd_show_board_info(void)
284{
285 ulong dram_size, nand_size, flash_size, dataflash_size;
286 int i;
287 char temp[32];
288
289 lcd_printf ("%s\n", U_BOOT_VERSION);
290 lcd_printf ("(C) 2009 Ronetix GmbH\n");
291 lcd_printf ("support@ronetix.at\n");
292 lcd_printf ("%s CPU at %s MHz",
7c966a8b 293 CONFIG_SYS_AT91_CPU_NAME,
f0a2c7b4
II		 294 strmhz(temp, get_cpu_clk_rate()));
295
296 dram_size = 0;
297 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
298 dram_size += gd->bd->bi_dram[i].size;
299
300 nand_size = 0;
301 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
302 nand_size += nand_info[i].size;
303
304 flash_size = 0;
305 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
306 flash_size += flash_info[i].size;
307
308 dataflash_size = 0;
309 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
310 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
311 dataflash_info[i].Device.pages_size;
312
313 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
314 "4 MB PSRAM, %ld MB DataFlash\n",
315 dram_size >> 20,
316 nand_size >> 20,
317 flash_size >> 20,
318 dataflash_size >> 20);
319}
320#endif /* CONFIG_LCD_INFO */
321
322#endif /* CONFIG_LCD */
323
52b26016 324int board_early_init_f(void)
f0a2c7b4 325{
684a567a 326 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
20d98c2c 327
52b26016
AD		 328 /* Enable clocks for all PIOs */
329 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
330 (1 << ATMEL_ID_PIOCDE),
20d98c2c 331 &pmc->pcer);
f0a2c7b4 332
52b26016
AD		 333 at91_seriald_hw_init();
334
335 return 0;
336}
337
338int board_init(void)
339{
340 /* arch number of AT91SAM9263EK-Board */
341 gd->bd->bi_arch_number = MACH_TYPE_PM9263;
342
f0a2c7b4
II		 343 /* adress of boot parameters */
344 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
345
f0a2c7b4
II		 346#ifdef CONFIG_CMD_NAND
347 pm9263_nand_hw_init();
348#endif
349#ifdef CONFIG_HAS_DATAFLASH
350 at91_spi0_hw_init(1 << 0);
351#endif
352#ifdef CONFIG_MACB
353 pm9263_macb_hw_init();
354#endif
355#ifdef CONFIG_USB_OHCI_NEW
356 at91_uhp_hw_init();
357#endif
358#ifdef CONFIG_LCD
359 pm9263_lcd_hw_init();
360#endif
361 return 0;
362}
363
364int dram_init(void)
9a2a05a4
AD		 365{
366 /* dram_init must store complete ramsize in gd->ram_size */
a55d23cc 367 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
9a2a05a4
AD		 368 PHYS_SDRAM_SIZE);
369 return 0;
370}
371
372void dram_init_banksize(void)
f0a2c7b4
II		 373{
374 gd->bd->bi_dram[0].start = PHYS_SDRAM;
375 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
f0a2c7b4
II		 376}
377
378#ifdef CONFIG_RESET_PHY_R
379void reset_phy(void)
380{
f0a2c7b4
II		 381}
382#endif
383
384int board_eth_init(bd_t *bis)
385{
386 int rc = 0;
387#ifdef CONFIG_MACB
684a567a 388 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
f0a2c7b4
II		 389#endif
390 return rc;
391}
392
393#ifdef CONFIG_DISPLAY_BOARDINFO
394int checkboard (void)
395{
396 char *ss;
f0a2c7b4
II		 397
398 printf ("Board : Ronetix PM9263\n");
f0a2c7b4
II		 399
400 switch (gd->fb_base) {
401 case PHYS_PSRAM:
402 ss = "(PSRAM)";
403 break;
404
684a567a 405 case ATMEL_BASE_SRAM0:
f0a2c7b4
II		 406 ss = "(Internal SRAM)";
407 break;
408
409 default:
410 ss = "";
411 break;
412 }
413 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );
414
415 printf ("\n");
416 return 0;
417}
418#endif
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