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b79316f2 SR |
1 | /* |
2 | * Copyright (C) 2005 Sandburst Corporation | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Ported from cpu/ppc4xx/i2c.c by AS HARNOIS by | |
25 | * Travis B. Sawyer | |
26 | * Sandburst Corporation. | |
27 | */ | |
28 | #include <common.h> | |
29 | #include <ppc4xx.h> | |
79b2d0bb | 30 | #include <4xx_i2c.h> |
b79316f2 | 31 | #include <i2c.h> |
b79316f2 SR |
32 | #include <command.h> |
33 | #include "ppc440gx_i2c.h" | |
34 | ||
35 | #ifdef CONFIG_I2C_BUS1 | |
36 | ||
b79316f2 SR |
37 | #define IIC_OK 0 |
38 | #define IIC_NOK 1 | |
39 | #define IIC_NOK_LA 2 /* Lost arbitration */ | |
40 | #define IIC_NOK_ICT 3 /* Incomplete transfer */ | |
41 | #define IIC_NOK_XFRA 4 /* Transfer aborted */ | |
42 | #define IIC_NOK_DATA 5 /* No data in buffer */ | |
43 | #define IIC_NOK_TOUT 6 /* Transfer timeout */ | |
44 | ||
45 | #define IIC_TIMEOUT 1 /* 1 second */ | |
6d0f6bcf JCPV |
46 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
47 | static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES; | |
b79316f2 SR |
48 | #endif |
49 | ||
50 | static void _i2c_bus1_reset (void) | |
51 | { | |
52 | int i, status; | |
53 | ||
54 | /* Reset status register */ | |
55 | /* write 1 in SCMP and IRQA to clear these fields */ | |
56 | out8 (IIC_STS1, 0x0A); | |
57 | ||
58 | /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */ | |
59 | out8 (IIC_EXTSTS1, 0x8F); | |
60 | __asm__ volatile ("eieio"); | |
61 | ||
62 | /* | |
63 | * Get current state, reset bus | |
64 | * only if no transfers are pending. | |
65 | */ | |
66 | i = 10; | |
67 | do { | |
68 | /* Get status */ | |
69 | status = in8 (IIC_STS1); | |
70 | udelay (500); /* 500us */ | |
71 | i--; | |
72 | } while ((status & IIC_STS_PT) && (i > 0)); | |
73 | /* Soft reset controller */ | |
74 | status = in8 (IIC_XTCNTLSS1); | |
75 | out8 (IIC_XTCNTLSS1, (status | IIC_XTCNTLSS_SRST)); | |
76 | __asm__ volatile ("eieio"); | |
77 | ||
78 | /* make sure where in initial state, data hi, clock hi */ | |
79 | out8 (IIC_DIRECTCNTL1, 0xC); | |
80 | for (i = 0; i < 10; i++) { | |
81 | if ((in8 (IIC_DIRECTCNTL1) & 0x3) != 0x3) { | |
82 | /* clock until we get to known state */ | |
83 | out8 (IIC_DIRECTCNTL1, 0x8); /* clock lo */ | |
84 | udelay (100); /* 100us */ | |
85 | out8 (IIC_DIRECTCNTL1, 0xC); /* clock hi */ | |
86 | udelay (100); /* 100us */ | |
87 | } else { | |
88 | break; | |
89 | } | |
90 | } | |
91 | /* send start condition */ | |
92 | out8 (IIC_DIRECTCNTL1, 0x4); | |
93 | udelay (1000); /* 1ms */ | |
94 | /* send stop condition */ | |
95 | out8 (IIC_DIRECTCNTL1, 0xC); | |
96 | udelay (1000); /* 1ms */ | |
97 | /* Unreset controller */ | |
98 | out8 (IIC_XTCNTLSS1, (status & ~IIC_XTCNTLSS_SRST)); | |
99 | udelay (1000); /* 1ms */ | |
100 | } | |
101 | ||
102 | void i2c1_init (int speed, int slaveadd) | |
103 | { | |
104 | sys_info_t sysInfo; | |
105 | unsigned long freqOPB; | |
106 | int val, divisor; | |
107 | ||
6d0f6bcf | 108 | #ifdef CONFIG_SYS_I2C_INIT_BOARD |
b79316f2 SR |
109 | /* call board specific i2c bus reset routine before accessing the */ |
110 | /* environment, which might be in a chip on that bus. For details */ | |
111 | /* about this problem see doc/I2C_Edge_Conditions. */ | |
112 | i2c_init_board(); | |
113 | #endif | |
114 | ||
115 | /* Handle possible failed I2C state */ | |
116 | /* FIXME: put this into i2c_init_board()? */ | |
117 | _i2c_bus1_reset (); | |
118 | ||
119 | /* clear lo master address */ | |
120 | out8 (IIC_LMADR1, 0); | |
121 | ||
122 | /* clear hi master address */ | |
123 | out8 (IIC_HMADR1, 0); | |
124 | ||
125 | /* clear lo slave address */ | |
126 | out8 (IIC_LSADR1, 0); | |
127 | ||
128 | /* clear hi slave address */ | |
129 | out8 (IIC_HSADR1, 0); | |
130 | ||
131 | /* Clock divide Register */ | |
132 | /* get OPB frequency */ | |
133 | get_sys_info (&sysInfo); | |
134 | freqOPB = sysInfo.freqPLB / sysInfo.pllOpbDiv; | |
135 | /* set divisor according to freqOPB */ | |
136 | divisor = (freqOPB - 1) / 10000000; | |
137 | if (divisor == 0) | |
138 | divisor = 1; | |
139 | out8 (IIC_CLKDIV1, divisor); | |
140 | ||
141 | /* no interrupts */ | |
142 | out8 (IIC_INTRMSK1, 0); | |
143 | ||
144 | /* clear transfer count */ | |
145 | out8 (IIC_XFRCNT1, 0); | |
146 | ||
147 | /* clear extended control & stat */ | |
148 | /* write 1 in SRC SRS SWC SWS to clear these fields */ | |
149 | out8 (IIC_XTCNTLSS1, 0xF0); | |
150 | ||
151 | /* Mode Control Register | |
152 | Flush Slave/Master data buffer */ | |
153 | out8 (IIC_MDCNTL1, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB); | |
154 | __asm__ volatile ("eieio"); | |
155 | ||
156 | ||
157 | val = in8(IIC_MDCNTL1); | |
158 | __asm__ volatile ("eieio"); | |
159 | ||
160 | /* Ignore General Call, slave transfers are ignored, | |
161 | disable interrupts, exit unknown bus state, enable hold | |
162 | SCL | |
163 | 100kHz normaly or FastMode for 400kHz and above | |
164 | */ | |
165 | ||
166 | val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL; | |
167 | if( speed >= 400000 ){ | |
168 | val |= IIC_MDCNTL_FSM; | |
169 | } | |
170 | out8 (IIC_MDCNTL1, val); | |
171 | ||
172 | /* clear control reg */ | |
173 | out8 (IIC_CNTL1, 0x00); | |
174 | __asm__ volatile ("eieio"); | |
175 | ||
176 | } | |
177 | ||
178 | /* | |
179 | This code tries to use the features of the 405GP i2c | |
180 | controller. It will transfer up to 4 bytes in one pass | |
181 | on the loop. It only does out8(lbz) to the buffer when it | |
182 | is possible to do out16(lhz) transfers. | |
183 | ||
184 | cmd_type is 0 for write 1 for read. | |
185 | ||
186 | addr_len can take any value from 0-255, it is only limited | |
187 | by the char, we could make it larger if needed. If it is | |
188 | 0 we skip the address write cycle. | |
189 | ||
190 | Typical case is a Write of an addr followd by a Read. The | |
191 | IBM FAQ does not cover this. On the last byte of the write | |
192 | we don't set the creg CHT bit, and on the first bytes of the | |
193 | read we set the RPST bit. | |
194 | ||
195 | It does not support address only transfers, there must be | |
196 | a data part. If you want to write the address yourself, put | |
197 | it in the data pointer. | |
198 | ||
199 | It does not support transfer to/from address 0. | |
200 | ||
201 | It does not check XFRCNT. | |
202 | */ | |
203 | static | |
204 | int i2c_transfer1(unsigned char cmd_type, | |
205 | unsigned char chip, | |
206 | unsigned char addr[], | |
207 | unsigned char addr_len, | |
208 | unsigned char data[], | |
209 | unsigned short data_len ) | |
210 | { | |
211 | unsigned char* ptr; | |
212 | int reading; | |
213 | int tran,cnt; | |
214 | int result; | |
215 | int status; | |
216 | int i; | |
217 | uchar creg; | |
218 | ||
219 | if( data == 0 || data_len == 0 ){ | |
220 | /*Don't support data transfer of no length or to address 0*/ | |
221 | printf( "i2c_transfer: bad call\n" ); | |
222 | return IIC_NOK; | |
223 | } | |
224 | if( addr && addr_len ){ | |
225 | ptr = addr; | |
226 | cnt = addr_len; | |
227 | reading = 0; | |
228 | }else{ | |
229 | ptr = data; | |
230 | cnt = data_len; | |
231 | reading = cmd_type; | |
232 | } | |
233 | ||
234 | /*Clear Stop Complete Bit*/ | |
235 | out8(IIC_STS1,IIC_STS_SCMP); | |
236 | /* Check init */ | |
237 | i=10; | |
238 | do { | |
239 | /* Get status */ | |
240 | status = in8(IIC_STS1); | |
241 | __asm__ volatile("eieio"); | |
242 | i--; | |
243 | } while ((status & IIC_STS_PT) && (i>0)); | |
244 | ||
245 | if (status & IIC_STS_PT) { | |
246 | result = IIC_NOK_TOUT; | |
247 | return(result); | |
248 | } | |
249 | /*flush the Master/Slave Databuffers*/ | |
250 | out8(IIC_MDCNTL1, ((in8(IIC_MDCNTL1))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB)); | |
251 | /*need to wait 4 OPB clocks? code below should take that long*/ | |
252 | ||
253 | /* 7-bit adressing */ | |
254 | out8(IIC_HMADR1,0); | |
255 | out8(IIC_LMADR1, chip); | |
256 | __asm__ volatile("eieio"); | |
257 | ||
258 | tran = 0; | |
259 | result = IIC_OK; | |
260 | creg = 0; | |
261 | ||
262 | while ( tran != cnt && (result == IIC_OK)) { | |
263 | int bc,j; | |
264 | ||
265 | /* Control register = | |
266 | Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start, | |
267 | Transfer is a sequence of transfers | |
268 | */ | |
269 | creg |= IIC_CNTL_PT; | |
270 | ||
271 | bc = (cnt - tran) > 4 ? 4 : | |
272 | cnt - tran; | |
273 | creg |= (bc-1)<<4; | |
274 | /* if the real cmd type is write continue trans*/ | |
275 | if ( (!cmd_type && (ptr == addr)) || ((tran+bc) != cnt) ) | |
276 | creg |= IIC_CNTL_CHT; | |
277 | ||
278 | if (reading) | |
279 | creg |= IIC_CNTL_READ; | |
280 | else { | |
281 | for(j=0; j<bc; j++) { | |
282 | /* Set buffer */ | |
283 | out8(IIC_MDBUF1,ptr[tran+j]); | |
284 | __asm__ volatile("eieio"); | |
285 | } | |
286 | } | |
287 | out8(IIC_CNTL1, creg ); | |
288 | __asm__ volatile("eieio"); | |
289 | ||
290 | /* Transfer is in progress | |
291 | we have to wait for upto 5 bytes of data | |
292 | 1 byte chip address+r/w bit then bc bytes | |
293 | of data. | |
294 | udelay(10) is 1 bit time at 100khz | |
295 | Doubled for slop. 20 is too small. | |
296 | */ | |
297 | i=2*5*8; | |
298 | do { | |
299 | /* Get status */ | |
300 | status = in8(IIC_STS1); | |
301 | __asm__ volatile("eieio"); | |
302 | udelay (10); | |
303 | i--; | |
304 | } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) | |
305 | && (i>0)); | |
306 | ||
307 | if (status & IIC_STS_ERR) { | |
308 | result = IIC_NOK; | |
309 | status = in8 (IIC_EXTSTS1); | |
310 | /* Lost arbitration? */ | |
311 | if (status & IIC_EXTSTS_LA) | |
312 | result = IIC_NOK_LA; | |
313 | /* Incomplete transfer? */ | |
314 | if (status & IIC_EXTSTS_ICT) | |
315 | result = IIC_NOK_ICT; | |
316 | /* Transfer aborted? */ | |
317 | if (status & IIC_EXTSTS_XFRA) | |
318 | result = IIC_NOK_XFRA; | |
319 | } else if ( status & IIC_STS_PT) { | |
320 | result = IIC_NOK_TOUT; | |
321 | } | |
322 | /* Command is reading => get buffer */ | |
323 | if ((reading) && (result == IIC_OK)) { | |
324 | /* Are there data in buffer */ | |
325 | if (status & IIC_STS_MDBS) { | |
326 | /* | |
327 | even if we have data we have to wait 4OPB clocks | |
328 | for it to hit the front of the FIFO, after that | |
329 | we can just read. We should check XFCNT here and | |
330 | if the FIFO is full there is no need to wait. | |
331 | */ | |
332 | udelay (1); | |
333 | for(j=0;j<bc;j++) { | |
334 | ptr[tran+j] = in8(IIC_MDBUF1); | |
335 | __asm__ volatile("eieio"); | |
336 | } | |
337 | } else | |
338 | result = IIC_NOK_DATA; | |
339 | } | |
340 | creg = 0; | |
341 | tran+=bc; | |
342 | if( ptr == addr && tran == cnt ) { | |
343 | ptr = data; | |
344 | cnt = data_len; | |
345 | tran = 0; | |
346 | reading = cmd_type; | |
347 | if( reading ) | |
348 | creg = IIC_CNTL_RPST; | |
349 | } | |
350 | } | |
351 | return (result); | |
352 | } | |
353 | ||
354 | int i2c_probe1 (uchar chip) | |
355 | { | |
356 | uchar buf[1]; | |
357 | ||
358 | buf[0] = 0; | |
359 | ||
360 | /* | |
361 | * What is needed is to send the chip address and verify that the | |
362 | * address was <ACK>ed (i.e. there was a chip at that address which | |
363 | * drove the data line low). | |
364 | */ | |
365 | return(i2c_transfer1 (1, chip << 1, 0,0, buf, 1) != 0); | |
366 | } | |
367 | ||
368 | ||
369 | int i2c_read1 (uchar chip, uint addr, int alen, uchar * buffer, int len) | |
370 | { | |
371 | uchar xaddr[4]; | |
372 | int ret; | |
373 | ||
374 | if ( alen > 4 ) { | |
375 | printf ("I2C read: addr len %d not supported\n", alen); | |
376 | return 1; | |
377 | } | |
378 | ||
379 | if ( alen > 0 ) { | |
380 | xaddr[0] = (addr >> 24) & 0xFF; | |
381 | xaddr[1] = (addr >> 16) & 0xFF; | |
382 | xaddr[2] = (addr >> 8) & 0xFF; | |
383 | xaddr[3] = addr & 0xFF; | |
384 | } | |
385 | ||
386 | ||
6d0f6bcf | 387 | #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
b79316f2 SR |
388 | /* |
389 | * EEPROM chips that implement "address overflow" are ones | |
390 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of | |
391 | * address and the extra bits end up in the "chip address" | |
392 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like | |
393 | * four 256 byte chips. | |
394 | * | |
395 | * Note that we consider the length of the address field to | |
396 | * still be one byte because the extra address bits are | |
397 | * hidden in the chip address. | |
398 | */ | |
399 | if( alen > 0 ) | |
6d0f6bcf | 400 | chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); |
b79316f2 SR |
401 | #endif |
402 | if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { | |
403 | printf( "I2c read: failed %d\n", ret); | |
404 | return 1; | |
405 | } | |
406 | return 0; | |
407 | } | |
408 | ||
409 | int i2c_write1 (uchar chip, uint addr, int alen, uchar * buffer, int len) | |
410 | { | |
411 | uchar xaddr[4]; | |
412 | ||
413 | if ( alen > 4 ) { | |
414 | printf ("I2C write: addr len %d not supported\n", alen); | |
415 | return 1; | |
416 | ||
417 | } | |
418 | if ( alen > 0 ) { | |
419 | xaddr[0] = (addr >> 24) & 0xFF; | |
420 | xaddr[1] = (addr >> 16) & 0xFF; | |
421 | xaddr[2] = (addr >> 8) & 0xFF; | |
422 | xaddr[3] = addr & 0xFF; | |
423 | } | |
424 | ||
6d0f6bcf | 425 | #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
b79316f2 SR |
426 | /* |
427 | * EEPROM chips that implement "address overflow" are ones | |
428 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of | |
429 | * address and the extra bits end up in the "chip address" | |
430 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like | |
431 | * four 256 byte chips. | |
432 | * | |
433 | * Note that we consider the length of the address field to | |
434 | * still be one byte because the extra address bits are | |
435 | * hidden in the chip address. | |
436 | */ | |
437 | if( alen > 0 ) | |
6d0f6bcf | 438 | chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); |
b79316f2 SR |
439 | #endif |
440 | ||
441 | return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); | |
442 | } | |
443 | ||
444 | /*----------------------------------------------------------------------- | |
445 | * Read a register | |
446 | */ | |
447 | uchar i2c_reg_read1(uchar i2c_addr, uchar reg) | |
448 | { | |
77ddac94 | 449 | uchar buf; |
b79316f2 | 450 | |
77ddac94 | 451 | i2c_read1(i2c_addr, reg, 1, &buf, (uchar)1); |
b79316f2 SR |
452 | |
453 | return(buf); | |
454 | } | |
455 | ||
456 | /*----------------------------------------------------------------------- | |
457 | * Write a register | |
458 | */ | |
459 | void i2c_reg_write1(uchar i2c_addr, uchar reg, uchar val) | |
460 | { | |
461 | i2c_write1(i2c_addr, reg, 1, &val, 1); | |
462 | } | |
463 | ||
464 | ||
465 | int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
466 | { | |
467 | int j; | |
6d0f6bcf | 468 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
b79316f2 SR |
469 | int k, skip; |
470 | #endif | |
471 | ||
472 | puts ("Valid chip addresses:"); | |
473 | for(j = 0; j < 128; j++) { | |
6d0f6bcf | 474 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
b79316f2 SR |
475 | skip = 0; |
476 | for (k = 0; k < sizeof(i2c_no_probes); k++){ | |
477 | if (j == i2c_no_probes[k]){ | |
478 | skip = 1; | |
479 | break; | |
480 | } | |
481 | } | |
482 | if (skip) | |
483 | continue; | |
484 | #endif | |
485 | if(i2c_probe1(j) == 0) { | |
486 | printf(" %02X", j); | |
487 | } | |
488 | } | |
489 | putc ('\n'); | |
490 | ||
6d0f6bcf | 491 | #if defined(CONFIG_SYS_I2C_NOPROBES) |
b79316f2 SR |
492 | puts ("Excluded chip addresses:"); |
493 | for( k = 0; k < sizeof(i2c_no_probes); k++ ) | |
494 | printf(" %02X", i2c_no_probes[k] ); | |
495 | putc ('\n'); | |
496 | #endif | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
501 | U_BOOT_CMD( | |
502 | iprobe1, 1, 1, do_i2c1_probe, | |
503 | "iprobe1 - probe to discover valid I2C chip addresses\n", | |
504 | "\n -discover valid I2C chip addresses\n" | |
505 | ); | |
506 | ||
3d078ce6 | 507 | #endif /* CONFIG_I2C_BUS1 */ |