[people/ms/u-boot.git] / board / sbc8548 / sbc8548.c

/*
 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
 *
 * Copyright 2007 Embedded Specialties, Inc.
 *
 * Copyright 2004, 2007 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <netdev.h>
#include <tsec.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>

DECLARE_GLOBAL_DATA_PTR;

void local_bus_init(void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;

	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
			in_8(rev) >> 4);

	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	out_be32(&ecm->eedr, 0xffffffff);	/* clear ecm errors */
	out_be32(&ecm->eeer, 0xffffffff);	/* enable ecm errors */
	return 0;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);
	clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;

	out_be32(&gur->lbiuiplldcr1, 0x00078080);
	if (clkdiv == 16) {
		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
	} else if (clkdiv == 8) {
		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
	} else if (clkdiv == 4) {
		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
	}

	setbits_be32(&lbc->lcrr, 0x00030000);

	asm("sync;isync;msync");

	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void lbc_sdram_init(void)
{
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)

	uint idx;
	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
	uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);

	puts("    SDRAM: ");

	print_size(size, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);

	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
	asm("msync");

	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
	asm("msync");

	/*
	 * Issue PRECHARGE ALL command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		*sdram_addr2 = 0xff;
		ppcDcbf((unsigned long) sdram_addr2);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(100);

	/*
	 * Issue RFEN command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CONFIG_SYS_MEMTEST_START,
	       CONFIG_SYS_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#if !defined(CONFIG_SPD_EEPROM)
#define CONFIG_SYS_DDR_CONTROL 0xc300c000
/*************************************************************************
 *  fixed_sdram init -- doesn't use serial presence detect.
 *  assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
 ************************************************************************/
phys_size_t fixed_sdram(void)
{
	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

	out_be32(&ddr->cs0_bnds, 0x0000007f);
	out_be32(&ddr->cs1_bnds, 0x008000ff);
	out_be32(&ddr->cs2_bnds, 0x00000000);
	out_be32(&ddr->cs3_bnds, 0x00000000);
	out_be32(&ddr->cs0_config, 0x80010101);
	out_be32(&ddr->cs1_config, 0x80010101);
	out_be32(&ddr->cs2_config, 0x00000000);
	out_be32(&ddr->cs3_config, 0x00000000);
	out_be32(&ddr->timing_cfg_3, 0x00000000);
	out_be32(&ddr->timing_cfg_0, 0x00220802);
	out_be32(&ddr->timing_cfg_1, 0x38377322);
	out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
	out_be32(&ddr->sdram_cfg, 0x4300C000);
	out_be32(&ddr->sdram_cfg_2, 0x24401000);
	out_be32(&ddr->sdram_mode, 0x23C00542);
	out_be32(&ddr->sdram_mode_2, 0x00000000);
	out_be32(&ddr->sdram_interval, 0x05080100);
	out_be32(&ddr->sdram_md_cntl, 0x00000000);
	out_be32(&ddr->sdram_data_init, 0x00000000);
	out_be32(&ddr->sdram_clk_cntl, 0x03800000);
	asm("sync;isync;msync");
	udelay(500);

	#if defined (CONFIG_DDR_ECC)
	  /* Enable ECC checking */
	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
	#else
	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
	#endif

	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif	/* CONFIG_PCI1 */

#ifdef CONFIG_PCI
void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int first_free_busno = 0;

#ifdef CONFIG_PCI1
	struct fsl_pci_info pci_info;
	u32 devdisr = in_be32(&gur->devdisr);
	u32 pordevsr = in_be32(&gur->pordevsr);
	u32 porpllsr = in_be32(&gur->porpllsr);

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
		uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
		uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* get_clock_freq() */

		printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33000000) ? "33" :
			(pci_speed == 66000000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_arb ? "arbiter" : "external-arbiter");

		SET_STD_PCI_INFO(pci_info, 1);
		set_next_law(pci_info.mem_phys,
			law_size_bits(pci_info.mem_size), pci_info.law);
		set_next_law(pci_info.io_phys,
			law_size_bits(pci_info.io_size), pci_info.law);

		first_free_busno = fsl_pci_init_port(&pci_info,
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif

	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */

	fsl_pcie_init_board(first_free_busno);
}
#endif

int board_eth_init(bd_t *bis)
{
	tsec_standard_init(bis);
	pci_eth_init(bis);
	return 0;	/* otherwise cpu_eth_init gets run */
}

int last_stage_init(void)
{
	return 0;
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

#ifdef CONFIG_FSL_PCI_INIT
	FT_FSL_PCI_SETUP;
#endif
}
#endif
Commit	Line	Data
11c45ebd	1	/*
bd42bbb8 PG	2	* Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
bd42bbb8 PG	3	*
11c45ebd JH	4	* Copyright 2007 Embedded Specialties, Inc.
	5	*
	6	* Copyright 2004, 2007 Freescale Semiconductor.
	7	*
	8	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <common.h>
	30	#include <pci.h>
	31	#include <asm/processor.h>
	32	#include <asm/immap_85xx.h>
c8514622	33	#include <asm/fsl_pci.h>
33b9079b	34	#include <asm/fsl_ddr_sdram.h>
5d27e02c	35	#include <asm/fsl_serdes.h>
a30a549a	36	#include <spd_sdram.h>
94ca0914 PG	37	#include <netdev.h>
94ca0914 PG	38	#include <tsec.h>
11c45ebd JH	39	#include <miiphy.h>
	40	#include <libfdt.h>
	41	#include <fdt_support.h>
	42
11c45ebd JH	43	DECLARE_GLOBAL_DATA_PTR;
11c45ebd JH	44
11c45ebd	45	void local_bus_init(void);
11c45ebd JH	46
	47	int board_early_init_f (void)
	48	{
	49	return 0;
	50	}
	51
	52	int checkboard (void)
	53	{
6d0f6bcf JCPV	54	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
6d0f6bcf JCPV	55	volatile u_char rev= (void )CONFIG_SYS_BD_REV;
11c45ebd JH	56
11c45ebd JH	57	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
0c7e4d45	58	in_8(rev) >> 4);
11c45ebd JH	59
	60	/*
	61	* Initialize local bus.
	62	*/
	63	local_bus_init ();
	64
0c7e4d45 PG	65	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
0c7e4d45 PG	66	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
11c45ebd JH	67	return 0;
	68	}
	69
11c45ebd JH	70	/*
	71	* Initialize Local Bus
	72	*/
	73	void
	74	local_bus_init(void)
	75	{
6d0f6bcf	76	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	77	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
11c45ebd JH	78
11c45ebd JH	79	uint clkdiv;
11c45ebd JH	80	sys_info_t sysinfo;
	81
	82	get_sys_info(&sysinfo);
0c7e4d45	83	clkdiv = (in_be32(&lbc->lcrr) & LCRR_CLKDIV) * 2;
11c45ebd	84
0c7e4d45	85	out_be32(&gur->lbiuiplldcr1, 0x00078080);
11c45ebd	86	if (clkdiv == 16) {
0c7e4d45	87	out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
11c45ebd	88	} else if (clkdiv == 8) {
0c7e4d45	89	out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
11c45ebd	90	} else if (clkdiv == 4) {
0c7e4d45	91	out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
11c45ebd JH	92	}
11c45ebd JH	93
0c7e4d45	94	setbits_be32(&lbc->lcrr, 0x00030000);
11c45ebd JH	95
	96	asm("sync;isync;msync");
	97
0c7e4d45 PG	98	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
0c7e4d45 PG	99	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
11c45ebd JH	100	}
	101
	102	/*
	103	* Initialize SDRAM memory on the Local Bus.
	104	*/
70961ba4	105	void lbc_sdram_init(void)
11c45ebd	106	{
11d5a629	107	#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
11c45ebd JH	108
11c45ebd JH	109	uint idx;
5f4c6f0d	110	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
f51cdaf1	111	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	112	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
5f4c6f0d	113	uint sdram_addr2 = (uint )(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
11c45ebd JH	114
	115	puts(" SDRAM: ");
	116
5f4c6f0d	117	print_size(size, "\n");
11c45ebd JH	118
	119	/*
	120	* Setup SDRAM Base and Option Registers
	121	*/
f51cdaf1 BB	122	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
	123	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
	124	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
	125	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
11d5a629	126
0c7e4d45	127	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
11c45ebd JH	128	asm("msync");
11c45ebd JH	129
0c7e4d45 PG	130	out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
0c7e4d45 PG	131	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
11c45ebd JH	132	asm("msync");
11c45ebd JH	133
11c45ebd JH	134	/*
	135	* Issue PRECHARGE ALL command.
	136	*/
5f4c6f0d	137	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
11c45ebd JH	138	asm("sync;msync");
	139	*sdram_addr = 0xff;
	140	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	141	*sdram_addr2 = 0xff;
5f4c6f0d PG	142	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	143	udelay(100);
	144
	145	/*
	146	* Issue 8 AUTO REFRESH commands.
	147	*/
	148	for (idx = 0; idx < 8; idx++) {
5f4c6f0d	149	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
11c45ebd JH	150	asm("sync;msync");
	151	*sdram_addr = 0xff;
	152	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	153	*sdram_addr2 = 0xff;
5f4c6f0d PG	154	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	155	udelay(100);
	156	}
	157
	158	/*
	159	* Issue 8 MODE-set command.
	160	*/
5f4c6f0d	161	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
11c45ebd JH	162	asm("sync;msync");
	163	*sdram_addr = 0xff;
	164	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	165	*sdram_addr2 = 0xff;
5f4c6f0d PG	166	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	167	udelay(100);
	168
	169	/*
5f4c6f0d	170	* Issue RFEN command.
11c45ebd	171	*/
5f4c6f0d	172	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
11c45ebd JH	173	asm("sync;msync");
	174	*sdram_addr = 0xff;
	175	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	176	*sdram_addr2 = 0xff;
5f4c6f0d PG	177	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	178	udelay(200); /* Overkill. Must wait > 200 bus cycles */
	179
	180	#endif /* enable SDRAM init */
	181	}
	182
6d0f6bcf	183	#if defined(CONFIG_SYS_DRAM_TEST)
11c45ebd JH	184	int
	185	testdram(void)
	186	{
6d0f6bcf JCPV	187	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	188	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
11c45ebd JH	189	uint *p;
	190
	191	printf("Testing DRAM from 0x%08x to 0x%08x\n",
6d0f6bcf JCPV	192	CONFIG_SYS_MEMTEST_START,
6d0f6bcf JCPV	193	CONFIG_SYS_MEMTEST_END);
11c45ebd JH	194
	195	printf("DRAM test phase 1:\n");
	196	for (p = pstart; p < pend; p++)
	197	*p = 0xaaaaaaaa;
	198
	199	for (p = pstart; p < pend; p++) {
	200	if (*p != 0xaaaaaaaa) {
	201	printf ("DRAM test fails at: %08x\n", (uint) p);
	202	return 1;
	203	}
	204	}
	205
	206	printf("DRAM test phase 2:\n");
	207	for (p = pstart; p < pend; p++)
	208	*p = 0x55555555;
	209
	210	for (p = pstart; p < pend; p++) {
	211	if (*p != 0x55555555) {
	212	printf ("DRAM test fails at: %08x\n", (uint) p);
	213	return 1;
	214	}
	215	}
	216
	217	printf("DRAM test passed.\n");
	218	return 0;
	219	}
	220	#endif
	221
0c7e4d45 PG	222	#if !defined(CONFIG_SPD_EEPROM)
0c7e4d45 PG	223	#define CONFIG_SYS_DDR_CONTROL 0xc300c000
11c45ebd JH	224	/*************************************************************************
	225	* fixed_sdram init -- doesn't use serial presence detect.
	226	* assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
	227	************************************************************************/
38dba0c2	228	phys_size_t fixed_sdram(void)
11c45ebd	229	{
6d0f6bcf	230	volatile ccsr_ddr_t ddr = (void )(CONFIG_SYS_MPC85xx_DDR_ADDR);
11c45ebd	231
0c7e4d45 PG	232	out_be32(&ddr->cs0_bnds, 0x0000007f);
	233	out_be32(&ddr->cs1_bnds, 0x008000ff);
	234	out_be32(&ddr->cs2_bnds, 0x00000000);
	235	out_be32(&ddr->cs3_bnds, 0x00000000);
	236	out_be32(&ddr->cs0_config, 0x80010101);
	237	out_be32(&ddr->cs1_config, 0x80010101);
	238	out_be32(&ddr->cs2_config, 0x00000000);
	239	out_be32(&ddr->cs3_config, 0x00000000);
	240	out_be32(&ddr->timing_cfg_3, 0x00000000);
	241	out_be32(&ddr->timing_cfg_0, 0x00220802);
	242	out_be32(&ddr->timing_cfg_1, 0x38377322);
	243	out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
	244	out_be32(&ddr->sdram_cfg, 0x4300C000);
	245	out_be32(&ddr->sdram_cfg_2, 0x24401000);
	246	out_be32(&ddr->sdram_mode, 0x23C00542);
	247	out_be32(&ddr->sdram_mode_2, 0x00000000);
	248	out_be32(&ddr->sdram_interval, 0x05080100);
	249	out_be32(&ddr->sdram_md_cntl, 0x00000000);
	250	out_be32(&ddr->sdram_data_init, 0x00000000);
	251	out_be32(&ddr->sdram_clk_cntl, 0x03800000);
11c45ebd JH	252	asm("sync;isync;msync");
	253	udelay(500);
	254
	255	#if defined (CONFIG_DDR_ECC)
	256	/* Enable ECC checking */
0c7e4d45	257	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL \| 0x20000000);
11c45ebd	258	#else
0c7e4d45	259	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
11c45ebd JH	260	#endif
11c45ebd JH	261
6d0f6bcf	262	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
11c45ebd JH	263	}
	264	#endif
	265
7b1f1399 PG	266	#ifdef CONFIG_PCI1
	267	static struct pci_controller pci1_hose;
	268	#endif /* CONFIG_PCI1 */
11c45ebd	269
fdc7eb90	270	#ifdef CONFIG_PCI
11c45ebd JH	271	void
	272	pci_init_board(void)
	273	{
6d0f6bcf	274	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
fdc7eb90	275	int first_free_busno = 0;
fdc7eb90 PG	276
fdc7eb90 PG	277	#ifdef CONFIG_PCI1
2d0a054d KG	278	struct fsl_pci_info pci_info;
	279	u32 devdisr = in_be32(&gur->devdisr);
	280	u32 pordevsr = in_be32(&gur->pordevsr);
	281	u32 porpllsr = in_be32(&gur->porpllsr);
	282
fdc7eb90 PG	283	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	284	uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
	285	uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	286	uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
	287	uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
11c45ebd	288
8ca78f2c	289	printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
11c45ebd	290	(pci_32) ? 32 : 64,
2c40acd3 PG	291	(pci_speed == 33000000) ? "33" :
2c40acd3 PG	292	(pci_speed == 66000000) ? "66" : "unknown",
11c45ebd	293	pci_clk_sel ? "sync" : "async",
fdc7eb90 PG	294	pci_arb ? "arbiter" : "external-arbiter");
fdc7eb90 PG	295
2d0a054d KG	296	SET_STD_PCI_INFO(pci_info, 1);
	297	set_next_law(pci_info.mem_phys,
	298	law_size_bits(pci_info.mem_size), pci_info.law);
	299	set_next_law(pci_info.io_phys,
	300	law_size_bits(pci_info.io_size), pci_info.law);
	301
	302	first_free_busno = fsl_pci_init_port(&pci_info,
01471d53	303	&pci1_hose, first_free_busno);
11c45ebd	304	} else {
8ca78f2c	305	printf("PCI: disabled\n");
11c45ebd	306	}
fdc7eb90 PG	307
fdc7eb90 PG	308	puts("\n");
11c45ebd	309	#else
fdc7eb90	310	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
11c45ebd JH	311	#endif
11c45ebd JH	312
fdc7eb90	313	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
11c45ebd	314
2d0a054d	315	fsl_pcie_init_board(first_free_busno);
11c45ebd	316	}
fdc7eb90	317	#endif
11c45ebd	318
94ca0914 PG	319	int board_eth_init(bd_t *bis)
	320	{
	321	tsec_standard_init(bis);
	322	pci_eth_init(bis);
	323	return 0; /* otherwise cpu_eth_init gets run */
	324	}
	325
11c45ebd JH	326	int last_stage_init(void)
	327	{
	328	return 0;
	329	}
	330
	331	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea KG	332	void ft_board_setup(void blob, bd_t bd)
	333	{
	334	ft_cpu_setup(blob, bd);
6525d51f KG	335
	336	#ifdef CONFIG_FSL_PCI_INIT
	337	FT_FSL_PCI_SETUP;
11c45ebd JH	338	#endif
	339	}
	340	#endif