[people/ms/u-boot.git] / board / sbc8548 / sbc8548.c

/*
 * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
 *
 * Copyright 2007 Embedded Specialties, Inc.
 *
 * Copyright 2004, 2007 Freescale Semiconductor.
 *
 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#include <common.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <netdev.h>
#include <tsec.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>

DECLARE_GLOBAL_DATA_PTR;

void local_bus_init(void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;

	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
			in_8(rev) >> 4);

	/*
	 * Initialize local bus.
	 */
	local_bus_init ();

	out_be32(&ecm->eedr, 0xffffffff);	/* clear ecm errors */
	out_be32(&ecm->eeer, 0xffffffff);	/* enable ecm errors */
	return 0;
}

/*
 * Initialize Local Bus
 */
void
local_bus_init(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;

	uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
	sys_info_t sysinfo;

	get_sys_info(&sysinfo);

	lbc_mhz = sysinfo.freq_localbus / 1000000;
	clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;

	debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);

	out_be32(&gur->lbiuiplldcr1, 0x00078080);
	if (clkdiv == 16) {
		out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
	} else if (clkdiv == 8) {
		out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
	} else if (clkdiv == 4) {
		out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
	}

	/*
	 * Local Bus Clock > 83.3 MHz. According to timing
	 * specifications set LCRR[EADC] to 2 delay cycles.
	 */
	if (lbc_mhz > 83) {
		lcrr &= ~LCRR_EADC;
		lcrr |= LCRR_EADC_2;
	}

	/*
	 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
	 * disable PLL bypass for Local Bus Clock > 83 MHz.
	 */
	if (lbc_mhz >= 66)
		lcrr &= (~LCRR_DBYP);	/* DLL Enabled */

	else
		lcrr |= LCRR_DBYP;	/* DLL Bypass */

	out_be32(&lbc->lcrr, lcrr);
	asm("sync;isync;msync");

	 /*
	 * According to MPC8548ERMAD Rev.1.3 read back LCRR
	 * and terminate with isync
	 */
	lcrr = in_be32(&lbc->lcrr);
	asm ("isync;");

	/* let DLL stabilize */
	udelay(500);

	out_be32(&lbc->ltesr, 0xffffffff);	/* Clear LBC error IRQs */
	out_be32(&lbc->lteir, 0xffffffff);	/* Enable LBC error IRQs */
}

/*
 * Initialize SDRAM memory on the Local Bus.
 */
void lbc_sdram_init(void)
{
#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)

	uint idx;
	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
	uint *sdram_addr2 = (uint *)(CONFIG_SYS_LBC_SDRAM_BASE + size/2);

	puts("    SDRAM: ");

	print_size(size, "\n");

	/*
	 * Setup SDRAM Base and Option Registers
	 */
	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);

	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
	asm("msync");

	out_be32(&lbc->lsrt,  CONFIG_SYS_LBC_LSRT);
	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
	asm("msync");

	/*
	 * Issue PRECHARGE ALL command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(100);

	/*
	 * Issue 8 AUTO REFRESH commands.
	 */
	for (idx = 0; idx < 8; idx++) {
		out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
		asm("sync;msync");
		*sdram_addr = 0xff;
		ppcDcbf((unsigned long) sdram_addr);
		*sdram_addr2 = 0xff;
		ppcDcbf((unsigned long) sdram_addr2);
		udelay(100);
	}

	/*
	 * Issue 8 MODE-set command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(100);

	/*
	 * Issue RFEN command.
	 */
	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
	asm("sync;msync");
	*sdram_addr = 0xff;
	ppcDcbf((unsigned long) sdram_addr);
	*sdram_addr2 = 0xff;
	ppcDcbf((unsigned long) sdram_addr2);
	udelay(200);    /* Overkill. Must wait > 200 bus cycles */

#endif	/* enable SDRAM init */
}

#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CONFIG_SYS_MEMTEST_START,
	       CONFIG_SYS_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif	/* CONFIG_PCI1 */

#ifdef CONFIG_PCI
void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	int first_free_busno = 0;

#ifdef CONFIG_PCI1
	struct fsl_pci_info pci_info;
	u32 devdisr = in_be32(&gur->devdisr);
	u32 pordevsr = in_be32(&gur->pordevsr);
	u32 porpllsr = in_be32(&gur->porpllsr);

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
		uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
		uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* get_clock_freq() */

		printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33000000) ? "33" :
			(pci_speed == 66000000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_arb ? "arbiter" : "external-arbiter");

		SET_STD_PCI_INFO(pci_info, 1);
		set_next_law(pci_info.mem_phys,
			law_size_bits(pci_info.mem_size), pci_info.law);
		set_next_law(pci_info.io_phys,
			law_size_bits(pci_info.io_size), pci_info.law);

		first_free_busno = fsl_pci_init_port(&pci_info,
					&pci1_hose, first_free_busno);
	} else {
		printf("PCI: disabled\n");
	}

	puts("\n");
#else
	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif

	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */

	fsl_pcie_init_board(first_free_busno);
}
#endif

int board_eth_init(bd_t *bis)
{
	tsec_standard_init(bis);
	pci_eth_init(bis);
	return 0;	/* otherwise cpu_eth_init gets run */
}

int last_stage_init(void)
{
	return 0;
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);

#ifdef CONFIG_FSL_PCI_INIT
	FT_FSL_PCI_SETUP;
#endif
}
#endif
Commit	Line	Data
11c45ebd	1	/*
bd42bbb8 PG	2	* Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com>
bd42bbb8 PG	3	*
11c45ebd JH	4	* Copyright 2007 Embedded Specialties, Inc.
	5	*
	6	* Copyright 2004, 2007 Freescale Semiconductor.
	7	*
	8	* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
11c45ebd JH	11	*/
	12
	13	#include <common.h>
	14	#include <pci.h>
	15	#include <asm/processor.h>
	16	#include <asm/immap_85xx.h>
c8514622	17	#include <asm/fsl_pci.h>
33b9079b	18	#include <asm/fsl_ddr_sdram.h>
5d27e02c	19	#include <asm/fsl_serdes.h>
a30a549a	20	#include <spd_sdram.h>
94ca0914 PG	21	#include <netdev.h>
94ca0914 PG	22	#include <tsec.h>
11c45ebd JH	23	#include <miiphy.h>
	24	#include <libfdt.h>
	25	#include <fdt_support.h>
	26
11c45ebd JH	27	DECLARE_GLOBAL_DATA_PTR;
11c45ebd JH	28
11c45ebd	29	void local_bus_init(void);
11c45ebd JH	30
	31	int board_early_init_f (void)
	32	{
	33	return 0;
	34	}
	35
	36	int checkboard (void)
	37	{
6d0f6bcf JCPV	38	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
6d0f6bcf JCPV	39	volatile u_char rev= (void )CONFIG_SYS_BD_REV;
11c45ebd JH	40
11c45ebd JH	41	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
0c7e4d45	42	in_8(rev) >> 4);
11c45ebd JH	43
	44	/*
	45	* Initialize local bus.
	46	*/
	47	local_bus_init ();
	48
0c7e4d45 PG	49	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
0c7e4d45 PG	50	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
11c45ebd JH	51	return 0;
	52	}
	53
11c45ebd JH	54	/*
	55	* Initialize Local Bus
	56	*/
	57	void
	58	local_bus_init(void)
	59	{
6d0f6bcf	60	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
f51cdaf1	61	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
11c45ebd	62
e2b363ff	63	uint clkdiv, lbc_mhz, lcrr = CONFIG_SYS_LBC_LCRR;
11c45ebd JH	64	sys_info_t sysinfo;
	65
	66	get_sys_info(&sysinfo);
e2b363ff	67
997399fa PK	68	lbc_mhz = sysinfo.freq_localbus / 1000000;
997399fa PK	69	clkdiv = sysinfo.freq_systembus / sysinfo.freq_localbus;
e2b363ff PG	70
e2b363ff PG	71	debug("LCRR=0x%x, CD=%d, MHz=%d\n", lcrr, clkdiv, lbc_mhz);
11c45ebd	72
0c7e4d45	73	out_be32(&gur->lbiuiplldcr1, 0x00078080);
11c45ebd	74	if (clkdiv == 16) {
0c7e4d45	75	out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
11c45ebd	76	} else if (clkdiv == 8) {
0c7e4d45	77	out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
11c45ebd	78	} else if (clkdiv == 4) {
0c7e4d45	79	out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
11c45ebd JH	80	}
11c45ebd JH	81
e2b363ff PG	82	/*
	83	* Local Bus Clock > 83.3 MHz. According to timing
	84	* specifications set LCRR[EADC] to 2 delay cycles.
	85	*/
	86	if (lbc_mhz > 83) {
	87	lcrr &= ~LCRR_EADC;
	88	lcrr \|= LCRR_EADC_2;
	89	}
	90
	91	/*
	92	* According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
	93	* disable PLL bypass for Local Bus Clock > 83 MHz.
	94	*/
	95	if (lbc_mhz >= 66)
	96	lcrr &= (~LCRR_DBYP); /* DLL Enabled */
	97
	98	else
	99	lcrr \|= LCRR_DBYP; /* DLL Bypass */
11c45ebd	100
e2b363ff	101	out_be32(&lbc->lcrr, lcrr);
11c45ebd JH	102	asm("sync;isync;msync");
11c45ebd JH	103
e2b363ff PG	104	/*
	105	* According to MPC8548ERMAD Rev.1.3 read back LCRR
	106	* and terminate with isync
	107	*/
	108	lcrr = in_be32(&lbc->lcrr);
	109	asm ("isync;");
	110
	111	/* let DLL stabilize */
	112	udelay(500);
	113
0c7e4d45 PG	114	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
0c7e4d45 PG	115	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
11c45ebd JH	116	}
	117
	118	/*
	119	* Initialize SDRAM memory on the Local Bus.
	120	*/
70961ba4	121	void lbc_sdram_init(void)
11c45ebd	122	{
11d5a629	123	#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
11c45ebd JH	124
11c45ebd JH	125	uint idx;
5f4c6f0d	126	const unsigned long size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
f51cdaf1	127	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
6d0f6bcf	128	uint sdram_addr = (uint )CONFIG_SYS_LBC_SDRAM_BASE;
5f4c6f0d	129	uint sdram_addr2 = (uint )(CONFIG_SYS_LBC_SDRAM_BASE + size/2);
11c45ebd JH	130
	131	puts(" SDRAM: ");
	132
5f4c6f0d	133	print_size(size, "\n");
11c45ebd JH	134
	135	/*
	136	* Setup SDRAM Base and Option Registers
	137	*/
f51cdaf1 BB	138	set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
	139	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
	140	set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
	141	set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
11d5a629	142
0c7e4d45	143	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
11c45ebd JH	144	asm("msync");
11c45ebd JH	145
0c7e4d45 PG	146	out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
0c7e4d45 PG	147	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
11c45ebd JH	148	asm("msync");
11c45ebd JH	149
11c45ebd JH	150	/*
	151	* Issue PRECHARGE ALL command.
	152	*/
5f4c6f0d	153	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_PCHALL);
11c45ebd JH	154	asm("sync;msync");
	155	*sdram_addr = 0xff;
	156	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	157	*sdram_addr2 = 0xff;
5f4c6f0d PG	158	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	159	udelay(100);
	160
	161	/*
	162	* Issue 8 AUTO REFRESH commands.
	163	*/
	164	for (idx = 0; idx < 8; idx++) {
5f4c6f0d	165	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_ARFRSH);
11c45ebd JH	166	asm("sync;msync");
	167	*sdram_addr = 0xff;
	168	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	169	*sdram_addr2 = 0xff;
5f4c6f0d PG	170	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	171	udelay(100);
	172	}
	173
	174	/*
	175	* Issue 8 MODE-set command.
	176	*/
5f4c6f0d	177	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_MRW);
11c45ebd JH	178	asm("sync;msync");
	179	*sdram_addr = 0xff;
	180	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	181	*sdram_addr2 = 0xff;
5f4c6f0d PG	182	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	183	udelay(100);
	184
	185	/*
5f4c6f0d	186	* Issue RFEN command.
11c45ebd	187	*/
5f4c6f0d	188	out_be32(&lbc->lsdmr, CONFIG_SYS_LBC_LSDMR_RFEN);
11c45ebd JH	189	asm("sync;msync");
	190	*sdram_addr = 0xff;
	191	ppcDcbf((unsigned long) sdram_addr);
5f4c6f0d PG	192	*sdram_addr2 = 0xff;
5f4c6f0d PG	193	ppcDcbf((unsigned long) sdram_addr2);
11c45ebd JH	194	udelay(200); /* Overkill. Must wait > 200 bus cycles */
	195
	196	#endif /* enable SDRAM init */
	197	}
	198
6d0f6bcf	199	#if defined(CONFIG_SYS_DRAM_TEST)
11c45ebd JH	200	int
	201	testdram(void)
	202	{
6d0f6bcf JCPV	203	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	204	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
11c45ebd JH	205	uint *p;
	206
	207	printf("Testing DRAM from 0x%08x to 0x%08x\n",
6d0f6bcf JCPV	208	CONFIG_SYS_MEMTEST_START,
6d0f6bcf JCPV	209	CONFIG_SYS_MEMTEST_END);
11c45ebd JH	210
	211	printf("DRAM test phase 1:\n");
	212	for (p = pstart; p < pend; p++)
	213	*p = 0xaaaaaaaa;
	214
	215	for (p = pstart; p < pend; p++) {
	216	if (*p != 0xaaaaaaaa) {
	217	printf ("DRAM test fails at: %08x\n", (uint) p);
	218	return 1;
	219	}
	220	}
	221
	222	printf("DRAM test phase 2:\n");
	223	for (p = pstart; p < pend; p++)
	224	*p = 0x55555555;
	225
	226	for (p = pstart; p < pend; p++) {
	227	if (*p != 0x55555555) {
	228	printf ("DRAM test fails at: %08x\n", (uint) p);
	229	return 1;
	230	}
	231	}
	232
	233	printf("DRAM test passed.\n");
	234	return 0;
	235	}
	236	#endif
	237
7b1f1399 PG	238	#ifdef CONFIG_PCI1
	239	static struct pci_controller pci1_hose;
	240	#endif /* CONFIG_PCI1 */
11c45ebd	241
fdc7eb90	242	#ifdef CONFIG_PCI
11c45ebd JH	243	void
	244	pci_init_board(void)
	245	{
6d0f6bcf	246	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
fdc7eb90	247	int first_free_busno = 0;
fdc7eb90 PG	248
fdc7eb90 PG	249	#ifdef CONFIG_PCI1
2d0a054d KG	250	struct fsl_pci_info pci_info;
	251	u32 devdisr = in_be32(&gur->devdisr);
	252	u32 pordevsr = in_be32(&gur->pordevsr);
	253	u32 porpllsr = in_be32(&gur->porpllsr);
	254
fdc7eb90 PG	255	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	256	uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
	257	uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	258	uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
	259	uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
11c45ebd	260
8ca78f2c	261	printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
11c45ebd	262	(pci_32) ? 32 : 64,
2c40acd3 PG	263	(pci_speed == 33000000) ? "33" :
2c40acd3 PG	264	(pci_speed == 66000000) ? "66" : "unknown",
11c45ebd	265	pci_clk_sel ? "sync" : "async",
fdc7eb90 PG	266	pci_arb ? "arbiter" : "external-arbiter");
fdc7eb90 PG	267
2d0a054d KG	268	SET_STD_PCI_INFO(pci_info, 1);
	269	set_next_law(pci_info.mem_phys,
	270	law_size_bits(pci_info.mem_size), pci_info.law);
	271	set_next_law(pci_info.io_phys,
	272	law_size_bits(pci_info.io_size), pci_info.law);
	273
	274	first_free_busno = fsl_pci_init_port(&pci_info,
01471d53	275	&pci1_hose, first_free_busno);
11c45ebd	276	} else {
8ca78f2c	277	printf("PCI: disabled\n");
11c45ebd	278	}
fdc7eb90 PG	279
fdc7eb90 PG	280	puts("\n");
11c45ebd	281	#else
fdc7eb90	282	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
11c45ebd JH	283	#endif
11c45ebd JH	284
fdc7eb90	285	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
11c45ebd	286
2d0a054d	287	fsl_pcie_init_board(first_free_busno);
11c45ebd	288	}
fdc7eb90	289	#endif
11c45ebd	290
94ca0914 PG	291	int board_eth_init(bd_t *bis)
	292	{
	293	tsec_standard_init(bis);
	294	pci_eth_init(bis);
	295	return 0; /* otherwise cpu_eth_init gets run */
	296	}
	297
11c45ebd JH	298	int last_stage_init(void)
	299	{
	300	return 0;
	301	}
	302
	303	#if defined(CONFIG_OF_BOARD_SETUP)
2dba0dea KG	304	void ft_board_setup(void blob, bd_t bd)
	305	{
	306	ft_cpu_setup(blob, bd);
6525d51f KG	307
	308	#ifdef CONFIG_FSL_PCI_INIT
	309	FT_FSL_PCI_SETUP;
11c45ebd JH	310	#endif
	311	}
	312	#endif