[people/ms/u-boot.git] / board / sbc8560 / tlb.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
/* TLB for CCSRBAR (IMMR) */
	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 1, BOOKE_PAGESZ_1M, 1),

/* TLB for Local Bus stuff, just map the whole 512M */
/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */

	SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 2, BOOKE_PAGESZ_256M, 1),

	SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 3, BOOKE_PAGESZ_256M, 1),

#if !defined(CONFIG_SPD_EEPROM)
	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 4, BOOKE_PAGESZ_256M, 1),

	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 5, BOOKE_PAGESZ_256M, 1),
#endif

	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
		      0, 6, BOOKE_PAGESZ_16K, 1),

	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		      0, 7, BOOKE_PAGESZ_256M, 1),
};

int num_tlb_entries = ARRAY_SIZE(tlb_table);
Commit	Line	Data
143b518d KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/mmu.h>
	28
	29	struct fsl_e_tlb_entry tlb_table[] = {
	30	/* TLB for CCSRBAR (IMMR) */
6d0f6bcf	31	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
143b518d KG	32	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	33	0, 1, BOOKE_PAGESZ_1M, 1),
	34
	35	/* TLB for Local Bus stuff, just map the whole 512M */
	36	/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
	37
	38	SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000,
	39	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	40	0, 2, BOOKE_PAGESZ_256M, 1),
	41
	42	SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000,
	43	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	44	0, 3, BOOKE_PAGESZ_256M, 1),
	45
	46	#if !defined(CONFIG_SPD_EEPROM)
6d0f6bcf	47	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
143b518d KG	48	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	49	0, 4, BOOKE_PAGESZ_256M, 1),
	50
6d0f6bcf	51	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
143b518d KG	52	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	53	0, 5, BOOKE_PAGESZ_256M, 1),
	54	#endif
	55
6d0f6bcf	56	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
143b518d KG	57	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
	58	0, 6, BOOKE_PAGESZ_16K, 1),
	59
6d0f6bcf	60	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
143b518d KG	61	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	62	0, 7, BOOKE_PAGESZ_256M, 1),
	63	};
	64
	65	int num_tlb_entries = ARRAY_SIZE(tlb_table);