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Commit | Line | Data |
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e363426e PK |
1 | /* |
2 | * board.c | |
3 | * | |
4 | * Board functions for TI AM335X based boards | |
5 | * | |
6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
e363426e PK |
9 | */ |
10 | ||
11 | #include <common.h> | |
12 | #include <errno.h> | |
13 | #include <spl.h> | |
3d16389c | 14 | #include <serial.h> |
e363426e PK |
15 | #include <asm/arch/cpu.h> |
16 | #include <asm/arch/hardware.h> | |
17 | #include <asm/arch/omap.h> | |
18 | #include <asm/arch/ddr_defs.h> | |
19 | #include <asm/arch/clock.h> | |
97f3a178 | 20 | #include <asm/arch/clk_synthesizer.h> |
e363426e PK |
21 | #include <asm/arch/gpio.h> |
22 | #include <asm/arch/mmc_host_def.h> | |
23 | #include <asm/arch/sys_proto.h> | |
cd8845d7 | 24 | #include <asm/arch/mem.h> |
e363426e PK |
25 | #include <asm/io.h> |
26 | #include <asm/emif.h> | |
27 | #include <asm/gpio.h> | |
b0a4eea1 | 28 | #include <asm/omap_sec_common.h> |
e363426e PK |
29 | #include <i2c.h> |
30 | #include <miiphy.h> | |
31 | #include <cpsw.h> | |
9721027a TR |
32 | #include <power/tps65217.h> |
33 | #include <power/tps65910.h> | |
6843918e TR |
34 | #include <environment.h> |
35 | #include <watchdog.h> | |
ba9a6708 | 36 | #include <environment.h> |
770e68c0 | 37 | #include "../common/board_detect.h" |
e363426e PK |
38 | #include "board.h" |
39 | ||
40 | DECLARE_GLOBAL_DATA_PTR; | |
41 | ||
e363426e | 42 | /* GPIO that controls power to DDR on EVM-SK */ |
97f3a178 LV |
43 | #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) |
44 | #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) | |
45 | #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) | |
46 | #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) | |
47 | #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) | |
48 | #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) | |
49 | #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) | |
e607ec99 RQ |
50 | #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11) |
51 | #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26) | |
e363426e PK |
52 | |
53 | static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; | |
54 | ||
e607ec99 RQ |
55 | #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT) |
56 | #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT) | |
57 | ||
58 | #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1) | |
59 | #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1) | |
60 | ||
61 | #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024) | |
62 | #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024) | |
63 | ||
e363426e PK |
64 | /* |
65 | * Read header information from EEPROM into global structure. | |
66 | */ | |
140d76a9 LV |
67 | #ifdef CONFIG_TI_I2C_BOARD_DETECT |
68 | void do_board_detect(void) | |
e363426e | 69 | { |
140d76a9 LV |
70 | enable_i2c0_pin_mux(); |
71 | i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); | |
72 | ||
73 | if (ti_i2c_eeprom_am_get(-1, CONFIG_SYS_I2C_EEPROM_ADDR)) | |
74 | printf("ti_i2c_eeprom_init failed\n"); | |
e363426e | 75 | } |
140d76a9 | 76 | #endif |
e363426e | 77 | |
3d16389c LV |
78 | #ifndef CONFIG_DM_SERIAL |
79 | struct serial_device *default_serial_console(void) | |
80 | { | |
81 | if (board_is_icev2()) | |
82 | return &eserial4_device; | |
83 | else | |
84 | return &eserial1_device; | |
85 | } | |
86 | #endif | |
87 | ||
d0e6d34d | 88 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
c00f69db | 89 | static const struct ddr_data ddr2_data = { |
c4f80f50 TR |
90 | .datardsratio0 = MT47H128M16RT25E_RD_DQS, |
91 | .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, | |
92 | .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, | |
c00f69db | 93 | }; |
e363426e | 94 | |
c00f69db | 95 | static const struct cmd_control ddr2_cmd_ctrl_data = { |
c7d35bef | 96 | .cmd0csratio = MT47H128M16RT25E_RATIO, |
c00f69db | 97 | |
c7d35bef | 98 | .cmd1csratio = MT47H128M16RT25E_RATIO, |
c00f69db | 99 | |
c7d35bef | 100 | .cmd2csratio = MT47H128M16RT25E_RATIO, |
c00f69db PK |
101 | }; |
102 | ||
103 | static const struct emif_regs ddr2_emif_reg_data = { | |
c7d35bef PK |
104 | .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, |
105 | .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, | |
106 | .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, | |
107 | .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, | |
108 | .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, | |
109 | .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, | |
c00f69db PK |
110 | }; |
111 | ||
8c17cbdf JS |
112 | static const struct emif_regs ddr2_evm_emif_reg_data = { |
113 | .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, | |
114 | .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, | |
115 | .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, | |
116 | .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, | |
117 | .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, | |
118 | .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, | |
119 | .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, | |
120 | }; | |
121 | ||
c00f69db | 122 | static const struct ddr_data ddr3_data = { |
c7d35bef PK |
123 | .datardsratio0 = MT41J128MJT125_RD_DQS, |
124 | .datawdsratio0 = MT41J128MJT125_WR_DQS, | |
125 | .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, | |
126 | .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, | |
c00f69db PK |
127 | }; |
128 | ||
c7ba18ad TR |
129 | static const struct ddr_data ddr3_beagleblack_data = { |
130 | .datardsratio0 = MT41K256M16HA125E_RD_DQS, | |
131 | .datawdsratio0 = MT41K256M16HA125E_WR_DQS, | |
132 | .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, | |
133 | .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, | |
c7ba18ad TR |
134 | }; |
135 | ||
13526f71 JL |
136 | static const struct ddr_data ddr3_evm_data = { |
137 | .datardsratio0 = MT41J512M8RH125_RD_DQS, | |
138 | .datawdsratio0 = MT41J512M8RH125_WR_DQS, | |
139 | .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, | |
140 | .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, | |
13526f71 JL |
141 | }; |
142 | ||
d8ff4fdb LV |
143 | static const struct ddr_data ddr3_icev2_data = { |
144 | .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, | |
145 | .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, | |
146 | .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, | |
147 | .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, | |
148 | }; | |
149 | ||
c00f69db | 150 | static const struct cmd_control ddr3_cmd_ctrl_data = { |
c7d35bef | 151 | .cmd0csratio = MT41J128MJT125_RATIO, |
c7d35bef | 152 | .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, |
c00f69db | 153 | |
c7d35bef | 154 | .cmd1csratio = MT41J128MJT125_RATIO, |
c7d35bef | 155 | .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, |
c00f69db | 156 | |
c7d35bef | 157 | .cmd2csratio = MT41J128MJT125_RATIO, |
c7d35bef | 158 | .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, |
c00f69db PK |
159 | }; |
160 | ||
c7ba18ad TR |
161 | static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { |
162 | .cmd0csratio = MT41K256M16HA125E_RATIO, | |
c7ba18ad TR |
163 | .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
164 | ||
165 | .cmd1csratio = MT41K256M16HA125E_RATIO, | |
c7ba18ad TR |
166 | .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
167 | ||
168 | .cmd2csratio = MT41K256M16HA125E_RATIO, | |
c7ba18ad TR |
169 | .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, |
170 | }; | |
171 | ||
13526f71 JL |
172 | static const struct cmd_control ddr3_evm_cmd_ctrl_data = { |
173 | .cmd0csratio = MT41J512M8RH125_RATIO, | |
13526f71 JL |
174 | .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, |
175 | ||
176 | .cmd1csratio = MT41J512M8RH125_RATIO, | |
13526f71 JL |
177 | .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, |
178 | ||
179 | .cmd2csratio = MT41J512M8RH125_RATIO, | |
13526f71 JL |
180 | .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, |
181 | }; | |
182 | ||
d8ff4fdb LV |
183 | static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { |
184 | .cmd0csratio = MT41J128MJT125_RATIO_400MHz, | |
185 | .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, | |
186 | ||
187 | .cmd1csratio = MT41J128MJT125_RATIO_400MHz, | |
188 | .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, | |
189 | ||
190 | .cmd2csratio = MT41J128MJT125_RATIO_400MHz, | |
191 | .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, | |
192 | }; | |
193 | ||
c00f69db | 194 | static struct emif_regs ddr3_emif_reg_data = { |
c7d35bef PK |
195 | .sdram_config = MT41J128MJT125_EMIF_SDCFG, |
196 | .ref_ctrl = MT41J128MJT125_EMIF_SDREF, | |
197 | .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, | |
198 | .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, | |
199 | .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, | |
200 | .zq_config = MT41J128MJT125_ZQ_CFG, | |
59dcf970 VH |
201 | .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | |
202 | PHY_EN_DYN_PWRDN, | |
c00f69db | 203 | }; |
13526f71 | 204 | |
c7ba18ad TR |
205 | static struct emif_regs ddr3_beagleblack_emif_reg_data = { |
206 | .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, | |
207 | .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, | |
208 | .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, | |
209 | .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, | |
210 | .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, | |
8c17cbdf | 211 | .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK, |
c7ba18ad TR |
212 | .zq_config = MT41K256M16HA125E_ZQ_CFG, |
213 | .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, | |
214 | }; | |
215 | ||
13526f71 JL |
216 | static struct emif_regs ddr3_evm_emif_reg_data = { |
217 | .sdram_config = MT41J512M8RH125_EMIF_SDCFG, | |
218 | .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, | |
219 | .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, | |
220 | .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, | |
221 | .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, | |
8c17cbdf | 222 | .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, |
13526f71 | 223 | .zq_config = MT41J512M8RH125_ZQ_CFG, |
59dcf970 VH |
224 | .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | |
225 | PHY_EN_DYN_PWRDN, | |
13526f71 | 226 | }; |
12d7a474 | 227 | |
d8ff4fdb LV |
228 | static struct emif_regs ddr3_icev2_emif_reg_data = { |
229 | .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, | |
230 | .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, | |
231 | .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, | |
232 | .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, | |
233 | .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, | |
234 | .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, | |
235 | .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | | |
236 | PHY_EN_DYN_PWRDN, | |
237 | }; | |
238 | ||
12d7a474 PK |
239 | #ifdef CONFIG_SPL_OS_BOOT |
240 | int spl_start_uboot(void) | |
241 | { | |
242 | /* break into full u-boot on 'c' */ | |
ba9a6708 TR |
243 | if (serial_tstc() && serial_getc() == 'c') |
244 | return 1; | |
245 | ||
246 | #ifdef CONFIG_SPL_ENV_SUPPORT | |
247 | env_init(); | |
248 | env_relocate_spec(); | |
249 | if (getenv_yesno("boot_os") != 1) | |
250 | return 1; | |
251 | #endif | |
252 | ||
253 | return 0; | |
12d7a474 PK |
254 | } |
255 | #endif | |
256 | ||
94d77fb6 LV |
257 | #define OSC (V_OSCK/1000000) |
258 | const struct dpll_params dpll_ddr = { | |
259 | 266, OSC-1, 1, -1, -1, -1, -1}; | |
260 | const struct dpll_params dpll_ddr_evm_sk = { | |
261 | 303, OSC-1, 1, -1, -1, -1, -1}; | |
262 | const struct dpll_params dpll_ddr_bone_black = { | |
263 | 400, OSC-1, 1, -1, -1, -1, -1}; | |
264 | ||
9721027a TR |
265 | void am33xx_spl_board_init(void) |
266 | { | |
9721027a TR |
267 | int mpu_vdd; |
268 | ||
9721027a | 269 | /* Get the frequency */ |
52f7d844 | 270 | dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); |
9721027a | 271 | |
770e68c0 | 272 | if (board_is_bone() || board_is_bone_lt()) { |
9721027a TR |
273 | /* BeagleBone PMIC Code */ |
274 | int usb_cur_lim; | |
275 | ||
276 | /* | |
277 | * Only perform PMIC configurations if board rev > A1 | |
278 | * on Beaglebone White | |
279 | */ | |
770e68c0 | 280 | if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) |
9721027a TR |
281 | return; |
282 | ||
283 | if (i2c_probe(TPS65217_CHIP_PM)) | |
284 | return; | |
285 | ||
286 | /* | |
287 | * On Beaglebone White we need to ensure we have AC power | |
288 | * before increasing the frequency. | |
289 | */ | |
770e68c0 | 290 | if (board_is_bone()) { |
9721027a TR |
291 | uchar pmic_status_reg; |
292 | if (tps65217_reg_read(TPS65217_STATUS, | |
293 | &pmic_status_reg)) | |
294 | return; | |
295 | if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { | |
296 | puts("No AC power, disabling frequency switch\n"); | |
297 | return; | |
298 | } | |
299 | } | |
300 | ||
301 | /* | |
302 | * Override what we have detected since we know if we have | |
303 | * a Beaglebone Black it supports 1GHz. | |
304 | */ | |
770e68c0 | 305 | if (board_is_bone_lt()) |
52f7d844 | 306 | dpll_mpu_opp100.m = MPUPLL_M_1000; |
9721027a TR |
307 | |
308 | /* | |
309 | * Increase USB current limit to 1300mA or 1800mA and set | |
310 | * the MPU voltage controller as needed. | |
311 | */ | |
52f7d844 | 312 | if (dpll_mpu_opp100.m == MPUPLL_M_1000) { |
9721027a TR |
313 | usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; |
314 | mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; | |
315 | } else { | |
316 | usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; | |
317 | mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; | |
318 | } | |
319 | ||
320 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, | |
321 | TPS65217_POWER_PATH, | |
322 | usb_cur_lim, | |
323 | TPS65217_USB_INPUT_CUR_LIMIT_MASK)) | |
324 | puts("tps65217_reg_write failure\n"); | |
325 | ||
52f7d844 SK |
326 | /* Set DCDC3 (CORE) voltage to 1.125V */ |
327 | if (tps65217_voltage_update(TPS65217_DEFDCDC3, | |
328 | TPS65217_DCDC_VOLT_SEL_1125MV)) { | |
329 | puts("tps65217_voltage_update failure\n"); | |
330 | return; | |
331 | } | |
332 | ||
333 | /* Set CORE Frequencies to OPP100 */ | |
334 | do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); | |
9721027a TR |
335 | |
336 | /* Set DCDC2 (MPU) voltage */ | |
337 | if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { | |
338 | puts("tps65217_voltage_update failure\n"); | |
339 | return; | |
340 | } | |
341 | ||
342 | /* | |
343 | * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. | |
344 | * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. | |
345 | */ | |
770e68c0 | 346 | if (board_is_bone()) { |
9721027a TR |
347 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, |
348 | TPS65217_DEFLS1, | |
349 | TPS65217_LDO_VOLTAGE_OUT_3_3, | |
350 | TPS65217_LDO_MASK)) | |
351 | puts("tps65217_reg_write failure\n"); | |
352 | } else { | |
353 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, | |
354 | TPS65217_DEFLS1, | |
355 | TPS65217_LDO_VOLTAGE_OUT_1_8, | |
356 | TPS65217_LDO_MASK)) | |
357 | puts("tps65217_reg_write failure\n"); | |
358 | } | |
359 | ||
360 | if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, | |
361 | TPS65217_DEFLS2, | |
362 | TPS65217_LDO_VOLTAGE_OUT_3_3, | |
363 | TPS65217_LDO_MASK)) | |
364 | puts("tps65217_reg_write failure\n"); | |
365 | } else { | |
366 | int sil_rev; | |
367 | ||
368 | /* | |
369 | * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all | |
370 | * MPU frequencies we support we use a CORE voltage of | |
371 | * 1.1375V. For MPU voltage we need to switch based on | |
372 | * the frequency we are running at. | |
373 | */ | |
374 | if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) | |
375 | return; | |
376 | ||
377 | /* | |
378 | * Depending on MPU clock and PG we will need a different | |
379 | * VDD to drive at that speed. | |
380 | */ | |
381 | sil_rev = readl(&cdev->deviceid) >> 28; | |
52f7d844 SK |
382 | mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, |
383 | dpll_mpu_opp100.m); | |
9721027a TR |
384 | |
385 | /* Tell the TPS65910 to use i2c */ | |
386 | tps65910_set_i2c_control(); | |
387 | ||
388 | /* First update MPU voltage. */ | |
389 | if (tps65910_voltage_update(MPU, mpu_vdd)) | |
390 | return; | |
391 | ||
392 | /* Second, update the CORE voltage. */ | |
393 | if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) | |
394 | return; | |
52f7d844 SK |
395 | |
396 | /* Set CORE Frequencies to OPP100 */ | |
397 | do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); | |
9721027a TR |
398 | } |
399 | ||
400 | /* Set MPU Frequency to what we detected now that voltages are set */ | |
52f7d844 | 401 | do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); |
9721027a TR |
402 | } |
403 | ||
94d77fb6 LV |
404 | const struct dpll_params *get_dpll_ddr_params(void) |
405 | { | |
770e68c0 | 406 | if (board_is_evm_sk()) |
94d77fb6 | 407 | return &dpll_ddr_evm_sk; |
d8ff4fdb | 408 | else if (board_is_bone_lt() || board_is_icev2()) |
94d77fb6 | 409 | return &dpll_ddr_bone_black; |
770e68c0 | 410 | else if (board_is_evm_15_or_later()) |
94d77fb6 LV |
411 | return &dpll_ddr_evm_sk; |
412 | else | |
413 | return &dpll_ddr; | |
414 | } | |
415 | ||
0660481a | 416 | void set_uart_mux_conf(void) |
e363426e | 417 | { |
1286b7f6 | 418 | #if CONFIG_CONS_INDEX == 1 |
e363426e | 419 | enable_uart0_pin_mux(); |
1286b7f6 | 420 | #elif CONFIG_CONS_INDEX == 2 |
6422b70b | 421 | enable_uart1_pin_mux(); |
1286b7f6 | 422 | #elif CONFIG_CONS_INDEX == 3 |
6422b70b | 423 | enable_uart2_pin_mux(); |
1286b7f6 | 424 | #elif CONFIG_CONS_INDEX == 4 |
6422b70b | 425 | enable_uart3_pin_mux(); |
1286b7f6 | 426 | #elif CONFIG_CONS_INDEX == 5 |
6422b70b | 427 | enable_uart4_pin_mux(); |
1286b7f6 | 428 | #elif CONFIG_CONS_INDEX == 6 |
6422b70b | 429 | enable_uart5_pin_mux(); |
1286b7f6 | 430 | #endif |
0660481a | 431 | } |
e363426e | 432 | |
0660481a HS |
433 | void set_mux_conf_regs(void) |
434 | { | |
770e68c0 | 435 | enable_board_pin_mux(); |
0660481a | 436 | } |
e363426e | 437 | |
965de8b9 LV |
438 | const struct ctrl_ioregs ioregs_evmsk = { |
439 | .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, | |
440 | .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, | |
441 | .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, | |
442 | .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, | |
443 | .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, | |
444 | }; | |
445 | ||
446 | const struct ctrl_ioregs ioregs_bonelt = { | |
447 | .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
448 | .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
449 | .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
450 | .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
451 | .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
452 | }; | |
453 | ||
454 | const struct ctrl_ioregs ioregs_evm15 = { | |
455 | .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, | |
456 | .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, | |
457 | .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, | |
458 | .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, | |
459 | .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, | |
460 | }; | |
461 | ||
462 | const struct ctrl_ioregs ioregs = { | |
463 | .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, | |
464 | .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, | |
465 | .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, | |
466 | .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, | |
467 | .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, | |
468 | }; | |
469 | ||
0660481a HS |
470 | void sdram_init(void) |
471 | { | |
770e68c0 | 472 | if (board_is_evm_sk()) { |
e363426e PK |
473 | /* |
474 | * EVM SK 1.2A and later use gpio0_7 to enable DDR3. | |
475 | * This is safe enough to do on older revs. | |
476 | */ | |
477 | gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); | |
478 | gpio_direction_output(GPIO_DDR_VTT_EN, 1); | |
479 | } | |
480 | ||
d8ff4fdb LV |
481 | if (board_is_icev2()) { |
482 | gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); | |
483 | gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); | |
484 | } | |
485 | ||
770e68c0 | 486 | if (board_is_evm_sk()) |
965de8b9 | 487 | config_ddr(303, &ioregs_evmsk, &ddr3_data, |
3ba65f97 | 488 | &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); |
770e68c0 | 489 | else if (board_is_bone_lt()) |
965de8b9 | 490 | config_ddr(400, &ioregs_bonelt, |
c7ba18ad TR |
491 | &ddr3_beagleblack_data, |
492 | &ddr3_beagleblack_cmd_ctrl_data, | |
493 | &ddr3_beagleblack_emif_reg_data, 0); | |
770e68c0 | 494 | else if (board_is_evm_15_or_later()) |
965de8b9 | 495 | config_ddr(303, &ioregs_evm15, &ddr3_evm_data, |
3ba65f97 | 496 | &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); |
d8ff4fdb LV |
497 | else if (board_is_icev2()) |
498 | config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, | |
499 | &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, | |
500 | 0); | |
8c17cbdf JS |
501 | else if (board_is_gp_evm()) |
502 | config_ddr(266, &ioregs, &ddr2_data, | |
503 | &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0); | |
c00f69db | 504 | else |
965de8b9 | 505 | config_ddr(266, &ioregs, &ddr2_data, |
3ba65f97 | 506 | &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); |
e363426e | 507 | } |
0660481a | 508 | #endif |
e363426e | 509 | |
e607ec99 | 510 | #if !defined(CONFIG_SPL_BUILD) || \ |
97f3a178 | 511 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) |
e607ec99 | 512 | static void request_and_set_gpio(int gpio, char *name, int val) |
97f3a178 LV |
513 | { |
514 | int ret; | |
515 | ||
516 | ret = gpio_request(gpio, name); | |
517 | if (ret < 0) { | |
518 | printf("%s: Unable to request %s\n", __func__, name); | |
519 | return; | |
520 | } | |
521 | ||
522 | ret = gpio_direction_output(gpio, 0); | |
523 | if (ret < 0) { | |
524 | printf("%s: Unable to set %s as output\n", __func__, name); | |
525 | goto err_free_gpio; | |
526 | } | |
527 | ||
e607ec99 | 528 | gpio_set_value(gpio, val); |
97f3a178 LV |
529 | |
530 | return; | |
531 | ||
532 | err_free_gpio: | |
533 | gpio_free(gpio); | |
534 | } | |
535 | ||
e607ec99 RQ |
536 | #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1); |
537 | #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0); | |
97f3a178 LV |
538 | |
539 | /** | |
540 | * RMII mode on ICEv2 board needs 50MHz clock. Given the clock | |
541 | * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle | |
542 | * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to | |
543 | * give 50MHz output for Eth0 and 1. | |
544 | */ | |
545 | static struct clk_synth cdce913_data = { | |
546 | .id = 0x81, | |
547 | .capacitor = 0x90, | |
548 | .mux = 0x6d, | |
549 | .pdiv2 = 0x2, | |
550 | .pdiv3 = 0x2, | |
551 | }; | |
552 | #endif | |
553 | ||
e363426e PK |
554 | /* |
555 | * Basic board specific setup. Pinmux has been handled already. | |
556 | */ | |
557 | int board_init(void) | |
558 | { | |
6843918e TR |
559 | #if defined(CONFIG_HW_WATCHDOG) |
560 | hw_watchdog_init(); | |
561 | #endif | |
562 | ||
73feefdc | 563 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
2c17e6d1 | 564 | #if defined(CONFIG_NOR) || defined(CONFIG_NAND) |
98b5c269 | 565 | gpmc_init(); |
cd8845d7 | 566 | #endif |
97f3a178 | 567 | |
e607ec99 RQ |
568 | #if !defined(CONFIG_SPL_BUILD) || \ |
569 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) | |
97f3a178 | 570 | if (board_is_icev2()) { |
e607ec99 RQ |
571 | int rv; |
572 | u32 reg; | |
573 | ||
97f3a178 | 574 | REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); |
e607ec99 RQ |
575 | /* Make J19 status available on GPIO1_26 */ |
576 | REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL); | |
577 | ||
97f3a178 | 578 | REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); |
e607ec99 RQ |
579 | /* |
580 | * Both ports can be set as RMII-CPSW or MII-PRU-ETH using | |
581 | * jumpers near the port. Read the jumper value and set | |
582 | * the pinmux, external mux and PHY clock accordingly. | |
583 | * As jumper line is overridden by PHY RX_DV pin immediately | |
584 | * after bootstrap (power-up/reset), we need to sample | |
585 | * it during PHY reset using GPIO rising edge detection. | |
586 | */ | |
97f3a178 | 587 | REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); |
e607ec99 RQ |
588 | /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */ |
589 | reg = readl(GPIO0_RISINGDETECT) | BIT(11); | |
590 | writel(reg, GPIO0_RISINGDETECT); | |
591 | reg = readl(GPIO1_RISINGDETECT) | BIT(26); | |
592 | writel(reg, GPIO1_RISINGDETECT); | |
593 | /* Reset PHYs to capture the Jumper setting */ | |
594 | gpio_set_value(GPIO_PHY_RESET, 0); | |
595 | udelay(2); /* PHY datasheet states 1uS min. */ | |
596 | gpio_set_value(GPIO_PHY_RESET, 1); | |
597 | ||
598 | reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11); | |
599 | if (reg) { | |
600 | writel(reg, GPIO0_IRQSTATUS1); /* clear irq */ | |
601 | /* RMII mode */ | |
602 | printf("ETH0, CPSW\n"); | |
603 | } else { | |
604 | /* MII mode */ | |
605 | printf("ETH0, PRU\n"); | |
606 | cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */ | |
607 | } | |
608 | ||
609 | reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26); | |
610 | if (reg) { | |
611 | writel(reg, GPIO1_IRQSTATUS1); /* clear irq */ | |
612 | /* RMII mode */ | |
613 | printf("ETH1, CPSW\n"); | |
614 | gpio_set_value(GPIO_MUX_MII_CTRL, 1); | |
615 | } else { | |
616 | /* MII mode */ | |
617 | printf("ETH1, PRU\n"); | |
618 | cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */ | |
619 | } | |
620 | ||
621 | /* disable rising edge IRQs */ | |
622 | reg = readl(GPIO0_RISINGDETECT) & ~BIT(11); | |
623 | writel(reg, GPIO0_RISINGDETECT); | |
624 | reg = readl(GPIO1_RISINGDETECT) & ~BIT(26); | |
625 | writel(reg, GPIO1_RISINGDETECT); | |
97f3a178 LV |
626 | |
627 | rv = setup_clock_synthesizer(&cdce913_data); | |
628 | if (rv) { | |
629 | printf("Clock synthesizer setup failed %d\n", rv); | |
630 | return rv; | |
631 | } | |
e607ec99 RQ |
632 | |
633 | /* reset PHYs */ | |
634 | gpio_set_value(GPIO_PHY_RESET, 0); | |
635 | udelay(2); /* PHY datasheet states 1uS min. */ | |
636 | gpio_set_value(GPIO_PHY_RESET, 1); | |
97f3a178 LV |
637 | } |
638 | #endif | |
639 | ||
e363426e PK |
640 | return 0; |
641 | } | |
642 | ||
044fc14b TR |
643 | #ifdef CONFIG_BOARD_LATE_INIT |
644 | int board_late_init(void) | |
645 | { | |
f411b5cc RQ |
646 | #if !defined(CONFIG_SPL_BUILD) |
647 | uint8_t mac_addr[6]; | |
648 | uint32_t mac_hi, mac_lo; | |
649 | #endif | |
650 | ||
044fc14b | 651 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
770e68c0 | 652 | char *name = NULL; |
ace4275e | 653 | |
770e68c0 NM |
654 | if (board_is_bbg1()) |
655 | name = "BBG1"; | |
656 | set_board_info_env(name); | |
5d4d436c LV |
657 | |
658 | /* | |
659 | * Default FIT boot on HS devices. Non FIT images are not allowed | |
660 | * on HS devices. | |
661 | */ | |
662 | if (get_device_type() == HS_DEVICE) | |
663 | setenv("boot_fit", "1"); | |
044fc14b TR |
664 | #endif |
665 | ||
f411b5cc RQ |
666 | #if !defined(CONFIG_SPL_BUILD) |
667 | /* try reading mac address from efuse */ | |
668 | mac_lo = readl(&cdev->macid0l); | |
669 | mac_hi = readl(&cdev->macid0h); | |
670 | mac_addr[0] = mac_hi & 0xFF; | |
671 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; | |
672 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; | |
673 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; | |
674 | mac_addr[4] = mac_lo & 0xFF; | |
675 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; | |
676 | ||
677 | if (!getenv("ethaddr")) { | |
678 | printf("<ethaddr> not set. Validating first E-fuse MAC\n"); | |
679 | ||
680 | if (is_valid_ethaddr(mac_addr)) | |
681 | eth_setenv_enetaddr("ethaddr", mac_addr); | |
682 | } | |
683 | ||
684 | mac_lo = readl(&cdev->macid1l); | |
685 | mac_hi = readl(&cdev->macid1h); | |
686 | mac_addr[0] = mac_hi & 0xFF; | |
687 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; | |
688 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; | |
689 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; | |
690 | mac_addr[4] = mac_lo & 0xFF; | |
691 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; | |
692 | ||
693 | if (!getenv("eth1addr")) { | |
694 | if (is_valid_ethaddr(mac_addr)) | |
695 | eth_setenv_enetaddr("eth1addr", mac_addr); | |
696 | } | |
697 | #endif | |
698 | ||
044fc14b TR |
699 | return 0; |
700 | } | |
701 | #endif | |
702 | ||
bd83e3df M |
703 | #ifndef CONFIG_DM_ETH |
704 | ||
c0e66793 IY |
705 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ |
706 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) | |
e363426e PK |
707 | static void cpsw_control(int enabled) |
708 | { | |
709 | /* VTP can be added here */ | |
710 | ||
711 | return; | |
712 | } | |
713 | ||
714 | static struct cpsw_slave_data cpsw_slaves[] = { | |
715 | { | |
716 | .slave_reg_ofs = 0x208, | |
717 | .sliver_reg_ofs = 0xd80, | |
9c653aad | 718 | .phy_addr = 0, |
e363426e PK |
719 | }, |
720 | { | |
721 | .slave_reg_ofs = 0x308, | |
722 | .sliver_reg_ofs = 0xdc0, | |
9c653aad | 723 | .phy_addr = 1, |
e363426e PK |
724 | }, |
725 | }; | |
726 | ||
727 | static struct cpsw_platform_data cpsw_data = { | |
81df2bab MP |
728 | .mdio_base = CPSW_MDIO_BASE, |
729 | .cpsw_base = CPSW_BASE, | |
e363426e PK |
730 | .mdio_div = 0xff, |
731 | .channels = 8, | |
732 | .cpdma_reg_ofs = 0x800, | |
733 | .slaves = 1, | |
734 | .slave_data = cpsw_slaves, | |
735 | .ale_reg_ofs = 0xd00, | |
736 | .ale_entries = 1024, | |
737 | .host_port_reg_ofs = 0x108, | |
738 | .hw_stats_reg_ofs = 0x900, | |
2bf36ac6 | 739 | .bd_ram_ofs = 0x2000, |
e363426e PK |
740 | .mac_control = (1 << 5), |
741 | .control = cpsw_control, | |
742 | .host_port_num = 0, | |
743 | .version = CPSW_CTRL_VERSION_2, | |
744 | }; | |
d2aa1154 | 745 | #endif |
e363426e | 746 | |
97f3a178 LV |
747 | #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\ |
748 | defined(CONFIG_SPL_BUILD)) || \ | |
749 | ((defined(CONFIG_DRIVER_TI_CPSW) || \ | |
750 | defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ | |
751 | !defined(CONFIG_SPL_BUILD)) | |
752 | ||
68996b84 TR |
753 | /* |
754 | * This function will: | |
755 | * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr | |
756 | * in the environment | |
757 | * Perform fixups to the PHY present on certain boards. We only need this | |
758 | * function in: | |
759 | * - SPL with either CPSW or USB ethernet support | |
760 | * - Full U-Boot, with either CPSW or USB ethernet | |
761 | * Build in only these cases to avoid warnings about unused variables | |
762 | * when we build an SPL that has neither option but full U-Boot will. | |
763 | */ | |
e363426e PK |
764 | int board_eth_init(bd_t *bis) |
765 | { | |
d2aa1154 | 766 | int rv, n = 0; |
f411b5cc RQ |
767 | #if defined(CONFIG_USB_ETHER) && \ |
768 | (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) | |
e363426e PK |
769 | uint8_t mac_addr[6]; |
770 | uint32_t mac_hi, mac_lo; | |
771 | ||
f411b5cc RQ |
772 | /* |
773 | * use efuse mac address for USB ethernet as we know that | |
774 | * both CPSW and USB ethernet will never be active at the same time | |
775 | */ | |
c0e66793 IY |
776 | mac_lo = readl(&cdev->macid0l); |
777 | mac_hi = readl(&cdev->macid0h); | |
778 | mac_addr[0] = mac_hi & 0xFF; | |
779 | mac_addr[1] = (mac_hi & 0xFF00) >> 8; | |
780 | mac_addr[2] = (mac_hi & 0xFF0000) >> 16; | |
781 | mac_addr[3] = (mac_hi & 0xFF000000) >> 24; | |
782 | mac_addr[4] = mac_lo & 0xFF; | |
783 | mac_addr[5] = (mac_lo & 0xFF00) >> 8; | |
f411b5cc RQ |
784 | #endif |
785 | ||
c0e66793 IY |
786 | |
787 | #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ | |
788 | (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) | |
e363426e | 789 | |
a662e0c3 | 790 | #ifdef CONFIG_DRIVER_TI_CPSW |
770e68c0 NM |
791 | if (board_is_bone() || board_is_bone_lt() || |
792 | board_is_idk()) { | |
e363426e PK |
793 | writel(MII_MODE_ENABLE, &cdev->miisel); |
794 | cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = | |
795 | PHY_INTERFACE_MODE_MII; | |
97f3a178 LV |
796 | } else if (board_is_icev2()) { |
797 | writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); | |
798 | cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; | |
799 | cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; | |
800 | cpsw_slaves[0].phy_addr = 1; | |
801 | cpsw_slaves[1].phy_addr = 3; | |
e363426e | 802 | } else { |
dafd4db3 | 803 | writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); |
e363426e PK |
804 | cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = |
805 | PHY_INTERFACE_MODE_RGMII; | |
806 | } | |
807 | ||
d2aa1154 IY |
808 | rv = cpsw_register(&cpsw_data); |
809 | if (rv < 0) | |
810 | printf("Error %d registering CPSW switch\n", rv); | |
811 | else | |
812 | n += rv; | |
a662e0c3 | 813 | #endif |
1634e969 TR |
814 | |
815 | /* | |
816 | * | |
817 | * CPSW RGMII Internal Delay Mode is not supported in all PVT | |
818 | * operating points. So we must set the TX clock delay feature | |
819 | * in the AR8051 PHY. Since we only support a single ethernet | |
820 | * device in U-Boot, we only do this for the first instance. | |
821 | */ | |
822 | #define AR8051_PHY_DEBUG_ADDR_REG 0x1d | |
823 | #define AR8051_PHY_DEBUG_DATA_REG 0x1e | |
824 | #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 | |
825 | #define AR8051_RGMII_TX_CLK_DLY 0x100 | |
826 | ||
770e68c0 | 827 | if (board_is_evm_sk() || board_is_gp_evm()) { |
1634e969 TR |
828 | const char *devname; |
829 | devname = miiphy_get_current_dev(); | |
830 | ||
831 | miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, | |
832 | AR8051_DEBUG_RGMII_CLK_DLY_REG); | |
833 | miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, | |
834 | AR8051_RGMII_TX_CLK_DLY); | |
835 | } | |
d2aa1154 | 836 | #endif |
c0e66793 IY |
837 | #if defined(CONFIG_USB_ETHER) && \ |
838 | (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) | |
0adb5b76 | 839 | if (is_valid_ethaddr(mac_addr)) |
c0e66793 IY |
840 | eth_setenv_enetaddr("usbnet_devaddr", mac_addr); |
841 | ||
d2aa1154 IY |
842 | rv = usb_eth_initialize(bis); |
843 | if (rv < 0) | |
844 | printf("Error %d registering USB_ETHER\n", rv); | |
845 | else | |
846 | n += rv; | |
847 | #endif | |
848 | return n; | |
e363426e PK |
849 | } |
850 | #endif | |
bd83e3df M |
851 | |
852 | #endif /* CONFIG_DM_ETH */ | |
505ea6e8 LV |
853 | |
854 | #ifdef CONFIG_SPL_LOAD_FIT | |
855 | int board_fit_config_name_match(const char *name) | |
856 | { | |
857 | if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) | |
858 | return 0; | |
859 | else if (board_is_bone() && !strcmp(name, "am335x-bone")) | |
860 | return 0; | |
861 | else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) | |
862 | return 0; | |
3819ea70 LV |
863 | else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) |
864 | return 0; | |
da9d9599 LV |
865 | else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) |
866 | return 0; | |
73ec6960 LV |
867 | else if (board_is_icev2() && !strcmp(name, "am335x-icev2")) |
868 | return 0; | |
505ea6e8 LV |
869 | else |
870 | return -1; | |
871 | } | |
872 | #endif | |
b0a4eea1 AD |
873 | |
874 | #ifdef CONFIG_TI_SECURE_DEVICE | |
875 | void board_fit_image_post_process(void **p_image, size_t *p_size) | |
876 | { | |
877 | secure_boot_verify_image(p_image, p_size); | |
878 | } | |
879 | #endif |