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board: ti: dra76-evm: Add epprom support
[people/ms/u-boot.git] / board / ti / dra7xx / evm.c
CommitLineData
687054a7
LV		 1/*
2 * (C) Copyright 2013
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Lokesh Vutla <lokeshvutla@ti.com>
6 *
7 * Based on previous work by:
8 * Aneesh V <aneesh@ti.com>
9 * Steve Sakoman <steve@sakoman.com>
10 *
1a459660 11 * SPDX-License-Identifier: GPL-2.0+
687054a7
LV		 12 */
13#include <common.h>
cb199102 14#include <palmas.h>
e9024ef2 15#include <sata.h>
25afe55d 16#include <linux/string.h>
7b922523 17#include <asm/gpio.h>
a17188c1
KVA		 18#include <usb.h>
19#include <linux/usb/gadget.h>
17c29873
AD		 20#include <asm/omap_common.h>
21#include <asm/omap_sec_common.h>
7b922523 22#include <asm/arch/gpio.h>
706dd348 23#include <asm/arch/dra7xx_iodelay.h>
a7638833 24#include <asm/emif.h>
687054a7
LV		 25#include <asm/arch/sys_proto.h>
26#include <asm/arch/mmc_host_def.h>
21914ee6 27#include <asm/arch/sata.h>
79b079f3 28#include <environment.h>
a17188c1
KVA		 29#include <dwc3-uboot.h>
30#include <dwc3-omap-uboot.h>
31#include <ti-usb-phy-uboot.h>
39fbac91 32#include <miiphy.h>
687054a7
LV		 33
34#include "mux_data.h"
25afe55d
LV		 35#include "../common/board_detect.h"
36
c8c04eca 37#define board_is_dra76x_evm() board_ti_is("DRA76/7x")
25afe55d 38#define board_is_dra74x_evm() board_ti_is("5777xCPU")
6b1c14bb 39#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
463dd225 40#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
1053a769
M		 41#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
42 (strncmp("H", board_ti_get_rev(), 1) <= 0))
43#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
44 (strncmp("C", board_ti_get_rev(), 1) <= 0))
c4a2736c
LV		 45#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
46 board_ti_get_emif2_size()
687054a7 47
b1e26e3b
M		 48#ifdef CONFIG_DRIVER_TI_CPSW
49#include <cpsw.h>
50#endif
51
687054a7
LV		 52DECLARE_GLOBAL_DATA_PTR;
53
7b922523
LV		 54/* GPIO 7_11 */
55#define GPIO_DDR_VTT_EN 203
56
25afe55d
LV		 57#define SYSINFO_BOARD_NAME_MAX_LEN 37
58
687054a7 59const struct omap_sysinfo sysinfo = {
25afe55d 60 "Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
687054a7
LV		 61};
62
a7638833
LV		 63static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
64 .sdram_config_init = 0x61851ab2,
65 .sdram_config = 0x61851ab2,
66 .sdram_config2 = 0x08000000,
67 .ref_ctrl = 0x000040F1,
68 .ref_ctrl_final = 0x00001035,
69 .sdram_tim1 = 0xCCCF36B3,
70 .sdram_tim2 = 0x308F7FDA,
71 .sdram_tim3 = 0x427F88A8,
72 .read_idle_ctrl = 0x00050000,
73 .zq_config = 0x0007190B,
74 .temp_alert_config = 0x00000000,
75 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
76 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
77 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
78 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
79 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
80 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
81 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
82 .emif_rd_wr_lvl_rmp_win = 0x00000000,
83 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
84 .emif_rd_wr_lvl_ctl = 0x00000000,
85 .emif_rd_wr_exec_thresh = 0x00000305
86};
87
88static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
89 .sdram_config_init = 0x61851B32,
90 .sdram_config = 0x61851B32,
91 .sdram_config2 = 0x08000000,
92 .ref_ctrl = 0x000040F1,
93 .ref_ctrl_final = 0x00001035,
94 .sdram_tim1 = 0xCCCF36B3,
95 .sdram_tim2 = 0x308F7FDA,
96 .sdram_tim3 = 0x427F88A8,
97 .read_idle_ctrl = 0x00050000,
98 .zq_config = 0x0007190B,
99 .temp_alert_config = 0x00000000,
100 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
101 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
102 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
103 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
104 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
105 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
106 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
107 .emif_rd_wr_lvl_rmp_win = 0x00000000,
108 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
109 .emif_rd_wr_lvl_ctl = 0x00000000,
110 .emif_rd_wr_exec_thresh = 0x00000305
111};
112
113static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
114 .sdram_config_init = 0x61862B32,
115 .sdram_config = 0x61862B32,
116 .sdram_config2 = 0x08000000,
117 .ref_ctrl = 0x0000514C,
118 .ref_ctrl_final = 0x0000144A,
119 .sdram_tim1 = 0xD113781C,
120 .sdram_tim2 = 0x30717FE3,
121 .sdram_tim3 = 0x409F86A8,
122 .read_idle_ctrl = 0x00050000,
123 .zq_config = 0x5007190B,
124 .temp_alert_config = 0x00000000,
125 .emif_ddr_phy_ctlr_1_init = 0x0024400D,
126 .emif_ddr_phy_ctlr_1 = 0x0E24400D,
127 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
128 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
129 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
130 .emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
131 .emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
132 .emif_rd_wr_lvl_rmp_win = 0x00000000,
133 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
134 .emif_rd_wr_lvl_ctl = 0x00000000,
135 .emif_rd_wr_exec_thresh = 0x00000305
136};
137
6b1c14bb
RB		 138const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
139 .sdram_config_init = 0x61862BB2,
140 .sdram_config = 0x61862BB2,
141 .sdram_config2 = 0x00000000,
142 .ref_ctrl = 0x0000514D,
143 .ref_ctrl_final = 0x0000144A,
144 .sdram_tim1 = 0xD1137824,
145 .sdram_tim2 = 0x30B37FE3,
146 .sdram_tim3 = 0x409F8AD8,
147 .read_idle_ctrl = 0x00050000,
148 .zq_config = 0x5007190B,
149 .temp_alert_config = 0x00000000,
150 .emif_ddr_phy_ctlr_1_init = 0x0824400E,
151 .emif_ddr_phy_ctlr_1 = 0x0E24400E,
152 .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
153 .emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
154 .emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
155 .emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
156 .emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
157 .emif_rd_wr_lvl_rmp_win = 0x00000000,
158 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
159 .emif_rd_wr_lvl_ctl = 0x00000000,
160 .emif_rd_wr_exec_thresh = 0x00000305
161};
162
c4a2736c
LV		 163const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
164 .sdram_config_init = 0x61851ab2,
165 .sdram_config = 0x61851ab2,
166 .sdram_config2 = 0x08000000,
167 .ref_ctrl = 0x000040F1,
168 .ref_ctrl_final = 0x00001035,
169 .sdram_tim1 = 0xCCCF36B3,
170 .sdram_tim2 = 0x30BF7FDA,
171 .sdram_tim3 = 0x427F8BA8,
172 .read_idle_ctrl = 0x00050000,
173 .zq_config = 0x0007190B,
174 .temp_alert_config = 0x00000000,
175 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
176 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
177 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
178 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
179 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
180 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
181 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
182 .emif_rd_wr_lvl_rmp_win = 0x00000000,
183 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
184 .emif_rd_wr_lvl_ctl = 0x00000000,
185 .emif_rd_wr_exec_thresh = 0x00000305
186};
187
188const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
189 .sdram_config_init = 0x61851B32,
190 .sdram_config = 0x61851B32,
191 .sdram_config2 = 0x08000000,
192 .ref_ctrl = 0x000040F1,
193 .ref_ctrl_final = 0x00001035,
194 .sdram_tim1 = 0xCCCF36B3,
195 .sdram_tim2 = 0x308F7FDA,
196 .sdram_tim3 = 0x427F88A8,
197 .read_idle_ctrl = 0x00050000,
198 .zq_config = 0x0007190B,
199 .temp_alert_config = 0x00000000,
200 .emif_ddr_phy_ctlr_1_init = 0x0024400B,
201 .emif_ddr_phy_ctlr_1 = 0x0E24400B,
202 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
203 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
204 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
205 .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
206 .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
207 .emif_rd_wr_lvl_rmp_win = 0x00000000,
208 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
209 .emif_rd_wr_lvl_ctl = 0x00000000,
210 .emif_rd_wr_exec_thresh = 0x00000305
211};
212
a7638833
LV		 213void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
214{
c4a2736c
LV		 215 u64 ram_size;
216
217 ram_size = board_ti_get_emif_size();
218
a7638833
LV		 219 switch (omap_revision()) {
220 case DRA752_ES1_0:
221 case DRA752_ES1_1:
222 case DRA752_ES2_0:
223 switch (emif_nr) {
224 case 1:
c4a2736c
LV		 225 if (ram_size > CONFIG_MAX_MEM_MAPPED)
226 *regs = &emif1_ddr3_532_mhz_1cs_2G;
227 else
228 *regs = &emif1_ddr3_532_mhz_1cs;
a7638833
LV		 229 break;
230 case 2:
c4a2736c
LV		 231 if (ram_size > CONFIG_MAX_MEM_MAPPED)
232 *regs = &emif2_ddr3_532_mhz_1cs_2G;
233 else
234 *regs = &emif2_ddr3_532_mhz_1cs;
a7638833
LV		 235 break;
236 }
237 break;
238 case DRA722_ES1_0:
6b1c14bb
RB		 239 case DRA722_ES2_0:
240 if (ram_size < CONFIG_MAX_MEM_MAPPED)
241 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
242 else
243 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
a7638833
LV		 244 break;
245 default:
246 *regs = &emif1_ddr3_532_mhz_1cs;
247 }
248}
249
250static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
251 .dmm_lisa_map_0 = 0x0,
252 .dmm_lisa_map_1 = 0x80640300,
253 .dmm_lisa_map_2 = 0xC0500220,
254 .dmm_lisa_map_3 = 0xFF020100,
255 .is_ma_present = 0x1
256};
257
258static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
259 .dmm_lisa_map_0 = 0x0,
260 .dmm_lisa_map_1 = 0x0,
261 .dmm_lisa_map_2 = 0x80600100,
262 .dmm_lisa_map_3 = 0xFF020100,
263 .is_ma_present = 0x1
264};
265
c4a2736c
LV		 266const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
267 .dmm_lisa_map_0 = 0x0,
268 .dmm_lisa_map_1 = 0x0,
269 .dmm_lisa_map_2 = 0x80740300,
270 .dmm_lisa_map_3 = 0xFF020100,
271 .is_ma_present = 0x1
272};
273
6b1c14bb
RB		 274/*
275 * DRA722 EVM EMIF1 2GB CONFIGURATION
276 * EMIF1 4 devices of 512Mb x 8 Micron
277 */
278const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
279 .dmm_lisa_map_0 = 0x0,
280 .dmm_lisa_map_1 = 0x0,
281 .dmm_lisa_map_2 = 0x80700100,
282 .dmm_lisa_map_3 = 0xFF020100,
283 .is_ma_present = 0x1
284};
285
a7638833
LV		 286void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
287{
c4a2736c
LV		 288 u64 ram_size;
289
290 ram_size = board_ti_get_emif_size();
291
a7638833
LV		 292 switch (omap_revision()) {
293 case DRA752_ES1_0:
294 case DRA752_ES1_1:
295 case DRA752_ES2_0:
c4a2736c
LV		 296 if (ram_size > CONFIG_MAX_MEM_MAPPED)
297 *dmm_lisa_regs = &lisa_map_dra7_2GB;
298 else
299 *dmm_lisa_regs = &lisa_map_dra7_1536MB;
a7638833
LV		 300 break;
301 case DRA722_ES1_0:
6b1c14bb 302 case DRA722_ES2_0:
a7638833 303 default:
6b1c14bb
RB		 304 if (ram_size < CONFIG_MAX_MEM_MAPPED)
305 *dmm_lisa_regs = &lisa_map_2G_x_2;
306 else
307 *dmm_lisa_regs = &lisa_map_2G_x_4;
308 break;
a7638833
LV		 309 }
310}
311
1428d832 312struct vcores_data dra752_volts = {
beb71279
LV		 313 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
314 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
1428d832
K		 315 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
316 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
317 .mpu.pmic = &tps659038,
318 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
319
beb71279
LV		 320 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
321 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
322 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
323 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
324 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
325 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
1428d832
K		 326 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
327 .eve.addr = TPS659038_REG_ADDR_SMPS45,
328 .eve.pmic = &tps659038,
329 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
330
beb71279
LV		 331 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
332 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
333 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
334 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
335 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
336 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
1428d832
K		 337 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
338 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
339 .gpu.pmic = &tps659038,
340 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
341
beb71279
LV		 342 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
343 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
1428d832
K		 344 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
345 .core.addr = TPS659038_REG_ADDR_SMPS7,
346 .core.pmic = &tps659038,
347
beb71279
LV		 348 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
349 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
350 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
351 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
352 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
353 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
1428d832
K		 354 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
355 .iva.addr = TPS659038_REG_ADDR_SMPS8,
356 .iva.pmic = &tps659038,
357 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
358};
359
360struct vcores_data dra722_volts = {
beb71279
LV		 361 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
362 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
1428d832
K		 363 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
364 .mpu.addr = TPS65917_REG_ADDR_SMPS1,
365 .mpu.pmic = &tps659038,
366 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
367
beb71279
LV		 368 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
369 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
1428d832
K		 370 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
371 .core.addr = TPS65917_REG_ADDR_SMPS2,
372 .core.pmic = &tps659038,
373
374 /*
375 * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
376 * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
377 */
beb71279
LV		 378 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
379 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
380 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
381 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
382 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
383 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
1428d832
K		 384 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
385 .gpu.addr = TPS65917_REG_ADDR_SMPS3,
386 .gpu.pmic = &tps659038,
387 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
388
beb71279
LV		 389 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
390 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
391 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
392 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
393 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
394 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
1428d832
K		 395 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
396 .eve.addr = TPS65917_REG_ADDR_SMPS3,
397 .eve.pmic = &tps659038,
398 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
399
beb71279
LV		 400 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
401 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
402 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
403 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
404 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
405 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
1428d832
K		 406 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
407 .iva.addr = TPS65917_REG_ADDR_SMPS3,
408 .iva.pmic = &tps659038,
409 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
410};
411
f56e6350
K		 412struct vcores_data dra718_volts = {
413 /*
414 * In the case of dra71x GPU MPU and CORE
415 * are all powered up by BUCK0 of LP873X PMIC
416 */
417 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
418 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
419 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
420 .mpu.addr = LP873X_REG_ADDR_BUCK0,
421 .mpu.pmic = &lp8733,
422 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
423
424 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
425 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
426 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
427 .core.addr = LP873X_REG_ADDR_BUCK0,
428 .core.pmic = &lp8733,
429
430 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
431 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
432 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
433 .gpu.addr = LP873X_REG_ADDR_BUCK0,
434 .gpu.pmic = &lp8733,
435 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
436
437 /*
438 * The DSPEVE and IVA rails are grouped on DRA71x-evm
439 * and are powered by BUCK1 of LP873X PMIC
440 */
441 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
6cc96bc7 442 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
f56e6350 443 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
6cc96bc7 444 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
f56e6350
K		 445 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
446 .eve.addr = LP873X_REG_ADDR_BUCK1,
447 .eve.pmic = &lp8733,
448 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
449
450 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
6cc96bc7 451 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
f56e6350 452 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
6cc96bc7 453 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
f56e6350
K		 454 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
455 .iva.addr = LP873X_REG_ADDR_BUCK1,
456 .iva.pmic = &lp8733,
457 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
458};
459
beb71279
LV		 460int get_voltrail_opp(int rail_offset)
461{
462 int opp;
463
464 switch (rail_offset) {
465 case VOLT_MPU:
466 opp = DRA7_MPU_OPP;
6cc96bc7
LV		 467 /* DRA71x supports only OPP_NOM for MPU */
468 if (board_is_dra71x_evm())
469 opp = OPP_NOM;
beb71279
LV		 470 break;
471 case VOLT_CORE:
472 opp = DRA7_CORE_OPP;
6cc96bc7
LV		 473 /* DRA71x supports only OPP_NOM for CORE */
474 if (board_is_dra71x_evm())
475 opp = OPP_NOM;
beb71279
LV		 476 break;
477 case VOLT_GPU:
478 opp = DRA7_GPU_OPP;
6cc96bc7
LV		 479 /* DRA71x supports only OPP_NOM for GPU */
480 if (board_is_dra71x_evm())
481 opp = OPP_NOM;
beb71279
LV		 482 break;
483 case VOLT_EVE:
484 opp = DRA7_DSPEVE_OPP;
6cc96bc7
LV		 485 /*
486 * DRA71x does not support OPP_OD for EVE.
487 * If OPP_OD is selected by menuconfig, fallback
488 * to OPP_NOM.
489 */
490 if (board_is_dra71x_evm() && opp == OPP_OD)
491 opp = OPP_NOM;
beb71279
LV		 492 break;
493 case VOLT_IVA:
494 opp = DRA7_IVA_OPP;
6cc96bc7
LV		 495 /*
496 * DRA71x does not support OPP_OD for IVA.
497 * If OPP_OD is selected by menuconfig, fallback
498 * to OPP_NOM.
499 */
500 if (board_is_dra71x_evm() && opp == OPP_OD)
501 opp = OPP_NOM;
beb71279
LV		 502 break;
503 default:
504 opp = OPP_NOM;
505 }
506
507 return opp;
508}
509
687054a7
LV		 510/**
511 * @brief board_init
512 *
513 * @return 0
514 */
515int board_init(void)
516{
517 gpmc_init();
518 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
519
520 return 0;
521}
522
76b00aca 523int dram_init_banksize(void)
d468b178
LV		 524{
525 u64 ram_size;
526
527 ram_size = board_ti_get_emif_size();
528
529 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
530 gd->bd->bi_dram[0].size = get_effective_memsize();
531 if (ram_size > CONFIG_MAX_MEM_MAPPED) {
532 gd->bd->bi_dram[1].start = 0x200000000;
533 gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
534 }
76b00aca
SG		 535
536 return 0;
d468b178
LV		 537}
538
21914ee6
RQ		 539int board_late_init(void)
540{
4ec3f6e5 541#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
25afe55d
LV		 542 char *name = "unknown";
543
df6b506f
LV		 544 if (is_dra72x()) {
545 if (board_is_dra72x_revc_or_later())
546 name = "dra72x-revc";
463dd225
LV		 547 else if (board_is_dra71x_evm())
548 name = "dra71x";
df6b506f
LV		 549 else
550 name = "dra72x";
c8c04eca
LV		 551 } else if (is_dra76x()) {
552 name = "dra76x";
df6b506f 553 } else {
25afe55d 554 name = "dra7xx";
df6b506f 555 }
25afe55d
LV		 556
557 set_board_info_env(name);
f12467d1 558
71c1b58e
LV		 559 /*
560 * Default FIT boot on HS devices. Non FIT images are not allowed
561 * on HS devices.
562 */
563 if (get_device_type() == HS_DEVICE)
382bee57 564 env_set("boot_fit", "1");
71c1b58e 565
07815eb9 566 omap_die_id_serial();
4a30a939 567 omap_set_fastboot_vars();
4ec3f6e5 568#endif
21914ee6
RQ		 569 return 0;
570}
571
25afe55d
LV		 572#ifdef CONFIG_SPL_BUILD
573void do_board_detect(void)
574{
575 int rc;
576
577 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
578 CONFIG_EEPROM_CHIP_ADDRESS);
579 if (rc)
580 printf("ti_i2c_eeprom_init failed %d\n", rc);
581}
582
583#else
584
585void do_board_detect(void)
586{
587 char *bname = NULL;
588 int rc;
589
590 rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
591 CONFIG_EEPROM_CHIP_ADDRESS);
592 if (rc)
593 printf("ti_i2c_eeprom_init failed %d\n", rc);
594
595 if (board_is_dra74x_evm()) {
596 bname = "DRA74x EVM";
6b1c14bb
RB		 597 } else if (board_is_dra72x_evm()) {
598 bname = "DRA72x EVM";
463dd225
LV		 599 } else if (board_is_dra71x_evm()) {
600 bname = "DRA71x EVM";
c8c04eca
LV		 601 } else if (board_is_dra76x_evm()) {
602 bname = "DRA76x EVM";
25afe55d 603 } else {
6b1c14bb 604 /* If EEPROM is not populated */
25afe55d
LV		 605 if (is_dra72x())
606 bname = "DRA72x EVM";
607 else
608 bname = "DRA74x EVM";
609 }
610
611 if (bname)
612 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
613 "Board: %s REV %s\n", bname, board_ti_get_rev());
614}
615#endif /* CONFIG_SPL_BUILD */
616
1428d832
K		 617void vcores_init(void)
618{
619 if (board_is_dra74x_evm()) {
620 *omap_vcores = &dra752_volts;
621 } else if (board_is_dra72x_evm()) {
622 *omap_vcores = &dra722_volts;
f56e6350
K		 623 } else if (board_is_dra71x_evm()) {
624 *omap_vcores = &dra718_volts;
1428d832
K		 625 } else {
626 /* If EEPROM is not populated */
627 if (is_dra72x())
628 *omap_vcores = &dra722_volts;
629 else
630 *omap_vcores = &dra752_volts;
631 }
632}
633
3ef56e61 634void set_muxconf_regs(void)
687054a7
LV		 635{
636 do_set_mux32((*ctrl)->control_padconf_core_base,
706dd348 637 early_padconf, ARRAY_SIZE(early_padconf));
687054a7
LV		 638}
639
706dd348
LV		 640#ifdef CONFIG_IODELAY_RECALIBRATION
641void recalibrate_iodelay(void)
642{
8cac1471 643 struct pad_conf_entry const *pads, *delta_pads = NULL;
03589234 644 struct iodelay_cfg_entry const *iodelay;
8cac1471
NM		 645 int npads, niodelays, delta_npads = 0;
646 int ret;
03589234
NM		 647
648 switch (omap_revision()) {
649 case DRA722_ES1_0:
8cac1471
NM		 650 case DRA722_ES2_0:
651 pads = dra72x_core_padconf_array_common;
652 npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
4d748048
LV		 653 if (board_is_dra71x_evm()) {
654 pads = dra71x_core_padconf_array;
655 npads = ARRAY_SIZE(dra71x_core_padconf_array);
656 iodelay = dra71_iodelay_cfg_array;
657 niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
658 } else if (board_is_dra72x_revc_or_later()) {
8cac1471
NM		 659 delta_pads = dra72x_rgmii_padconf_array_revc;
660 delta_npads =
661 ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
662 iodelay = dra72_iodelay_cfg_array_revc;
663 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
664 } else {
665 delta_pads = dra72x_rgmii_padconf_array_revb;
666 delta_npads =
667 ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
668 iodelay = dra72_iodelay_cfg_array_revb;
669 niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
670 }
03589234
NM		 671 break;
672 case DRA752_ES1_0:
673 case DRA752_ES1_1:
674 pads = dra74x_core_padconf_array;
675 npads = ARRAY_SIZE(dra74x_core_padconf_array);
676 iodelay = dra742_es1_1_iodelay_cfg_array;
677 niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
678 break;
679 default:
680 case DRA752_ES2_0:
681 pads = dra74x_core_padconf_array;
682 npads = ARRAY_SIZE(dra74x_core_padconf_array);
683 iodelay = dra742_es2_0_iodelay_cfg_array;
684 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
76cff2b1
NM		 685 /* Setup port1 and port2 for rgmii with 'no-id' mode */
686 clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
687 RGMII1_ID_MODE_N_MASK);
03589234 688 break;
27d170af 689 }
8cac1471
NM		 690 /* Setup I/O isolation */
691 ret = __recalibrate_iodelay_start();
692 if (ret)
693 goto err;
694
695 /* Do the muxing here */
696 do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
697
698 /* Now do the weird minor deltas that should be safe */
699 if (delta_npads)
700 do_set_mux32((*ctrl)->control_padconf_core_base,
701 delta_pads, delta_npads);
702
703 /* Setup IOdelay configuration */
704 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
705err:
706 /* Closeup.. remove isolation */
707 __recalibrate_iodelay_end(ret);
706dd348
LV		 708}
709#endif
710
4aa2ba3a 711#if defined(CONFIG_MMC)
687054a7
LV		 712int board_mmc_init(bd_t *bis)
713{
714 omap_mmc_init(0, 0, 0, -1, -1);
715 omap_mmc_init(1, 0, 0, -1, -1);
716 return 0;
717}
91d3e906
LV		 718
719void board_mmc_poweron_ldo(uint voltage)
720{
721 if (board_is_dra71x_evm()) {
722 if (voltage == LDO_VOLT_3V0)
723 voltage = 0x19;
724 else if (voltage == LDO_VOLT_1V8)
725 voltage = 0xa;
726 lp873x_mmc1_poweron_ldo(voltage);
727 } else {
db4fce8f 728 palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage);
91d3e906
LV		 729 }
730}
687054a7 731#endif
b1e26e3b 732
a17188c1
KVA		 733#ifdef CONFIG_USB_DWC3
734static struct dwc3_device usb_otg_ss1 = {
735 .maximum_speed = USB_SPEED_SUPER,
736 .base = DRA7_USB_OTG_SS1_BASE,
737 .tx_fifo_resize = false,
738 .index = 0,
739};
740
741static struct dwc3_omap_device usb_otg_ss1_glue = {
742 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
743 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
a17188c1
KVA		 744 .index = 0,
745};
746
747static struct ti_usb_phy_device usb_phy1_device = {
748 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
749 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
750 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
751 .index = 0,
752};
753
754static struct dwc3_device usb_otg_ss2 = {
755 .maximum_speed = USB_SPEED_SUPER,
756 .base = DRA7_USB_OTG_SS2_BASE,
757 .tx_fifo_resize = false,
758 .index = 1,
759};
760
761static struct dwc3_omap_device usb_otg_ss2_glue = {
762 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
763 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
a17188c1
KVA		 764 .index = 1,
765};
766
767static struct ti_usb_phy_device usb_phy2_device = {
768 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
769 .index = 1,
770};
771
1a9a5f7a 772int omap_xhci_board_usb_init(int index, enum usb_init_type init)
a17188c1 773{
6f1af1e3 774 enable_usb_clocks(index);
a17188c1
KVA		 775 switch (index) {
776 case 0:
777 if (init == USB_INIT_DEVICE) {
778 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
779 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
780 } else {
781 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
782 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
783 }
784
785 ti_usb_phy_uboot_init(&usb_phy1_device);
786 dwc3_omap_uboot_init(&usb_otg_ss1_glue);
787 dwc3_uboot_init(&usb_otg_ss1);
788 break;
789 case 1:
790 if (init == USB_INIT_DEVICE) {
791 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
792 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
793 } else {
794 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
795 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
796 }
797
798 ti_usb_phy_uboot_init(&usb_phy2_device);
799 dwc3_omap_uboot_init(&usb_otg_ss2_glue);
800 dwc3_uboot_init(&usb_otg_ss2);
801 break;
802 default:
803 printf("Invalid Controller Index\n");
804 }
805
806 return 0;
807}
808
1a9a5f7a 809int omap_xhci_board_usb_cleanup(int index, enum usb_init_type init)
a17188c1
KVA		 810{
811 switch (index) {
812 case 0:
813 case 1:
814 ti_usb_phy_uboot_exit(index);
815 dwc3_uboot_exit(index);
816 dwc3_omap_uboot_exit(index);
817 break;
818 default:
819 printf("Invalid Controller Index\n");
820 }
6f1af1e3 821 disable_usb_clocks(index);
a17188c1
KVA		 822 return 0;
823}
824
2d48aa69 825int usb_gadget_handle_interrupts(int index)
a17188c1
KVA		 826{
827 u32 status;
828
2d48aa69 829 status = dwc3_omap_uboot_interrupt_status(index);
a17188c1 830 if (status)
2d48aa69 831 dwc3_uboot_handle_interrupt(index);
a17188c1
KVA		 832
833 return 0;
834}
835#endif
836
79b079f3
TR		 837#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
838int spl_start_uboot(void)
839{
840 /* break into full u-boot on 'c' */
841 if (serial_tstc() && serial_getc() == 'c')
842 return 1;
843
844#ifdef CONFIG_SPL_ENV_SUPPORT
845 env_init();
310fb14b 846 env_load();
bfebc8c9 847 if (env_get_yesno("boot_os") != 1)
79b079f3
TR		 848 return 1;
849#endif
850
851 return 0;
852}
853#endif
854
b1e26e3b 855#ifdef CONFIG_DRIVER_TI_CPSW
4c8014b9
M		 856extern u32 *const omap_si_rev;
857
b1e26e3b
M		 858static void cpsw_control(int enabled)
859{
860 /* VTP can be added here */
861
862 return;
863}
864
865static struct cpsw_slave_data cpsw_slaves[] = {
866 {
867 .slave_reg_ofs = 0x208,
868 .sliver_reg_ofs = 0xd80,
9c653aad 869 .phy_addr = 2,
b1e26e3b
M		 870 },
871 {
872 .slave_reg_ofs = 0x308,
873 .sliver_reg_ofs = 0xdc0,
9c653aad 874 .phy_addr = 3,
b1e26e3b
M		 875 },
876};
877
878static struct cpsw_platform_data cpsw_data = {
879 .mdio_base = CPSW_MDIO_BASE,
880 .cpsw_base = CPSW_BASE,
881 .mdio_div = 0xff,
882 .channels = 8,
883 .cpdma_reg_ofs = 0x800,
4c8014b9 884 .slaves = 2,
b1e26e3b
M		 885 .slave_data = cpsw_slaves,
886 .ale_reg_ofs = 0xd00,
887 .ale_entries = 1024,
888 .host_port_reg_ofs = 0x108,
889 .hw_stats_reg_ofs = 0x900,
890 .bd_ram_ofs = 0x2000,
891 .mac_control = (1 << 5),
892 .control = cpsw_control,
893 .host_port_num = 0,
894 .version = CPSW_CTRL_VERSION_2,
895};
896
897int board_eth_init(bd_t *bis)
898{
899 int ret;
900 uint8_t mac_addr[6];
901 uint32_t mac_hi, mac_lo;
902 uint32_t ctrl_val;
b1e26e3b
M		 903
904 /* try reading mac address from efuse */
905 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
906 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
e0a1d598 907 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
b1e26e3b 908 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
e0a1d598
M		 909 mac_addr[2] = mac_hi & 0xFF;
910 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
b1e26e3b 911 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
e0a1d598 912 mac_addr[5] = mac_lo & 0xFF;
b1e26e3b 913
00caae6d 914 if (!env_get("ethaddr")) {
b1e26e3b
M		 915 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
916
0adb5b76 917 if (is_valid_ethaddr(mac_addr))
fd1e959e 918 eth_env_set_enetaddr("ethaddr", mac_addr);
b1e26e3b 919 }
8feb37b9
M		 920
921 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
922 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
923 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
924 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
925 mac_addr[2] = mac_hi & 0xFF;
926 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
927 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
928 mac_addr[5] = mac_lo & 0xFF;
929
00caae6d 930 if (!env_get("eth1addr")) {
0adb5b76 931 if (is_valid_ethaddr(mac_addr))
fd1e959e 932 eth_env_set_enetaddr("eth1addr", mac_addr);
8feb37b9
M		 933 }
934
b1e26e3b
M		 935 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
936 ctrl_val |= 0x22;
937 writel(ctrl_val, (*ctrl)->control_core_control_io1);
938
4c8014b9
M		 939 if (*omap_si_rev == DRA722_ES1_0)
940 cpsw_data.active_slave = 1;
941
39fbac91
DM		 942 if (board_is_dra72x_revc_or_later()) {
943 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
944 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
945 }
946
b1e26e3b
M		 947 ret = cpsw_register(&cpsw_data);
948 if (ret < 0)
949 printf("Error %d registering CPSW switch\n", ret);
950
951 return ret;
952}
953#endif
7b922523
LV		 954
955#ifdef CONFIG_BOARD_EARLY_INIT_F
956/* VTT regulator enable */
957static inline void vtt_regulator_enable(void)
958{
959 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
960 return;
961
962 /* Do not enable VTT for DRA722 */
6b1c14bb 963 if (is_dra72x())
7b922523
LV		 964 return;
965
966 /*
967 * EVM Rev G and later use gpio7_11 for DDR3 termination.
968 * This is safe enough to do on older revs.
969 */
970 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
971 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
972}
973
974int board_early_init_f(void)
975{
976 vtt_regulator_enable();
977 return 0;
978}
979#endif
62a09f05
DA		 980
981#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
982int ft_board_setup(void *blob, bd_t *bd)
983{
984 ft_cpu_setup(blob, bd);
985
986 return 0;
987}
988#endif
09da87da
LV		 989
990#ifdef CONFIG_SPL_LOAD_FIT
991int board_fit_config_name_match(const char *name)
992{
e8131386 993 if (is_dra72x()) {
40de70fb
LV		 994 if (board_is_dra71x_evm()) {
995 if (!strcmp(name, "dra71-evm"))
996 return 0;
997 }else if(board_is_dra72x_revc_or_later()) {
e8131386
M		 998 if (!strcmp(name, "dra72-evm-revc"))
999 return 0;
1000 } else if (!strcmp(name, "dra72-evm")) {
1001 return 0;
1002 }
1003 } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
09da87da 1004 return 0;
e8131386
M		 1005 }
1006
1007 return -1;
09da87da
LV		 1008}
1009#endif
17c29873
AD		 1010
1011#ifdef CONFIG_TI_SECURE_DEVICE
1012void board_fit_image_post_process(void **p_image, size_t *p_size)
1013{
1014 secure_boot_verify_image(p_image, p_size);
1015}
0fcc5207
AD		 1016
1017void board_tee_image_process(ulong tee_image, size_t tee_size)
1018{
1019 secure_tee_install((u32)tee_image);
1020}
1021
1022U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
17c29873 1023#endif
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