[people/ms/u-boot.git] / board / tqc / tqm85xx / tlb.c

/*
 * Copyright 2008 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/mmu.h>

struct fsl_e_tlb_entry tlb_table[] = {
	/* TLB 0 - for temp stack in cache */
	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
		       0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
		       0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
		       0, 0, BOOKE_PAGESZ_4K, 0),
	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
		       0, 0, BOOKE_PAGESZ_4K, 0),

#ifndef CONFIG_TQM_BIGFLASH
	/*
	 * TLB 0, 1:	128M	Non-cacheable, guarded
	 * 0xf8000000	128M	FLASH
	 * Out of reset this entry is only 4K.
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 1, BOOKE_PAGESZ_64M, 1),
	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000,
		       CONFIG_SYS_FLASH_BASE + 0x4000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 0, BOOKE_PAGESZ_64M, 1),

	/*
	 * TLB 2:	256M	Non-cacheable, guarded
	 * 0x80000000	256M	PCI1 MEM First half
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 2, BOOKE_PAGESZ_256M, 1),

	/*
	 * TLB 3:	256M	Non-cacheable, guarded
	 * 0x90000000	256M	PCI1 MEM Second half
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
		       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 3, BOOKE_PAGESZ_256M, 1),

#ifdef CONFIG_PCIE1
	/*
	 * TLB 4:	256M	Non-cacheable, guarded
	 * 0xc0000000	256M	PCI express MEM First half
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 4, BOOKE_PAGESZ_256M, 1),

	/*
	 * TLB 5:	256M	Non-cacheable, guarded
	 * 0xd0000000	256M	PCI express MEM Second half
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
		       CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 5, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
	/*
	 * TLB 4:	256M	Non-cacheable, guarded
	 * 0xc0000000	256M	Rapid IO MEM First half
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 4, BOOKE_PAGESZ_256M, 1),

	/*
	 * TLB 5:	256M	Non-cacheable, guarded
	 * 0xd0000000	256M	Rapid IO MEM Second half
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
		       CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 5, BOOKE_PAGESZ_256M, 1),
#endif /* CONFIG_PCIE */

	/*
	 * TLB 6:	 64M	Non-cacheable, guarded
	 * 0xe0000000	  1M	CCSRBAR
	 * 0xe2000000	 16M	PCI1 IO
	 * 0xe3000000	 16M	CAN and NAND Flash
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 6, BOOKE_PAGESZ_64M, 1),

	/*
	 * TLB 7+8:	512M	 DDR, cache disabled (needed for memory test)
	 * 0x00000000	512M	 DDR System memory
	 * Without SPD EEPROM configured DDR, this must be setup manually.
	 * Make sure the TLB count at the top of this table is correct.
	 * Likely it needs to be increased by two for these entries.
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 7, BOOKE_PAGESZ_256M, 1),

	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
		       CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 8, BOOKE_PAGESZ_256M, 1),

#ifdef CONFIG_PCIE1
	/*
	 * TLB 9:	 16M	Non-cacheable, guarded
	 * 0xef000000	 16M	PCI express IO
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 9, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */

#else /* CONFIG_TQM_BIGFLASH */

	/*
	 * TLB 0,1,2,3:	  1G	Non-cacheable, guarded
	 * 0xc0000000	  1G	FLASH
	 * Out of reset this entry is only 4K.
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 3, BOOKE_PAGESZ_256M, 1),
	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000,
		       CONFIG_SYS_FLASH_BASE + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 2, BOOKE_PAGESZ_256M, 1),
	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000,
		       CONFIG_SYS_FLASH_BASE + 0x20000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 1, BOOKE_PAGESZ_256M, 1),
	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000,
		       CONFIG_SYS_FLASH_BASE + 0x30000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 0, BOOKE_PAGESZ_256M, 1),

	/*
	 * TLB 4:	256M	Non-cacheable, guarded
	 * 0x80000000	256M	PCI1 MEM First half
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 4, BOOKE_PAGESZ_256M, 1),

	/*
	 * TLB 5:	256M	Non-cacheable, guarded
	 * 0x90000000	256M	PCI1 MEM Second half
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
		       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 5, BOOKE_PAGESZ_256M, 1),

#ifdef CONFIG_PCIE1
	/*
	 * TLB 6:	256M	Non-cacheable, guarded
	 * 0xc0000000	256M	PCI express MEM First half
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 6, BOOKE_PAGESZ_256M, 1),
#else /* !CONFIG_PCIE */
	/*
	 * TLB 6:	256M	Non-cacheable, guarded
	 * 0xb0000000	256M	Rapid IO MEM First half
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 6, BOOKE_PAGESZ_256M, 1),

#endif /* CONFIG_PCIE */

	/*
	 * TLB 7:	 64M	Non-cacheable, guarded
	 * 0xa0000000	  1M	CCSRBAR
	 * 0xa2000000	 16M	PCI1 IO
	 * 0xa3000000	 16M	CAN and NAND Flash
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 7, BOOKE_PAGESZ_64M, 1),

	/*
	 * TLB 8+9:	512M	 DDR, cache disabled (needed for memory test)
	 * 0x00000000	512M	 DDR System memory
	 * Without SPD EEPROM configured DDR, this must be setup manually.
	 * Make sure the TLB count at the top of this table is correct.
	 * Likely it needs to be increased by two for these entries.
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 8, BOOKE_PAGESZ_256M, 1),

	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
		       CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 9, BOOKE_PAGESZ_256M, 1),

#ifdef CONFIG_PCIE1
	/*
	 * TLB 10:	 16M	Non-cacheable, guarded
	 * 0xaf000000	 16M	PCI express IO
	 */
	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
		       0, 10, BOOKE_PAGESZ_16M, 1),
#endif /* CONFIG_PCIE */

#endif /* CONFIG_TQM_BIGFLASH */
};

int num_tlb_entries = ARRAY_SIZE (tlb_table);
Commit	Line	Data
3b558e26 KG	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc.
	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/mmu.h>
	28
	29	struct fsl_e_tlb_entry tlb_table[] = {
	30	/* TLB 0 - for temp stack in cache */
6d0f6bcf	31	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
b99ba167 WG	32	MAS3_SX \| MAS3_SW \| MAS3_SR, 0,
b99ba167 WG	33	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf JCPV	34	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
6d0f6bcf JCPV	35	CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
b99ba167 WG	36	MAS3_SX \| MAS3_SW \| MAS3_SR, 0,
b99ba167 WG	37	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf JCPV	38	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
6d0f6bcf JCPV	39	CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
b99ba167 WG	40	MAS3_SX \| MAS3_SW \| MAS3_SR, 0,
b99ba167 WG	41	0, 0, BOOKE_PAGESZ_4K, 0),
6d0f6bcf JCPV	42	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
6d0f6bcf JCPV	43	CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
b99ba167 WG	44	MAS3_SX \| MAS3_SW \| MAS3_SR, 0,
b99ba167 WG	45	0, 0, BOOKE_PAGESZ_4K, 0),
3b558e26	46
e8cc3f04	47	#ifndef CONFIG_TQM_BIGFLASH
3b558e26 KG	48	/*
	49	* TLB 0, 1: 128M Non-cacheable, guarded
	50	* 0xf8000000 128M FLASH
	51	* Out of reset this entry is only 4K.
	52	*/
6d0f6bcf	53	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
b99ba167 WG	54	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
b99ba167 WG	55	0, 1, BOOKE_PAGESZ_64M, 1),
6d0f6bcf JCPV	56	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000,
6d0f6bcf JCPV	57	CONFIG_SYS_FLASH_BASE + 0x4000000,
b99ba167 WG	58	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
b99ba167 WG	59	0, 0, BOOKE_PAGESZ_64M, 1),
3b558e26 KG	60
	61	/*
	62	* TLB 2: 256M Non-cacheable, guarded
	63	* 0x80000000 256M PCI1 MEM First half
	64	*/
6d0f6bcf	65	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
b99ba167 WG	66	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
b99ba167 WG	67	0, 2, BOOKE_PAGESZ_256M, 1),
3b558e26 KG	68
	69	/*
	70	* TLB 3: 256M Non-cacheable, guarded
	71	* 0x90000000 256M PCI1 MEM Second half
	72	*/
6d0f6bcf JCPV	73	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
6d0f6bcf JCPV	74	CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
b99ba167 WG	75	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
b99ba167 WG	76	0, 3, BOOKE_PAGESZ_256M, 1),
3b558e26	77
b9e8078b WG	78	#ifdef CONFIG_PCIE1
	79	/*
	80	* TLB 4: 256M Non-cacheable, guarded
	81	* 0xc0000000 256M PCI express MEM First half
	82	*/
6d0f6bcf	83	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
b9e8078b WG	84	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	85	0, 4, BOOKE_PAGESZ_256M, 1),
	86
	87	/*
	88	* TLB 5: 256M Non-cacheable, guarded
	89	* 0xd0000000 256M PCI express MEM Second half
	90	*/
6d0f6bcf JCPV	91	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
6d0f6bcf JCPV	92	CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
b9e8078b WG	93	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	94	0, 5, BOOKE_PAGESZ_256M, 1),
	95	#else /* !CONFIG_PCIE */
3b558e26 KG	96	/*
	97	* TLB 4: 256M Non-cacheable, guarded
	98	* 0xc0000000 256M Rapid IO MEM First half
	99	*/
6d0f6bcf	100	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
b99ba167 WG	101	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
b99ba167 WG	102	0, 4, BOOKE_PAGESZ_256M, 1),
3b558e26 KG	103
	104	/*
	105	* TLB 5: 256M Non-cacheable, guarded
	106	* 0xd0000000 256M Rapid IO MEM Second half
	107	*/
6d0f6bcf JCPV	108	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
6d0f6bcf JCPV	109	CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
b99ba167 WG	110	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
b99ba167 WG	111	0, 5, BOOKE_PAGESZ_256M, 1),
b9e8078b	112	#endif /* CONFIG_PCIE */
3b558e26 KG	113
3b558e26 KG	114	/*
b99ba167 WG	115	* TLB 6: 64M Non-cacheable, guarded
	116	* 0xe0000000 1M CCSRBAR
	117	* 0xe2000000 16M PCI1 IO
1c2deff2	118	* 0xe3000000 16M CAN and NAND Flash
3b558e26	119	*/
6d0f6bcf	120	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
b99ba167 WG	121	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
b99ba167 WG	122	0, 6, BOOKE_PAGESZ_64M, 1),
3b558e26 KG	123
3b558e26 KG	124	/*
b99ba167 WG	125	* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
b99ba167 WG	126	* 0x00000000 512M DDR System memory
3b558e26 KG	127	* Without SPD EEPROM configured DDR, this must be setup manually.
	128	* Make sure the TLB count at the top of this table is correct.
	129	* Likely it needs to be increased by two for these entries.
	130	*/
6d0f6bcf	131	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
b99ba167 WG	132	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
b99ba167 WG	133	0, 7, BOOKE_PAGESZ_256M, 1),
3b558e26	134
6d0f6bcf JCPV	135	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
6d0f6bcf JCPV	136	CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
b99ba167 WG	137	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
b99ba167 WG	138	0, 8, BOOKE_PAGESZ_256M, 1),
b9e8078b WG	139
	140	#ifdef CONFIG_PCIE1
	141	/*
	142	* TLB 9: 16M Non-cacheable, guarded
	143	* 0xef000000 16M PCI express IO
	144	*/
6d0f6bcf	145	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
b9e8078b WG	146	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	147	0, 9, BOOKE_PAGESZ_16M, 1),
	148	#endif /* CONFIG_PCIE */
	149
e8cc3f04 WG	150	#else /* CONFIG_TQM_BIGFLASH */
	151
	152	/*
	153	* TLB 0,1,2,3: 1G Non-cacheable, guarded
	154	* 0xc0000000 1G FLASH
	155	* Out of reset this entry is only 4K.
	156	*/
6d0f6bcf	157	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
e8cc3f04 WG	158	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
e8cc3f04 WG	159	0, 3, BOOKE_PAGESZ_256M, 1),
6d0f6bcf JCPV	160	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000,
6d0f6bcf JCPV	161	CONFIG_SYS_FLASH_BASE + 0x10000000,
e8cc3f04 WG	162	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
e8cc3f04 WG	163	0, 2, BOOKE_PAGESZ_256M, 1),
6d0f6bcf JCPV	164	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000,
6d0f6bcf JCPV	165	CONFIG_SYS_FLASH_BASE + 0x20000000,
e8cc3f04 WG	166	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
e8cc3f04 WG	167	0, 1, BOOKE_PAGESZ_256M, 1),
6d0f6bcf JCPV	168	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000,
6d0f6bcf JCPV	169	CONFIG_SYS_FLASH_BASE + 0x30000000,
e8cc3f04 WG	170	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	171	0, 0, BOOKE_PAGESZ_256M, 1),
	172
	173	/*
	174	* TLB 4: 256M Non-cacheable, guarded
	175	* 0x80000000 256M PCI1 MEM First half
	176	*/
6d0f6bcf	177	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
e8cc3f04 WG	178	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	179	0, 4, BOOKE_PAGESZ_256M, 1),
	180
	181	/*
	182	* TLB 5: 256M Non-cacheable, guarded
	183	* 0x90000000 256M PCI1 MEM Second half
	184	*/
6d0f6bcf JCPV	185	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
6d0f6bcf JCPV	186	CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
e8cc3f04 WG	187	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	188	0, 5, BOOKE_PAGESZ_256M, 1),
	189
	190	#ifdef CONFIG_PCIE1
	191	/*
	192	* TLB 6: 256M Non-cacheable, guarded
	193	* 0xc0000000 256M PCI express MEM First half
	194	*/
6d0f6bcf	195	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
e8cc3f04 WG	196	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	197	0, 6, BOOKE_PAGESZ_256M, 1),
	198	#else /* !CONFIG_PCIE */
	199	/*
	200	* TLB 6: 256M Non-cacheable, guarded
	201	* 0xb0000000 256M Rapid IO MEM First half
	202	*/
6d0f6bcf	203	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
e8cc3f04 WG	204	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	205	0, 6, BOOKE_PAGESZ_256M, 1),
	206
	207	#endif /* CONFIG_PCIE */
	208
	209	/*
	210	* TLB 7: 64M Non-cacheable, guarded
	211	* 0xa0000000 1M CCSRBAR
	212	* 0xa2000000 16M PCI1 IO
	213	* 0xa3000000 16M CAN and NAND Flash
	214	*/
6d0f6bcf	215	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
e8cc3f04 WG	216	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	217	0, 7, BOOKE_PAGESZ_64M, 1),
	218
	219	/*
	220	* TLB 8+9: 512M DDR, cache disabled (needed for memory test)
	221	* 0x00000000 512M DDR System memory
	222	* Without SPD EEPROM configured DDR, this must be setup manually.
	223	* Make sure the TLB count at the top of this table is correct.
	224	* Likely it needs to be increased by two for these entries.
	225	*/
6d0f6bcf	226	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
e8cc3f04 WG	227	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	228	0, 8, BOOKE_PAGESZ_256M, 1),
	229
6d0f6bcf JCPV	230	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
6d0f6bcf JCPV	231	CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
e8cc3f04 WG	232	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	233	0, 9, BOOKE_PAGESZ_256M, 1),
	234
	235	#ifdef CONFIG_PCIE1
	236	/*
	237	* TLB 10: 16M Non-cacheable, guarded
	238	* 0xaf000000 16M PCI express IO
	239	*/
6d0f6bcf	240	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
e8cc3f04 WG	241	MAS3_SX \| MAS3_SW \| MAS3_SR, MAS2_I \| MAS2_G,
	242	0, 10, BOOKE_PAGESZ_16M, 1),
	243	#endif /* CONFIG_PCIE */
	244
	245	#endif /* CONFIG_TQM_BIGFLASH */
3b558e26 KG	246	};
3b558e26 KG	247
b99ba167	248	int num_tlb_entries = ARRAY_SIZE (tlb_table);