[people/ms/u-boot.git] / board / xilinx / zynq / board.c

/*
 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fdtdec.h>
#include <fpga.h>
#include <mmc.h>
#include <zynqpl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/ps7_init_gpl.h>

DECLARE_GLOBAL_DATA_PTR;

#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
static xilinx_desc fpga;

/* It can be done differently */
static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif

int board_init(void)
{
#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
	u32 idcode;

	idcode = zynq_slcr_get_idcode();

	switch (idcode) {
	case XILINX_ZYNQ_7007S:
		fpga = fpga007s;
		break;
	case XILINX_ZYNQ_7010:
		fpga = fpga010;
		break;
	case XILINX_ZYNQ_7012S:
		fpga = fpga012s;
		break;
	case XILINX_ZYNQ_7014S:
		fpga = fpga014s;
		break;
	case XILINX_ZYNQ_7015:
		fpga = fpga015;
		break;
	case XILINX_ZYNQ_7020:
		fpga = fpga020;
		break;
	case XILINX_ZYNQ_7030:
		fpga = fpga030;
		break;
	case XILINX_ZYNQ_7035:
		fpga = fpga035;
		break;
	case XILINX_ZYNQ_7045:
		fpga = fpga045;
		break;
	case XILINX_ZYNQ_7100:
		fpga = fpga100;
		break;
	}
#endif

#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
    (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
	fpga_init();
	fpga_add(fpga_xilinx, &fpga);
#endif

	return 0;
}

int board_late_init(void)
{
	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
	case ZYNQ_BM_QSPI:
		env_set("modeboot", "qspiboot");
		break;
	case ZYNQ_BM_NAND:
		env_set("modeboot", "nandboot");
		break;
	case ZYNQ_BM_NOR:
		env_set("modeboot", "norboot");
		break;
	case ZYNQ_BM_SD:
		env_set("modeboot", "sdboot");
		break;
	case ZYNQ_BM_JTAG:
		env_set("modeboot", "jtagboot");
		break;
	default:
		env_set("modeboot", "");
		break;
	}

	return 0;
}

#ifdef CONFIG_DISPLAY_BOARDINFO
int checkboard(void)
{
	u32 version = zynq_get_silicon_version();

	version <<= 1;
	if (version > (PCW_SILICON_VERSION_3 << 1))
		version += 1;

	puts("Board: Xilinx Zynq\n");
	printf("Silicon: v%d.%d\n", version >> 1, version & 1);

	return 0;
}
#endif

int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
{
#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
    defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
			CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
			ethaddr, 6))
		printf("I2C EEPROM MAC address read failed\n");
#endif

	return 0;
}

#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
int dram_init_banksize(void)
{
	return fdtdec_setup_memory_banksize();
}

int dram_init(void)
{
	if (fdtdec_setup_memory_size() != 0)
		return -EINVAL;

	zynq_ddrc_init();

	return 0;
}
#else
int dram_init(void)
{
	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;

	zynq_ddrc_init();

	return 0;
}
#endif
Commit	Line	Data
f22651cf MS	1	/*
	2	* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
f22651cf MS	5	*/
	6
	7	#include <common.h>
9e0e37ac	8	#include <fdtdec.h>
5b73caff MS	9	#include <fpga.h>
5b73caff MS	10	#include <mmc.h>
d5dae85f	11	#include <zynqpl.h>
7193653e MS	12	#include <asm/arch/hardware.h>
7193653e MS	13	#include <asm/arch/sys_proto.h>
29fb5703	14	#include <asm/arch/ps7_init_gpl.h>
f22651cf MS	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
0b680206 MS	18	#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) \|\| \
0b680206 MS	19	(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
5b73caff	20	static xilinx_desc fpga;
d5dae85f MS	21
d5dae85f MS	22	/* It can be done differently */
05c59d0b	23	static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
5b73caff	24	static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
05c59d0b MS	25	static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
05c59d0b MS	26	static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
5b73caff MS	27	static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
	28	static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
	29	static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
b9103809	30	static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
5b73caff MS	31	static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
5b73caff MS	32	static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
d5dae85f MS	33	#endif
d5dae85f MS	34
f22651cf MS	35	int board_init(void)
f22651cf MS	36	{
0b680206 MS	37	#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) \|\| \
0b680206 MS	38	(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
d5dae85f MS	39	u32 idcode;
	40
	41	idcode = zynq_slcr_get_idcode();
	42
	43	switch (idcode) {
05c59d0b MS	44	case XILINX_ZYNQ_7007S:
	45	fpga = fpga007s;
	46	break;
d5dae85f MS	47	case XILINX_ZYNQ_7010:
	48	fpga = fpga010;
	49	break;
05c59d0b MS	50	case XILINX_ZYNQ_7012S:
	51	fpga = fpga012s;
	52	break;
	53	case XILINX_ZYNQ_7014S:
	54	fpga = fpga014s;
	55	break;
31993d6a MS	56	case XILINX_ZYNQ_7015:
	57	fpga = fpga015;
	58	break;
d5dae85f MS	59	case XILINX_ZYNQ_7020:
	60	fpga = fpga020;
	61	break;
	62	case XILINX_ZYNQ_7030:
	63	fpga = fpga030;
	64	break;
b9103809 SDPP	65	case XILINX_ZYNQ_7035:
	66	fpga = fpga035;
	67	break;
d5dae85f MS	68	case XILINX_ZYNQ_7045:
	69	fpga = fpga045;
	70	break;
fd2b10b6 MS	71	case XILINX_ZYNQ_7100:
	72	fpga = fpga100;
	73	break;
d5dae85f MS	74	}
	75	#endif
	76
0b680206 MS	77	#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) \|\| \
0b680206 MS	78	(defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
d5dae85f MS	79	fpga_init();
	80	fpga_add(fpga_xilinx, &fpga);
	81	#endif
	82
f22651cf MS	83	return 0;
	84	}
	85
b3de9249 JT	86	int board_late_init(void)
	87	{
	88	switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
085b2b82	89	case ZYNQ_BM_QSPI:
382bee57	90	env_set("modeboot", "qspiboot");
085b2b82 MS	91	break;
085b2b82 MS	92	case ZYNQ_BM_NAND:
382bee57	93	env_set("modeboot", "nandboot");
085b2b82	94	break;
b3de9249	95	case ZYNQ_BM_NOR:
382bee57	96	env_set("modeboot", "norboot");
b3de9249 JT	97	break;
b3de9249 JT	98	case ZYNQ_BM_SD:
382bee57	99	env_set("modeboot", "sdboot");
b3de9249 JT	100	break;
b3de9249 JT	101	case ZYNQ_BM_JTAG:
382bee57	102	env_set("modeboot", "jtagboot");
b3de9249 JT	103	break;
b3de9249 JT	104	default:
382bee57	105	env_set("modeboot", "");
b3de9249 JT	106	break;
	107	}
	108
	109	return 0;
	110	}
f22651cf	111
5a82d53c MS	112	#ifdef CONFIG_DISPLAY_BOARDINFO
	113	int checkboard(void)
	114	{
29fb5703 MS	115	u32 version = zynq_get_silicon_version();
	116
	117	version <<= 1;
	118	if (version > (PCW_SILICON_VERSION_3 << 1))
	119	version += 1;
	120
5af08556	121	puts("Board: Xilinx Zynq\n");
29fb5703 MS	122	printf("Silicon: v%d.%d\n", version >> 1, version & 1);
29fb5703 MS	123
5a82d53c MS	124	return 0;
	125	}
	126	#endif
	127
a509a1d4 JH	128	int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
	129	{
	130	#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
	131	defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
	132	if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
	133	CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
	134	ethaddr, 6))
	135	printf("I2C EEPROM MAC address read failed\n");
	136	#endif
	137
	138	return 0;
	139	}
	140
758f29d0	141	#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
76b00aca	142	int dram_init_banksize(void)
361a8799	143	{
da3f003b	144	return fdtdec_setup_memory_banksize();
361a8799	145	}
8a5db0ab	146
361a8799 TR	147	int dram_init(void)
361a8799 TR	148	{
de9bf1b5 NR	149	if (fdtdec_setup_memory_size() != 0)
de9bf1b5 NR	150	return -EINVAL;
64b67fb2	151
361a8799	152	zynq_ddrc_init();
64b67fb2	153
361a8799	154	return 0;
758f29d0	155	}
758f29d0 MS	156	#else
	157	int dram_init(void)
	158	{
	159	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
	160
148ba55c MS	161	zynq_ddrc_init();
148ba55c MS	162
f22651cf MS	163	return 0;
f22651cf MS	164	}
758f29d0	165	#endif