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PXA: Fix warning in zipitz2
[people/ms/u-boot.git] / board / zipitz2 / zipitz2.c
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1/*
2 * Copyright (C) 2009
3 * Marek Vasut <marek.vasut@gmail.com>
4 *
5 * Heavily based on pxa255_idp platform
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <command.h>
28#include <serial.h>
29#include <asm/arch/hardware.h>
4438a45f 30#include <asm/arch/pxa.h>
60994b99 31#include <asm/arch/regs-mmc.h>
bc3a4a53 32#include <spi.h>
3ba8bf7c 33#include <asm/io.h>
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34
35DECLARE_GLOBAL_DATA_PTR;
36
37#ifdef CONFIG_CMD_SPI
38void lcd_start(void);
39#else
40inline void lcd_start(void) {};
41#endif
42
43/*
44 * Miscelaneous platform dependent initialisations
45 */
46
47int board_init (void)
48{
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49 /* We have RAM, disable cache */
50 dcache_disable();
51 icache_disable();
bc3a4a53 52
24e84c3d 53 /* arch number of Z2 */
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54 gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
55
56 /* adress of boot parameters */
57 gd->bd->bi_boot_params = 0xa0000100;
58
59 /* Enable LCD */
60 lcd_start();
61
62 return 0;
63}
64
24e84c3d 65struct serial_device *default_serial_console (void)
bc3a4a53 66{
24e84c3d 67 return &serial_stuart_device;
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68}
69
24e84c3d 70int dram_init(void)
bc3a4a53 71{
f68d2a22 72 pxa2xx_dram_init();
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73 gd->ram_size = PHYS_SDRAM_1_SIZE;
74 return 0;
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75}
76
24e84c3d 77void dram_init_banksize(void)
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78{
79 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
80 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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81}
82
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83#ifdef CONFIG_CMD_MMC
84int board_mmc_init(bd_t *bis)
85{
86 pxa_mmc_register(0);
87 return 0;
88}
89#endif
90
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91#ifdef CONFIG_CMD_SPI
92
93struct {
94 unsigned char reg;
95 unsigned short data;
96 unsigned char mdelay;
97} lcd_data[] = {
98 { 0x07, 0x0000, 0 },
99 { 0x13, 0x0000, 10 },
100 { 0x11, 0x3004, 0 },
101 { 0x14, 0x200F, 0 },
102 { 0x10, 0x1a20, 0 },
103 { 0x13, 0x0040, 50 },
104 { 0x13, 0x0060, 0 },
105 { 0x13, 0x0070, 200 },
106 { 0x01, 0x0127, 0 },
107 { 0x02, 0x0700, 0 },
108 { 0x03, 0x1030, 0 },
109 { 0x08, 0x0208, 0 },
110 { 0x0B, 0x0620, 0 },
111 { 0x0C, 0x0110, 0 },
112 { 0x30, 0x0120, 0 },
113 { 0x31, 0x0127, 0 },
114 { 0x32, 0x0000, 0 },
115 { 0x33, 0x0503, 0 },
116 { 0x34, 0x0727, 0 },
117 { 0x35, 0x0124, 0 },
118 { 0x36, 0x0706, 0 },
119 { 0x37, 0x0701, 0 },
120 { 0x38, 0x0F00, 0 },
121 { 0x39, 0x0F00, 0 },
122 { 0x40, 0x0000, 0 },
123 { 0x41, 0x0000, 0 },
124 { 0x42, 0x013f, 0 },
125 { 0x43, 0x0000, 0 },
126 { 0x44, 0x013f, 0 },
127 { 0x45, 0x0000, 0 },
128 { 0x46, 0xef00, 0 },
129 { 0x47, 0x013f, 0 },
130 { 0x48, 0x0000, 0 },
131 { 0x07, 0x0015, 30 },
132 { 0x07, 0x0017, 0 },
133 { 0x20, 0x0000, 0 },
134 { 0x21, 0x0000, 0 },
135 { 0x22, 0x0000, 0 },
136};
137
138void zipitz2_spi_sda(int set)
139{
140 /* GPIO 13 */
141 if (set)
3ba8bf7c 142 writel((1 << 13), GPSR0);
bc3a4a53 143 else
3ba8bf7c 144 writel((1 << 13), GPCR0);
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145}
146
147void zipitz2_spi_scl(int set)
148{
149 /* GPIO 22 */
150 if (set)
3ba8bf7c 151 writel((1 << 22), GPCR0);
bc3a4a53 152 else
3ba8bf7c 153 writel((1 << 22), GPSR0);
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154}
155
156unsigned char zipitz2_spi_read(void)
157{
158 /* GPIO 40 */
3ba8bf7c 159 return !!(readl(GPLR1) & (1 << 8));
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160}
161
162int spi_cs_is_valid(unsigned int bus, unsigned int cs)
163{
164 /* Always valid */
165 return 1;
166}
167
168void spi_cs_activate(struct spi_slave *slave)
169{
170 /* GPIO 88 low */
3ba8bf7c 171 writel((1 << 24), GPCR2);
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172}
173
174void spi_cs_deactivate(struct spi_slave *slave)
175{
176 /* GPIO 88 high */
3ba8bf7c 177 writel((1 << 24), GPSR2);
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178
179}
180
181void lcd_start(void)
182{
183 int i;
184 unsigned char reg[3] = { 0x74, 0x00, 0 };
185 unsigned char data[3] = { 0x76, 0, 0 };
186 unsigned char dummy[3] = { 0, 0, 0 };
187
188 /* PWM2 AF */
3ba8bf7c 189 writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
bc3a4a53 190 /* Enable clock to all PWM */
3ba8bf7c 191 writel(readl(CKEN) | 0x3, CKEN);
bc3a4a53 192 /* Configure PWM2 */
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193 writel(0x4f, PWM_CTRL2);
194 writel(0x2ff, PWM_PWDUTY2);
195 writel(792, PWM_PERVAL2);
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196
197 /* Toggle the reset pin to reset the LCD */
3ba8bf7c 198 writel((1 << 19), GPSR0);
bc3a4a53 199 udelay(100000);
3ba8bf7c 200 writel((1 << 19), GPCR0);
bc3a4a53 201 udelay(20000);
3ba8bf7c 202 writel((1 << 19), GPSR0);
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203 udelay(20000);
204
205 /* Program the LCD init sequence */
206 for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
207 reg[0] = 0x74;
208 reg[1] = 0x0;
209 reg[2] = lcd_data[i].reg;
210 spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
211
212 data[0] = 0x76;
213 data[1] = lcd_data[i].data >> 8;
214 data[2] = lcd_data[i].data & 0xff;
215 spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
216
217 if (lcd_data[i].mdelay)
218 udelay(lcd_data[i].mdelay * 1000);
219 }
220
3ba8bf7c 221 writel((1 << 11), GPSR0);
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222}
223#endif