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9b56f4f0 SH |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Sascha Hauer, Pengutronix | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/arch/mx31-regs.h> | |
26 | ||
27 | #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ | |
28 | ||
29 | /* General purpose timers registers */ | |
1ed7a7f0 GL |
30 | #define GPTCR __REG(TIMER_BASE) /* Control register */ |
31 | #define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ | |
32 | #define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ | |
33 | #define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ | |
9b56f4f0 SH |
34 | |
35 | /* General purpose timers bitfields */ | |
1ed7a7f0 GL |
36 | #define GPTCR_SWR (1 << 15) /* Software reset */ |
37 | #define GPTCR_FRR (1 << 9) /* Freerun / restart */ | |
38 | #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ | |
39 | #define GPTCR_TEN 1 /* Timer enable */ | |
40 | ||
6d0f6bcf | 41 | /* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */ |
1ed7a7f0 GL |
42 | #ifdef CONFIG_MX31_TIMER_HIGH_PRECISION |
43 | /* ~0.4% error - measured with stop-watch on 100s boot-delay */ | |
6d0f6bcf JCPV |
44 | #define TICK_TO_TIME(t) ((t) * CONFIG_SYS_HZ / CONFIG_MX31_CLK32) |
45 | #define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CONFIG_SYS_HZ) | |
1ed7a7f0 GL |
46 | #define US_TO_TICK(t) (((unsigned long long)(t) * CONFIG_MX31_CLK32 + \ |
47 | 999999) / 1000000) | |
48 | #else | |
49 | /* ~2% error */ | |
6d0f6bcf | 50 | #define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ) |
1ed7a7f0 GL |
51 | #define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) |
52 | #define TICK_TO_TIME(t) ((t) / TICK_PER_TIME) | |
53 | #define TIME_TO_TICK(t) ((unsigned long long)(t) * TICK_PER_TIME) | |
54 | #define US_TO_TICK(t) (((t) + US_PER_TICK - 1) / US_PER_TICK) | |
55 | #endif | |
9b56f4f0 | 56 | |
8c4ebec2 ML |
57 | static ulong timestamp; |
58 | static ulong lastinc; | |
59 | ||
9b56f4f0 | 60 | /* nothing really to do with interrupts, just starts up a counter. */ |
1ed7a7f0 | 61 | /* The 32768Hz 32-bit timer overruns in 131072 seconds */ |
9b56f4f0 SH |
62 | int interrupt_init (void) |
63 | { | |
64 | int i; | |
65 | ||
66 | /* setup GP Timer 1 */ | |
67 | GPTCR = GPTCR_SWR; | |
1ed7a7f0 GL |
68 | for (i = 0; i < 100; i++) |
69 | GPTCR = 0; /* We have no udelay by now */ | |
9b56f4f0 | 70 | GPTPR = 0; /* 32Khz */ |
1ed7a7f0 GL |
71 | /* Freerun Mode, PERCLK1 input */ |
72 | GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; | |
9b56f4f0 SH |
73 | |
74 | return 0; | |
75 | } | |
76 | ||
77 | void reset_timer_masked (void) | |
78 | { | |
8c4ebec2 ML |
79 | /* reset time */ |
80 | lastinc = GPTCNT; /* capture current incrementer value time */ | |
81 | timestamp = 0; /* start "advancing" time stamp from 0 */ | |
82 | } | |
83 | ||
84 | void reset_timer(void) | |
85 | { | |
86 | reset_timer_masked(); | |
9b56f4f0 SH |
87 | } |
88 | ||
1ed7a7f0 | 89 | unsigned long long get_ticks (void) |
9b56f4f0 | 90 | { |
8c4ebec2 ML |
91 | ulong now = GPTCNT; /* current tick value */ |
92 | ||
93 | if (now >= lastinc) /* normal mode (non roll) */ | |
94 | /* move stamp forward with absolut diff ticks */ | |
95 | timestamp += (now - lastinc); | |
96 | else /* we have rollover of incrementer */ | |
97 | timestamp += (0xFFFFFFFF - lastinc) + now; | |
98 | lastinc = now; | |
99 | return timestamp; | |
9b56f4f0 SH |
100 | } |
101 | ||
1ed7a7f0 GL |
102 | ulong get_timer_masked (void) |
103 | { | |
104 | /* | |
105 | * get_ticks() returns a long long (64 bit), it wraps in | |
106 | * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ | |
6d0f6bcf | 107 | * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in |
1ed7a7f0 GL |
108 | * 5 * 10^6 days - long enough. |
109 | */ | |
110 | return TICK_TO_TIME(get_ticks()); | |
111 | } | |
112 | ||
9b56f4f0 SH |
113 | ulong get_timer (ulong base) |
114 | { | |
115 | return get_timer_masked () - base; | |
116 | } | |
117 | ||
118 | void set_timer (ulong t) | |
119 | { | |
1ed7a7f0 | 120 | timestamp = TIME_TO_TICK(t); |
9b56f4f0 SH |
121 | } |
122 | ||
123 | /* delay x useconds AND perserve advance timstamp value */ | |
124 | void udelay (unsigned long usec) | |
125 | { | |
1ed7a7f0 GL |
126 | unsigned long long tmp; |
127 | ulong tmo; | |
128 | ||
129 | tmo = US_TO_TICK(usec); | |
130 | tmp = get_ticks() + tmo; /* get current timestamp */ | |
131 | ||
132 | while (get_ticks() < tmp) /* loop till event */ | |
133 | /*NOP*/; | |
9b56f4f0 SH |
134 | } |
135 | ||
136 | void reset_cpu (ulong addr) | |
137 | { | |
138 | __REG16(WDOG_BASE) = 4; | |
139 | } |