[people/ms/u-boot.git] / cpu / arm1176 / cpu.c

/*
 * (C) Copyright 2004 Texas Insturments
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * (C) Copyright 2002
 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * CPU specific code
 */

#include <common.h>
#include <command.h>
#include <s3c6400.h>
#include <asm/system.h>

static void cache_flush (void);

int cpu_init (void)
{
	return 0;
}

int cleanup_before_linux (void)
{
	/*
	 * this function is called just before we call linux
	 * it prepares the processor for linux
	 *
	 * we turn off caches etc ...
	 */

	disable_interrupts ();

	/* turn off I/D-cache */
	icache_disable();
	dcache_disable();
	/* flush I/D-cache */
	cache_flush();

	return 0;
}


/* * reset the cpu by setting up the watchdog timer and let him time out */
void reset_cpu (ulong ignored)
{
	printf("reset... \n\n\n");
	SW_RST_REG = 0x6400;
	/* loop forever and wait for reset to happen */
	while (1) {
		if (serial_tstc()) {
			serial_getc();
			break;
		}
	}
	/*NOTREACHED*/
}

/* flush I/D-cache */
static void cache_flush (void)
{
	/* invalidate both caches and flush btb */
	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
	/* mem barrier to sync things */
	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
}
Commit	Line	Data
9b07773f GL	1	/*
	2	* (C) Copyright 2004 Texas Insturments
	3	*
	4	* (C) Copyright 2002
	5	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	6	* Marius Groeger <mgroeger@sysgo.de>
	7	*
	8	* (C) Copyright 2002
	9	* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
	10	*
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	/*
	31	* CPU specific code
	32	*/
	33
	34	#include <common.h>
	35	#include <command.h>
	36	#include <s3c6400.h>
677e62f4	37	#include <asm/system.h>
9b07773f GL	38
	39	static void cache_flush (void);
	40
9b07773f GL	41	int cpu_init (void)
	42	{
	43	return 0;
	44	}
	45
	46	int cleanup_before_linux (void)
	47	{
	48	/*
	49	* this function is called just before we call linux
	50	* it prepares the processor for linux
	51	*
	52	* we turn off caches etc ...
	53	*/
	54
	55	disable_interrupts ();
	56
	57	/* turn off I/D-cache */
	58	icache_disable();
	59	dcache_disable();
b3acb6cd	60	/* flush I/D-cache */
9b07773f GL	61	cache_flush();
	62
	63	return 0;
	64	}
	65
	66
	67	/* * reset the cpu by setting up the watchdog timer and let him time out */
	68	void reset_cpu (ulong ignored)
	69	{
	70	printf("reset... \n\n\n");
	71	SW_RST_REG = 0x6400;
	72	/* loop forever and wait for reset to happen */
	73	while (1) {
	74	if (serial_tstc()) {
	75	serial_getc();
	76	break;
	77	}
	78	}
	79	/NOTREACHED/
	80	}
	81
9b07773f GL	82	/* flush I/D-cache */
	83	static void cache_flush (void)
	84	{
	85	/* invalidate both caches and flush btb */
	86	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0));
	87	/* mem barrier to sync things */
	88	asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0));
	89	}