[people/ms/u-boot.git] / cpu / mpc85xx / pci.c

/*
 * Copyright 2004 Freescale Semiconductor.
 * Copyright (C) 2003 Motorola Inc.
 * Xianghua Xiao (x.xiao@motorola.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * PCI Configuration space access support for MPC85xx PCI Bridge
 */
#include <common.h>
#include <asm/cpm_85xx.h>
#include <pci.h>

#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)

static struct pci_controller *pci_hose;

void
pci_mpc85xx_init(struct pci_controller *board_hose)
{
	u16 reg16;
	u32 dev;

	volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
#ifdef CONFIG_MPC85XX_PCI2
	volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
#endif
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	struct pci_controller * hose;

	pci_hose = board_hose;

	hose = &pci_hose[0];

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_setup_indirect(hose,
			   (CONFIG_SYS_IMMR+0x8000),
			   (CONFIG_SYS_IMMR+0x8004));

	/*
	 * Hose scan.
	 */
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);

	if (!(gur->pordevsr & PORDEVSR_PCI)) {
		/* PCI-X init */
		if (CONFIG_SYS_CLK_FREQ < 66000000)
			printf("PCI-X will only work at 66 MHz\n");

		reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
			| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
		pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
	}

	pcix->potar1   = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff;
	pcix->potear1  = 0x00000000;
	pcix->powbar1  = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
	pcix->powbear1 = 0x00000000;
	pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
			POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));

	pcix->potar2  = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff;
	pcix->potear2  = 0x00000000;
	pcix->powbar2  = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
	pcix->powbear2 = 0x00000000;
	pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
			POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));

	pcix->pitar1 = 0x00000000;
	pcix->piwbar1 = 0x00000000;
	pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
			PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);

	pcix->powar3 = 0;
	pcix->powar4 = 0;
	pcix->piwar2 = 0;
	pcix->piwar3 = 0;

	pci_set_region(hose->regions + 0,
		       CONFIG_SYS_PCI1_MEM_BASE,
		       CONFIG_SYS_PCI1_MEM_PHYS,
		       CONFIG_SYS_PCI1_MEM_SIZE,
		       PCI_REGION_MEM);

	pci_set_region(hose->regions + 1,
		       CONFIG_SYS_PCI1_IO_BASE,
		       CONFIG_SYS_PCI1_IO_PHYS,
		       CONFIG_SYS_PCI1_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = 2;

	pci_register_hose(hose);

#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
	/*
	 * This is a SW workaround for an apparent HW problem
	 * in the PCI controller on the MPC85555/41 CDS boards.
	 * The first config cycle must be to a valid, known
	 * device on the PCI bus in order to trick the PCI
	 * controller state machine into a known valid state.
	 * Without this, the first config cycle has the chance
	 * of hanging the controller permanently, just leaving
	 * it in a semi-working state, or leaving it working.
	 *
	 * Pick on the Tundra, Device 17, to get it right.
	 */
	{
		u8 header_type;

		pci_hose_read_config_byte(hose,
					  PCI_BDF(0,BRIDGE_ID,0),
					  PCI_HEADER_TYPE,
					  &header_type);
	}
#endif

	hose->last_busno = pci_hose_scan(hose);

#ifdef CONFIG_MPC85XX_PCI2
	hose = &pci_hose[1];

	hose->first_busno = pci_hose[0].last_busno + 1;
	hose->last_busno = 0xff;

	pci_setup_indirect(hose,
			   (CONFIG_SYS_IMMR+0x9000),
			   (CONFIG_SYS_IMMR+0x9004));

	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);

	pcix2->potar1   = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff;
	pcix2->potear1  = 0x00000000;
	pcix2->powbar1  = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
	pcix2->powbear1 = 0x00000000;
	pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
			POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));

	pcix2->potar2  = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff;
	pcix2->potear2  = 0x00000000;
	pcix2->powbar2  = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
	pcix2->powbear2 = 0x00000000;
	pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
			POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));

	pcix2->pitar1 = 0x00000000;
	pcix2->piwbar1 = 0x00000000;
	pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
			PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);

	pcix2->powar3 = 0;
	pcix2->powar4 = 0;
	pcix2->piwar2 = 0;
	pcix2->piwar3 = 0;

	pci_set_region(hose->regions + 0,
		       CONFIG_SYS_PCI2_MEM_BASE,
		       CONFIG_SYS_PCI2_MEM_PHYS,
		       CONFIG_SYS_PCI2_MEM_SIZE,
		       PCI_REGION_MEM);

	pci_set_region(hose->regions + 1,
		       CONFIG_SYS_PCI2_IO_BASE,
		       CONFIG_SYS_PCI2_IO_PHYS,
		       CONFIG_SYS_PCI2_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = 2;

	/*
	 * Hose scan.
	 */
	pci_register_hose(hose);

	hose->last_busno = pci_hose_scan(hose);
#endif
}
#endif /* CONFIG_PCI */
Commit	Line	Data
42d1f039	1	/*
0ac6f8b7	2	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	3	* Copyright (C) 2003 Motorola Inc.
	4	* Xianghua Xiao (x.xiao@motorola.com)
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* PCI Configuration space access support for MPC85xx PCI Bridge
	27	*/
	28	#include <common.h>
	29	#include <asm/cpm_85xx.h>
	30	#include <pci.h>
	31
129ba616	32	#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
0ac6f8b7	33
08745460 MM	34	static struct pci_controller *pci_hose;
08745460 MM	35
9aea9530	36	void
08745460	37	pci_mpc85xx_init(struct pci_controller *board_hose)
0ac6f8b7	38	{
08745460 MM	39	u16 reg16;
	40	u32 dev;
	41
6d0f6bcf	42	volatile ccsr_pcix_t pcix = (void )(CONFIG_SYS_MPC85xx_PCIX_ADDR);
7376eb87	43	#ifdef CONFIG_MPC85XX_PCI2
6d0f6bcf	44	volatile ccsr_pcix_t pcix2 = (void )(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
7376eb87	45	#endif
6d0f6bcf	46	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
08745460	47	struct pci_controller * hose;
0ac6f8b7	48
08745460 MM	49	pci_hose = board_hose;
	50
	51	hose = &pci_hose[0];
0ac6f8b7 WD	52
	53	hose->first_busno = 0;
	54	hose->last_busno = 0xff;
	55
9aea9530	56	pci_setup_indirect(hose,
6d0f6bcf JCPV	57	(CONFIG_SYS_IMMR+0x8000),
6d0f6bcf JCPV	58	(CONFIG_SYS_IMMR+0x8004));
0ac6f8b7	59
08745460 MM	60	/*
	61	* Hose scan.
	62	*/
	63	dev = PCI_BDF(hose->first_busno, 0, 0);
	64	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
	65	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	66	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
	67
	68	/*
	69	* Clear non-reserved bits in status register.
	70	*/
	71	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	72
	73	if (!(gur->pordevsr & PORDEVSR_PCI)) {
	74	/* PCI-X init */
38433ccc MM	75	if (CONFIG_SYS_CLK_FREQ < 66000000)
	76	printf("PCI-X will only work at 66 MHz\n");
	77
08745460 MM	78	reg16 = PCI_X_CMD_MAX_SPLIT \| PCI_X_CMD_MAX_READ
	79	\| PCI_X_CMD_ERO \| PCI_X_CMD_DPERR_E;
	80	pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
	81	}
	82
6d0f6bcf	83	pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff;
9aea9530	84	pcix->potear1 = 0x00000000;
6d0f6bcf	85	pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
0ac6f8b7	86	pcix->powbear1 = 0x00000000;
08745460	87	pcix->powar1 = (POWAR_EN \| POWAR_MEM_READ \|
6d0f6bcf	88	POWAR_MEM_WRITE \| (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
0ac6f8b7	89
6d0f6bcf	90	pcix->potar2 = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff;
9aea9530	91	pcix->potear2 = 0x00000000;
6d0f6bcf	92	pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
0ac6f8b7	93	pcix->powbear2 = 0x00000000;
08745460	94	pcix->powar2 = (POWAR_EN \| POWAR_IO_READ \|
6d0f6bcf	95	POWAR_IO_WRITE \| (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
0ac6f8b7 WD	96
	97	pcix->pitar1 = 0x00000000;
	98	pcix->piwbar1 = 0x00000000;
08745460 MM	99	pcix->piwar1 = (PIWAR_EN \| PIWAR_PF \| PIWAR_LOCAL \|
08745460 MM	100	PIWAR_READ_SNOOP \| PIWAR_WRITE_SNOOP \| PIWAR_MEM_2G);
0ac6f8b7	101
08745460 MM	102	pcix->powar3 = 0;
	103	pcix->powar4 = 0;
	104	pcix->piwar2 = 0;
	105	pcix->piwar3 = 0;
cf33678e	106
08745460	107	pci_set_region(hose->regions + 0,
6d0f6bcf JCPV	108	CONFIG_SYS_PCI1_MEM_BASE,
	109	CONFIG_SYS_PCI1_MEM_PHYS,
	110	CONFIG_SYS_PCI1_MEM_SIZE,
08745460	111	PCI_REGION_MEM);
527b5a51	112
08745460	113	pci_set_region(hose->regions + 1,
6d0f6bcf JCPV	114	CONFIG_SYS_PCI1_IO_BASE,
	115	CONFIG_SYS_PCI1_IO_PHYS,
	116	CONFIG_SYS_PCI1_IO_SIZE,
08745460 MM	117	PCI_REGION_IO);
	118
	119	hose->region_count = 2;
	120
	121	pci_register_hose(hose);
527b5a51	122
cf33678e WD	123	#if defined(CONFIG_MPC8555CDS) \|\| defined(CONFIG_MPC8541CDS)
	124	/*
	125	* This is a SW workaround for an apparent HW problem
	126	* in the PCI controller on the MPC85555/41 CDS boards.
	127	* The first config cycle must be to a valid, known
	128	* device on the PCI bus in order to trick the PCI
	129	* controller state machine into a known valid state.
	130	* Without this, the first config cycle has the chance
	131	* of hanging the controller permanently, just leaving
	132	* it in a semi-working state, or leaving it working.
	133	*
	134	* Pick on the Tundra, Device 17, to get it right.
	135	*/
	136	{
	137	u8 header_type;
	138
	139	pci_hose_read_config_byte(hose,
7f3f2bd2	140	PCI_BDF(0,BRIDGE_ID,0),
cf33678e WD	141	PCI_HEADER_TYPE,
	142	&header_type);
	143	}
cf33678e WD	144	#endif
cf33678e WD	145
9aea9530	146	hose->last_busno = pci_hose_scan(hose);
08745460 MM	147
	148	#ifdef CONFIG_MPC85XX_PCI2
	149	hose = &pci_hose[1];
	150
	151	hose->first_busno = pci_hose[0].last_busno + 1;
	152	hose->last_busno = 0xff;
	153
	154	pci_setup_indirect(hose,
6d0f6bcf JCPV	155	(CONFIG_SYS_IMMR+0x9000),
6d0f6bcf JCPV	156	(CONFIG_SYS_IMMR+0x9004));
08745460 MM	157
	158	dev = PCI_BDF(hose->first_busno, 0, 0);
	159	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
	160	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	161	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
	162
	163	/*
	164	* Clear non-reserved bits in status register.
	165	*/
	166	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	167
6d0f6bcf	168	pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff;
08745460	169	pcix2->potear1 = 0x00000000;
6d0f6bcf	170	pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
08745460 MM	171	pcix2->powbear1 = 0x00000000;
08745460 MM	172	pcix2->powar1 = (POWAR_EN \| POWAR_MEM_READ \|
6d0f6bcf	173	POWAR_MEM_WRITE \| (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
08745460	174
6d0f6bcf	175	pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff;
08745460	176	pcix2->potear2 = 0x00000000;
6d0f6bcf	177	pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
08745460 MM	178	pcix2->powbear2 = 0x00000000;
08745460 MM	179	pcix2->powar2 = (POWAR_EN \| POWAR_IO_READ \|
6d0f6bcf	180	POWAR_IO_WRITE \| (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
08745460 MM	181
	182	pcix2->pitar1 = 0x00000000;
	183	pcix2->piwbar1 = 0x00000000;
	184	pcix2->piwar1 = (PIWAR_EN \| PIWAR_PF \| PIWAR_LOCAL \|
	185	PIWAR_READ_SNOOP \| PIWAR_WRITE_SNOOP \| PIWAR_MEM_2G);
	186
	187	pcix2->powar3 = 0;
	188	pcix2->powar4 = 0;
	189	pcix2->piwar2 = 0;
	190	pcix2->piwar3 = 0;
	191
	192	pci_set_region(hose->regions + 0,
6d0f6bcf JCPV	193	CONFIG_SYS_PCI2_MEM_BASE,
	194	CONFIG_SYS_PCI2_MEM_PHYS,
	195	CONFIG_SYS_PCI2_MEM_SIZE,
08745460 MM	196	PCI_REGION_MEM);
	197
	198	pci_set_region(hose->regions + 1,
6d0f6bcf JCPV	199	CONFIG_SYS_PCI2_IO_BASE,
	200	CONFIG_SYS_PCI2_IO_PHYS,
	201	CONFIG_SYS_PCI2_IO_SIZE,
08745460 MM	202	PCI_REGION_IO);
	203
	204	hose->region_count = 2;
	205
	206	/*
	207	* Hose scan.
	208	*/
	209	pci_register_hose(hose);
	210
	211	hose->last_busno = pci_hose_scan(hose);
	212	#endif
42d1f039 WD	213	}
42d1f039 WD	214	#endif /* CONFIG_PCI */