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Commit | Line | Data |
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623b6386 SG |
1 | Soft SPI |
2 | ||
3 | The soft SPI bus implementation allows the use of GPIO pins to simulate a | |
4 | SPI bus. No SPI host is required for this to work. The down-side is that the | |
5 | performance will typically be much lower than a real SPI bus. | |
6 | ||
7 | The soft SPI node requires the following properties: | |
8 | ||
32466c44 MR |
9 | Mandatory properties: |
10 | compatible: "spi-gpio" | |
11 | cs-gpios: GPIOs to use for SPI chip select (output) | |
12 | gpio-sck: GPIO to use for SPI clock (output) | |
13 | And at least one of: | |
14 | gpio-mosi: GPIO to use for SPI MOSI line (output) | |
15 | gpio-miso: GPIO to use for SPI MISO line (input) | |
16 | ||
17 | Optional propertie: | |
623b6386 SG |
18 | spi-delay-us: Number of microseconds of delay between each CS transition |
19 | ||
20 | The GPIOs should be specified as required by the GPIO controller referenced. | |
21 | The first cell holds the phandle of the controller and the second cell | |
22 | typically holds the GPIO number. | |
23 | ||
24 | ||
25 | Example: | |
26 | ||
27 | soft-spi { | |
32466c44 MR |
28 | compatible = "spi-gpio"; |
29 | cs-gpios = <&gpio 235 0>; /* Y43 */ | |
30 | gpio-sck = <&gpio 225 0>; /* Y31 */ | |
31 | gpio-mosi = <&gpio 227 0>; /* Y33 */ | |
32 | gpio-miso = <&gpio 224 0>; /* Y30 */ | |
623b6386 SG |
33 | spi-delay-us = <1>; |
34 | #address-cells = <1>; | |
35 | #size-cells = <0>; | |
36 | cs@0 { | |
37 | }; | |
38 | }; |