[people/ms/u-boot.git] / drivers / clk / rockchip / clk_rk3368.c

/*
 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
 * Author: Andy Yan <andy.yan@rock-chips.com>
 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
#include <mapmem.h>
#include <syscon.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3368.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3368-cru.h>

DECLARE_GLOBAL_DATA_PTR;

#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3368_clk_plat {
	struct dtd_rockchip_rk3368_cru dtd;
};
#endif

struct pll_div {
	u32 nr;
	u32 nf;
	u32 no;
};

#define OSC_HZ		(24 * 1000 * 1000)
#define APLL_L_HZ	(800 * 1000 * 1000)
#define APLL_B_HZ	(816 * 1000 * 1000)
#define GPLL_HZ		(576 * 1000 * 1000)
#define CPLL_HZ		(400 * 1000 * 1000)

#define RATE_TO_DIV(input_rate, output_rate) \
		((input_rate) / (output_rate) - 1);

#define DIV_TO_RATE(input_rate, div)    ((input_rate) / ((div) + 1))

#define PLL_DIVISORS(hz, _nr, _no) { \
	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
		       (_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
		       "divisors on line " __stringify(__LINE__));

static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);

/* Get pll rate by id */
static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
				   enum rk3368_pll_id pll_id)
{
	uint32_t nr, no, nf;
	uint32_t con;
	struct rk3368_pll *pll = &cru->pll[pll_id];

	con = readl(&pll->con3);

	switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
	case PLL_MODE_SLOW:
		return OSC_HZ;
	case PLL_MODE_NORMAL:
		con = readl(&pll->con0);
		no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
		nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
		con = readl(&pll->con1);
		nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;

		return (24 * nf / (nr * no)) * 1000000;
	case PLL_MODE_DEEP_SLOW:
	default:
		return 32768;
	}
}

static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
			 const struct pll_div *div)
{
	struct rk3368_pll *pll = &cru->pll[pll_id];
	/* All PLLs have same VCO and output frequency range restrictions*/
	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
	uint output_hz = vco_hz / div->no;

	debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
	      pll, div->nf, div->nr, div->no, vco_hz, output_hz);

	/* enter slow mode and reset pll */
	rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK,
		     PLL_RESET << PLL_RESET_SHIFT);

	rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK,
		     ((div->nr - 1) << PLL_NR_SHIFT) |
		     ((div->no - 1) << PLL_OD_SHIFT));
	writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
	/*
	 * BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
	 * Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
	 */
	clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);

	udelay(10);

	/* return from reset */
	rk_clrreg(&pll->con3, PLL_RESET_MASK);

	/* waiting for pll lock */
	while (!(readl(&pll->con1) & PLL_LOCK_STA))
		udelay(1);

	rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
		     PLL_MODE_NORMAL << PLL_MODE_SHIFT);

	return 0;
}

static void rkclk_init(struct rk3368_cru *cru)
{
	u32 apllb, aplll, dpll, cpll, gpll;

	rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
	rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
	rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
	rkclk_set_pll(cru, CPLL, &cpll_init_cfg);

	apllb = rkclk_pll_get_rate(cru, APLLB);
	aplll = rkclk_pll_get_rate(cru, APLLL);
	dpll = rkclk_pll_get_rate(cru, DPLL);
	cpll = rkclk_pll_get_rate(cru, CPLL);
	gpll = rkclk_pll_get_rate(cru, GPLL);

	debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
	       __func__, apllb, aplll, dpll, cpll, gpll);
}

static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
{
	u32 div, con, con_id, rate;
	u32 pll_rate;

	switch (clk_id) {
	case SCLK_SDMMC:
		con_id = 50;
		break;
	case SCLK_EMMC:
		con_id = 51;
		break;
	case SCLK_SDIO0:
		con_id = 48;
		break;
	default:
		return -EINVAL;
	}

	con = readl(&cru->clksel_con[con_id]);
	switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
	case MMC_PLL_SEL_GPLL:
		pll_rate = rkclk_pll_get_rate(cru, GPLL);
		break;
	case MMC_PLL_SEL_24M:
		pll_rate = OSC_HZ;
		break;
	case MMC_PLL_SEL_CPLL:
	case MMC_PLL_SEL_USBPHY_480M:
	default:
		return -EINVAL;
	}
	div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
	rate = DIV_TO_RATE(pll_rate, div);

	return rate >> 1;
}

static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
				ulong clk_id, ulong rate)
{
	u32 div;
	u32 con_id;
	u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);

	div = RATE_TO_DIV(gpll_rate, rate << 1);

	switch (clk_id) {
	case SCLK_SDMMC:
		con_id = 50;
		break;
	case SCLK_EMMC:
		con_id = 51;
		break;
	case SCLK_SDIO0:
		con_id = 48;
		break;
	default:
		return -EINVAL;
	}

	if (div > 0x3f) {
		div = RATE_TO_DIV(OSC_HZ, rate);
		rk_clrsetreg(&cru->clksel_con[con_id],
			     MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
			     (MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) |
			     (div << MMC_CLK_DIV_SHIFT));
	} else {
		rk_clrsetreg(&cru->clksel_con[con_id],
			     MMC_PLL_SEL_MASK | MMC_CLK_DIV_MASK,
			     (MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) |
			     div << MMC_CLK_DIV_SHIFT);
	}

	return rk3368_mmc_get_clk(cru, clk_id);
}

static ulong rk3368_clk_get_rate(struct clk *clk)
{
	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
	ulong rate = 0;

	debug("%s id:%ld\n", __func__, clk->id);
	switch (clk->id) {
	case HCLK_SDMMC:
	case HCLK_EMMC:
		rate = rk3368_mmc_get_clk(priv->cru, clk->id);
		break;
	default:
		return -ENOENT;
	}

	return rate;
}

static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
{
	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
	ulong ret = 0;

	debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
	switch (clk->id) {
	case SCLK_SDMMC:
	case SCLK_EMMC:
		ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
		break;
	default:
		return -ENOENT;
	}

	return ret;
}

static struct clk_ops rk3368_clk_ops = {
	.get_rate = rk3368_clk_get_rate,
	.set_rate = rk3368_clk_set_rate,
};

static int rk3368_clk_probe(struct udevice *dev)
{
	struct rk3368_clk_priv *priv = dev_get_priv(dev);
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	struct rk3368_clk_plat *plat = dev_get_platdata(dev);

	priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
#endif
	rkclk_init(priv->cru);

	return 0;
}

static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
	struct rk3368_clk_priv *priv = dev_get_priv(dev);

	priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);
#endif

	return 0;
}

static int rk3368_clk_bind(struct udevice *dev)
{
	int ret;

	/* The reset driver does not have a device node, so bind it here */
	ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev);
	if (ret)
		error("bind RK3368 reset driver failed: ret=%d\n", ret);

	return ret;
}

static const struct udevice_id rk3368_clk_ids[] = {
	{ .compatible = "rockchip,rk3368-cru" },
	{ }
};

U_BOOT_DRIVER(rockchip_rk3368_cru) = {
	.name		= "rockchip_rk3368_cru",
	.id		= UCLASS_CLK,
	.of_match	= rk3368_clk_ids,
	.priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	.platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
#endif
	.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
	.ops		= &rk3368_clk_ops,
	.bind		= rk3368_clk_bind,
	.probe		= rk3368_clk_probe,
};
Commit	Line	Data
d1dcf852 AY	1	/*
	2	* (C) Copyright 2017 Rockchip Electronics Co., Ltd
	3	* Author: Andy Yan <andy.yan@rock-chips.com>
ddfe77df	4	* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
d1dcf852 AY	5	* SPDX-License-Identifier: GPL-2.0
	6	*/
	7
	8	#include <common.h>
	9	#include <clk-uclass.h>
	10	#include <dm.h>
bee61801	11	#include <dt-structs.h>
d1dcf852	12	#include <errno.h>
bee61801	13	#include <mapmem.h>
d1dcf852 AY	14	#include <syscon.h>
	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/cru_rk3368.h>
	17	#include <asm/arch/hardware.h>
	18	#include <asm/io.h>
	19	#include <dm/lists.h>
	20	#include <dt-bindings/clock/rk3368-cru.h>
	21
	22	DECLARE_GLOBAL_DATA_PTR;
	23
bee61801 PT	24	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	25	struct rk3368_clk_plat {
	26	struct dtd_rockchip_rk3368_cru dtd;
	27	};
	28	#endif
	29
d1dcf852 AY	30	struct pll_div {
	31	u32 nr;
	32	u32 nf;
	33	u32 no;
	34	};
	35
	36	#define OSC_HZ (24 * 1000 * 1000)
	37	#define APLL_L_HZ (800 * 1000 * 1000)
	38	#define APLL_B_HZ (816 * 1000 * 1000)
	39	#define GPLL_HZ (576 * 1000 * 1000)
	40	#define CPLL_HZ (400 * 1000 * 1000)
	41
	42	#define RATE_TO_DIV(input_rate, output_rate) \
	43	((input_rate) / (output_rate) - 1);
	44
	45	#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
	46
	47	#define PLL_DIVISORS(hz, _nr, _no) { \
	48	.nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no}; \
	49	_Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
	50	(_nr * _no) == hz, #hz "Hz cannot be hit with PLL " \
	51	"divisors on line " __stringify(__LINE__));
	52
	53	static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
	54	static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
	55	static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
	56	static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
	57
	58	/* Get pll rate by id */
	59	static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru,
	60	enum rk3368_pll_id pll_id)
	61	{
	62	uint32_t nr, no, nf;
	63	uint32_t con;
	64	struct rk3368_pll *pll = &cru->pll[pll_id];
	65
	66	con = readl(&pll->con3);
	67
	68	switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) {
	69	case PLL_MODE_SLOW:
	70	return OSC_HZ;
	71	case PLL_MODE_NORMAL:
	72	con = readl(&pll->con0);
	73	no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1;
	74	nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1;
	75	con = readl(&pll->con1);
	76	nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1;
	77
	78	return (24 * nf / (nr * no)) * 1000000;
	79	case PLL_MODE_DEEP_SLOW:
	80	default:
	81	return 32768;
	82	}
	83	}
	84
	85	static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id,
ddfe77df	86	const struct pll_div *div)
d1dcf852 AY	87	{
	88	struct rk3368_pll *pll = &cru->pll[pll_id];
	89	/* All PLLs have same VCO and output frequency range restrictions*/
	90	uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
	91	uint output_hz = vco_hz / div->no;
	92
	93	debug("PLL at %p: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
	94	pll, div->nf, div->nr, div->no, vco_hz, output_hz);
	95
	96	/* enter slow mode and reset pll */
	97	rk_clrsetreg(&pll->con3, PLL_MODE_MASK \| PLL_RESET_MASK,
	98	PLL_RESET << PLL_RESET_SHIFT);
	99
	100	rk_clrsetreg(&pll->con0, PLL_NR_MASK \| PLL_OD_MASK,
	101	((div->nr - 1) << PLL_NR_SHIFT) \|
	102	((div->no - 1) << PLL_OD_SHIFT));
	103	writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1);
ddfe77df PT	104	/*
	105	* BWADJ should be set to NF / 2 to ensure the nominal bandwidth.
	106	* Compare the RK3368 TRM, section "3.6.4 PLL Bandwidth Adjustment".
	107	*/
	108	clrsetbits_le32(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
	109
d1dcf852 AY	110	udelay(10);
	111
	112	/* return from reset */
	113	rk_clrreg(&pll->con3, PLL_RESET_MASK);
	114
	115	/* waiting for pll lock */
	116	while (!(readl(&pll->con1) & PLL_LOCK_STA))
	117	udelay(1);
	118
	119	rk_clrsetreg(&pll->con3, PLL_MODE_MASK,
	120	PLL_MODE_NORMAL << PLL_MODE_SHIFT);
	121
	122	return 0;
	123	}
	124
	125	static void rkclk_init(struct rk3368_cru *cru)
	126	{
	127	u32 apllb, aplll, dpll, cpll, gpll;
	128
ddfe77df PT	129	rkclk_set_pll(cru, APLLB, &apll_b_init_cfg);
	130	rkclk_set_pll(cru, APLLL, &apll_l_init_cfg);
	131	rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
	132	rkclk_set_pll(cru, CPLL, &cpll_init_cfg);
d1dcf852 AY	133
	134	apllb = rkclk_pll_get_rate(cru, APLLB);
	135	aplll = rkclk_pll_get_rate(cru, APLLL);
	136	dpll = rkclk_pll_get_rate(cru, DPLL);
	137	cpll = rkclk_pll_get_rate(cru, CPLL);
	138	gpll = rkclk_pll_get_rate(cru, GPLL);
	139
	140	debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
	141	__func__, apllb, aplll, dpll, cpll, gpll);
	142	}
	143
	144	static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id)
	145	{
	146	u32 div, con, con_id, rate;
	147	u32 pll_rate;
	148
	149	switch (clk_id) {
	150	case SCLK_SDMMC:
	151	con_id = 50;
	152	break;
	153	case SCLK_EMMC:
	154	con_id = 51;
	155	break;
	156	case SCLK_SDIO0:
	157	con_id = 48;
	158	break;
	159	default:
	160	return -EINVAL;
	161	}
	162
	163	con = readl(&cru->clksel_con[con_id]);
	164	switch ((con & MMC_PLL_SEL_MASK) >> MMC_PLL_SEL_SHIFT) {
	165	case MMC_PLL_SEL_GPLL:
	166	pll_rate = rkclk_pll_get_rate(cru, GPLL);
	167	break;
	168	case MMC_PLL_SEL_24M:
	169	pll_rate = OSC_HZ;
	170	break;
	171	case MMC_PLL_SEL_CPLL:
	172	case MMC_PLL_SEL_USBPHY_480M:
	173	default:
	174	return -EINVAL;
	175	}
	176	div = (con & MMC_CLK_DIV_MASK) >> MMC_CLK_DIV_SHIFT;
	177	rate = DIV_TO_RATE(pll_rate, div);
	178
	179	return rate >> 1;
	180	}
	181
	182	static ulong rk3368_mmc_set_clk(struct rk3368_cru *cru,
	183	ulong clk_id, ulong rate)
	184	{
	185	u32 div;
	186	u32 con_id;
	187	u32 gpll_rate = rkclk_pll_get_rate(cru, GPLL);
	188
	189	div = RATE_TO_DIV(gpll_rate, rate << 1);
	190
	191	switch (clk_id) {
	192	case SCLK_SDMMC:
	193	con_id = 50;
	194	break;
	195	case SCLK_EMMC:
	196	con_id = 51;
197	break;
198	case SCLK_SDIO0:
199	con_id = 48;
200	break;
201	default:
202	return -EINVAL;
203	}
204
205	if (div > 0x3f) {
206	div = RATE_TO_DIV(OSC_HZ, rate);
207	rk_clrsetreg(&cru->clksel_con[con_id],
208	MMC_PLL_SEL_MASK \| MMC_CLK_DIV_MASK,
209	(MMC_PLL_SEL_24M << MMC_PLL_SEL_SHIFT) \|
210	(div << MMC_CLK_DIV_SHIFT));
211	} else {
212	rk_clrsetreg(&cru->clksel_con[con_id],
213	MMC_PLL_SEL_MASK \| MMC_CLK_DIV_MASK,
214	(MMC_PLL_SEL_GPLL << MMC_PLL_SEL_SHIFT) \|
215	div << MMC_CLK_DIV_SHIFT);
216	}
217
218	return rk3368_mmc_get_clk(cru, clk_id);
219	}
220
221	static ulong rk3368_clk_get_rate(struct clk *clk)
222	{
223	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
224	ulong rate = 0;
225
226	debug("%s id:%ld\n", __func__, clk->id);
227	switch (clk->id) {
228	case HCLK_SDMMC:
229	case HCLK_EMMC:
230	rate = rk3368_mmc_get_clk(priv->cru, clk->id);
231	break;
232	default:
233	return -ENOENT;
234	}
235
236	return rate;
237	}
238
239	static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
240	{
241	struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);
242	ulong ret = 0;
243
244	debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
245	switch (clk->id) {
246	case SCLK_SDMMC:
247	case SCLK_EMMC:
248	ret = rk3368_mmc_set_clk(priv->cru, clk->id, rate);
249	break;
250	default:
251	return -ENOENT;
252	}
253
254	return ret;
255	}
256
257	static struct clk_ops rk3368_clk_ops = {
258	.get_rate = rk3368_clk_get_rate,
259	.set_rate = rk3368_clk_set_rate,
260	};
261
262	static int rk3368_clk_probe(struct udevice *dev)
263	{
264	struct rk3368_clk_priv *priv = dev_get_priv(dev);
bee61801 PT	265	#if CONFIG_IS_ENABLED(OF_PLATDATA)
bee61801 PT	266	struct rk3368_clk_plat *plat = dev_get_platdata(dev);
d1dcf852	267
bee61801 PT	268	priv->cru = map_sysmem(plat->dtd.reg[1], plat->dtd.reg[3]);
bee61801 PT	269	#endif
d1dcf852 AY	270	rkclk_init(priv->cru);
	271
	272	return 0;
	273	}
	274
	275	static int rk3368_clk_ofdata_to_platdata(struct udevice *dev)
	276	{
bee61801	277	#if !CONFIG_IS_ENABLED(OF_PLATDATA)
d1dcf852 AY	278	struct rk3368_clk_priv *priv = dev_get_priv(dev);
	279
	280	priv->cru = (struct rk3368_cru *)devfdt_get_addr(dev);
bee61801	281	#endif
d1dcf852 AY	282
	283	return 0;
	284	}
	285
	286	static int rk3368_clk_bind(struct udevice *dev)
	287	{
	288	int ret;
	289
	290	/* The reset driver does not have a device node, so bind it here */
	291	ret = device_bind_driver(gd->dm_root, "rk3368_sysreset", "reset", &dev);
	292	if (ret)
	293	error("bind RK3368 reset driver failed: ret=%d\n", ret);
	294
	295	return ret;
	296	}
	297
	298	static const struct udevice_id rk3368_clk_ids[] = {
	299	{ .compatible = "rockchip,rk3368-cru" },
	300	{ }
	301	};
	302
	303	U_BOOT_DRIVER(rockchip_rk3368_cru) = {
	304	.name = "rockchip_rk3368_cru",
	305	.id = UCLASS_CLK,
	306	.of_match = rk3368_clk_ids,
cdc6080a	307	.priv_auto_alloc_size = sizeof(struct rk3368_clk_priv),
bee61801 PT	308	#if CONFIG_IS_ENABLED(OF_PLATDATA)
	309	.platdata_auto_alloc_size = sizeof(struct rk3368_clk_plat),
	310	#endif
d1dcf852 AY	311	.ofdata_to_platdata = rk3368_clk_ofdata_to_platdata,
	312	.ops = &rk3368_clk_ops,
	313	.bind = rk3368_clk_bind,
	314	.probe = rk3368_clk_probe,
	315	};