[people/ms/u-boot.git] / drivers / misc / mxc_ocotp.c

/*
 * (C) Copyright 2013 ADVANSEE
 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
 *
 * Based on Dirk Behme's
 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
 * which is based on Freescale's
 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
 * which is:
 * Copyright (C) 2011 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <fuse.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>

#define BO_CTRL_WR_UNLOCK		16
#define BM_CTRL_WR_UNLOCK		0xffff0000
#define BV_CTRL_WR_UNLOCK_KEY		0x3e77
#define BM_CTRL_ERROR			0x00000200
#define BM_CTRL_BUSY			0x00000100
#define BO_CTRL_ADDR			0
#ifdef CONFIG_MX7
#define BM_CTRL_ADDR                    0x0000000f
#define BM_CTRL_RELOAD                  0x00000400
#else
#define BM_CTRL_ADDR			0x0000007f
#endif

#ifdef CONFIG_MX7
#define BO_TIMING_FSOURCE               12
#define BM_TIMING_FSOURCE               0x0007f000
#define BV_TIMING_FSOURCE_NS            1001
#define BO_TIMING_PROG                  0
#define BM_TIMING_PROG                  0x00000fff
#define BV_TIMING_PROG_US               10
#else
#define BO_TIMING_STROBE_READ		16
#define BM_TIMING_STROBE_READ		0x003f0000
#define BV_TIMING_STROBE_READ_NS	37
#define BO_TIMING_RELAX			12
#define BM_TIMING_RELAX			0x0000f000
#define BV_TIMING_RELAX_NS		17
#define BO_TIMING_STROBE_PROG		0
#define BM_TIMING_STROBE_PROG		0x00000fff
#define BV_TIMING_STROBE_PROG_US	10
#endif

#define BM_READ_CTRL_READ_FUSE		0x00000001

#define BF(value, field)		(((value) << BO_##field) & BM_##field)

#define WRITE_POSTAMBLE_US		2

static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
{
	while (readl(&regs->ctrl) & BM_CTRL_BUSY)
		udelay(delay_us);
}

static void clear_error(struct ocotp_regs *regs)
{
	writel(BM_CTRL_ERROR, &regs->ctrl_clr);
}

static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
				int assert, const char *caller)
{
	*regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;

	if (bank >= ARRAY_SIZE((*regs)->bank) ||
			word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
			!assert) {
		printf("mxc_ocotp %s(): Invalid argument\n", caller);
		return -EINVAL;
	}

	enable_ocotp_clk(1);

	wait_busy(*regs, 1);
	clear_error(*regs);

	return 0;
}

static int finish_access(struct ocotp_regs *regs, const char *caller)
{
	u32 err;

	err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
	clear_error(regs);

	if (err) {
		printf("mxc_ocotp %s(): Access protect error\n", caller);
		return -EIO;
	}

	return 0;
}

static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
			const char *caller)
{
	return prepare_access(regs, bank, word, val != NULL, caller);
}

int fuse_read(u32 bank, u32 word, u32 *val)
{
	struct ocotp_regs *regs;
	int ret;

	ret = prepare_read(&regs, bank, word, val, __func__);
	if (ret)
		return ret;

	*val = readl(&regs->bank[bank].fuse_regs[word << 2]);

	return finish_access(regs, __func__);
}

#ifdef CONFIG_MX7
static void set_timing(struct ocotp_regs *regs)
{
	u32 ipg_clk;
	u32 fsource, prog;
	u32 timing;

	ipg_clk = mxc_get_clock(MXC_IPG_CLK);

	fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
			+       1000000) + 1;
	prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;

	timing = BF(fsource, TIMING_FSOURCE) | BF(prog, TIMING_PROG);

	clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE | BM_TIMING_PROG,
			timing);
}
#else
static void set_timing(struct ocotp_regs *regs)
{
	u32 ipg_clk;
	u32 relax, strobe_read, strobe_prog;
	u32 timing;

	ipg_clk = mxc_get_clock(MXC_IPG_CLK);

	relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
	strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
					1000000000) + 2 * (relax + 1) - 1;
	strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
						1000000) + 2 * (relax + 1) - 1;

	timing = BF(strobe_read, TIMING_STROBE_READ) |
			BF(relax, TIMING_RELAX) |
			BF(strobe_prog, TIMING_STROBE_PROG);

	clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
			BM_TIMING_STROBE_PROG, timing);
}
#endif

static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
				int write)
{
	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
#ifdef CONFIG_MX7
	u32 addr = bank;
#else
	u32 addr = bank << 3 | word;
#endif

	set_timing(regs);
	clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
			BF(wr_unlock, CTRL_WR_UNLOCK) |
			BF(addr, CTRL_ADDR));
}

int fuse_sense(u32 bank, u32 word, u32 *val)
{
	struct ocotp_regs *regs;
	int ret;

	ret = prepare_read(&regs, bank, word, val, __func__);
	if (ret)
		return ret;

	setup_direct_access(regs, bank, word, false);
	writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
	wait_busy(regs, 1);
#ifdef CONFIG_MX7
	*val = readl((&regs->read_fuse_data0) + (word << 2));
#else
	*val = readl(&regs->read_fuse_data);
#endif

	return finish_access(regs, __func__);
}

static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
				const char *caller)
{
	return prepare_access(regs, bank, word, true, caller);
}

int fuse_prog(u32 bank, u32 word, u32 val)
{
	struct ocotp_regs *regs;
	int ret;

	ret = prepare_write(&regs, bank, word, __func__);
	if (ret)
		return ret;

	setup_direct_access(regs, bank, word, true);
#ifdef CONFIG_MX7
	switch (word) {
	case 0:
		writel(0, &regs->data1);
		writel(0, &regs->data2);
		writel(0, &regs->data3);
		writel(val, &regs->data0);
		break;
	case 1:
		writel(val, &regs->data1);
		writel(0, &regs->data2);
		writel(0, &regs->data3);
		writel(0, &regs->data0);
		break;
	case 2:
		writel(0, &regs->data1);
		writel(val, &regs->data2);
		writel(0, &regs->data3);
		writel(0, &regs->data0);
		break;
	case 3:
		writel(0, &regs->data1);
		writel(0, &regs->data2);
		writel(val, &regs->data3);
		writel(0, &regs->data0);
		break;
	}
	wait_busy(regs, BV_TIMING_PROG_US);
#else
	writel(val, &regs->data);
	wait_busy(regs, BV_TIMING_STROBE_PROG_US);
#endif
	udelay(WRITE_POSTAMBLE_US);

	return finish_access(regs, __func__);
}

int fuse_override(u32 bank, u32 word, u32 val)
{
	struct ocotp_regs *regs;
	int ret;

	ret = prepare_write(&regs, bank, word, __func__);
	if (ret)
		return ret;

	writel(val, &regs->bank[bank].fuse_regs[word << 2]);

	return finish_access(regs, __func__);
}
Commit	Line	Data
112fd2ec BT	1	/*
	2	* (C) Copyright 2013 ADVANSEE
	3	* Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
	4	*
	5	* Based on Dirk Behme's
	6	* https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
	7	* which is based on Freescale's
	8	* http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
	9	* which is:
	10	* Copyright (C) 2011 Freescale Semiconductor, Inc.
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
112fd2ec BT	13	*/
	14
	15	#include <common.h>
	16	#include <fuse.h>
	17	#include <asm/errno.h>
	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/imx-regs.h>
	21
	22	#define BO_CTRL_WR_UNLOCK 16
	23	#define BM_CTRL_WR_UNLOCK 0xffff0000
	24	#define BV_CTRL_WR_UNLOCK_KEY 0x3e77
	25	#define BM_CTRL_ERROR 0x00000200
	26	#define BM_CTRL_BUSY 0x00000100
	27	#define BO_CTRL_ADDR 0
42c91c10 AA	28	#ifdef CONFIG_MX7
	29	#define BM_CTRL_ADDR 0x0000000f
	30	#define BM_CTRL_RELOAD 0x00000400
	31	#else
112fd2ec	32	#define BM_CTRL_ADDR 0x0000007f
42c91c10 AA	33	#endif
	34
	35	#ifdef CONFIG_MX7
	36	#define BO_TIMING_FSOURCE 12
	37	#define BM_TIMING_FSOURCE 0x0007f000
	38	#define BV_TIMING_FSOURCE_NS 1001
	39	#define BO_TIMING_PROG 0
	40	#define BM_TIMING_PROG 0x00000fff
	41	#define BV_TIMING_PROG_US 10
	42	#else
112fd2ec BT	43	#define BO_TIMING_STROBE_READ 16
	44	#define BM_TIMING_STROBE_READ 0x003f0000
	45	#define BV_TIMING_STROBE_READ_NS 37
	46	#define BO_TIMING_RELAX 12
	47	#define BM_TIMING_RELAX 0x0000f000
	48	#define BV_TIMING_RELAX_NS 17
	49	#define BO_TIMING_STROBE_PROG 0
	50	#define BM_TIMING_STROBE_PROG 0x00000fff
	51	#define BV_TIMING_STROBE_PROG_US 10
42c91c10	52	#endif
112fd2ec BT	53
	54	#define BM_READ_CTRL_READ_FUSE 0x00000001
	55
	56	#define BF(value, field) (((value) << BO_##field) & BM_##field)
	57
	58	#define WRITE_POSTAMBLE_US 2
	59
	60	static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
	61	{
	62	while (readl(&regs->ctrl) & BM_CTRL_BUSY)
	63	udelay(delay_us);
	64	}
	65
	66	static void clear_error(struct ocotp_regs *regs)
	67	{
	68	writel(BM_CTRL_ERROR, &regs->ctrl_clr);
	69	}
	70
	71	static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
	72	int assert, const char *caller)
	73	{
	74	regs = (struct ocotp_regs )OCOTP_BASE_ADDR;
	75
	76	if (bank >= ARRAY_SIZE((*regs)->bank) \|\|
	77	word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 \|\|
	78	!assert) {
	79	printf("mxc_ocotp %s(): Invalid argument\n", caller);
	80	return -EINVAL;
	81	}
	82
	83	enable_ocotp_clk(1);
	84
	85	wait_busy(*regs, 1);
	86	clear_error(*regs);
	87
	88	return 0;
	89	}
	90
	91	static int finish_access(struct ocotp_regs regs, const char caller)
	92	{
	93	u32 err;
	94
	95	err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
	96	clear_error(regs);
	97
112fd2ec BT	98	if (err) {
	99	printf("mxc_ocotp %s(): Access protect error\n", caller);
	100	return -EIO;
	101	}
	102
	103	return 0;
	104	}
	105
	106	static int prepare_read(struct ocotp_regs *regs, u32 bank, u32 word, u32 val,
	107	const char *caller)
	108	{
	109	return prepare_access(regs, bank, word, val != NULL, caller);
	110	}
	111
	112	int fuse_read(u32 bank, u32 word, u32 *val)
	113	{
	114	struct ocotp_regs *regs;
	115	int ret;
	116
	117	ret = prepare_read(&regs, bank, word, val, __func__);
	118	if (ret)
	119	return ret;
	120
	121	*val = readl(&regs->bank[bank].fuse_regs[word << 2]);
	122
	123	return finish_access(regs, __func__);
	124	}
	125
42c91c10 AA	126	#ifdef CONFIG_MX7
	127	static void set_timing(struct ocotp_regs *regs)
	128	{
	129	u32 ipg_clk;
	130	u32 fsource, prog;
	131	u32 timing;
	132
	133	ipg_clk = mxc_get_clock(MXC_IPG_CLK);
	134
	135	fsource = DIV_ROUND_UP((ipg_clk / 1000) * BV_TIMING_FSOURCE_NS,
	136	+ 1000000) + 1;
	137	prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_PROG_US, 1000000) + 1;
	138
	139	timing = BF(fsource, TIMING_FSOURCE) \| BF(prog, TIMING_PROG);
	140
	141	clrsetbits_le32(&regs->timing, BM_TIMING_FSOURCE \| BM_TIMING_PROG,
	142	timing);
	143	}
	144	#else
112fd2ec BT	145	static void set_timing(struct ocotp_regs *regs)
	146	{
	147	u32 ipg_clk;
	148	u32 relax, strobe_read, strobe_prog;
	149	u32 timing;
	150
	151	ipg_clk = mxc_get_clock(MXC_IPG_CLK);
	152
	153	relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
	154	strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
	155	1000000000) + 2 * (relax + 1) - 1;
4515992f MY	156	strobe_prog = DIV_ROUND_CLOSEST(ipg_clk * BV_TIMING_STROBE_PROG_US,
4515992f MY	157	1000000) + 2 * (relax + 1) - 1;
112fd2ec BT	158
	159	timing = BF(strobe_read, TIMING_STROBE_READ) \|
	160	BF(relax, TIMING_RELAX) \|
	161	BF(strobe_prog, TIMING_STROBE_PROG);
	162
	163	clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ \| BM_TIMING_RELAX \|
	164	BM_TIMING_STROBE_PROG, timing);
	165	}
42c91c10	166	#endif
112fd2ec BT	167
	168	static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
	169	int write)
	170	{
	171	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
42c91c10 AA	172	#ifdef CONFIG_MX7
	173	u32 addr = bank;
	174	#else
112fd2ec	175	u32 addr = bank << 3 \| word;
42c91c10	176	#endif
112fd2ec BT	177
	178	set_timing(regs);
	179	clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK \| BM_CTRL_ADDR,
	180	BF(wr_unlock, CTRL_WR_UNLOCK) \|
	181	BF(addr, CTRL_ADDR));
	182	}
	183
	184	int fuse_sense(u32 bank, u32 word, u32 *val)
	185	{
	186	struct ocotp_regs *regs;
	187	int ret;
	188
	189	ret = prepare_read(&regs, bank, word, val, __func__);
	190	if (ret)
	191	return ret;
	192
	193	setup_direct_access(regs, bank, word, false);
	194	writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
	195	wait_busy(regs, 1);
42c91c10 AA	196	#ifdef CONFIG_MX7
	197	*val = readl((&regs->read_fuse_data0) + (word << 2));
	198	#else
112fd2ec	199	*val = readl(&regs->read_fuse_data);
42c91c10	200	#endif
112fd2ec BT	201
	202	return finish_access(regs, __func__);
	203	}
	204
	205	static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
	206	const char *caller)
	207	{
	208	return prepare_access(regs, bank, word, true, caller);
	209	}
	210
	211	int fuse_prog(u32 bank, u32 word, u32 val)
	212	{
	213	struct ocotp_regs *regs;
	214	int ret;
	215
	216	ret = prepare_write(&regs, bank, word, __func__);
	217	if (ret)
	218	return ret;
	219
	220	setup_direct_access(regs, bank, word, true);
42c91c10 AA	221	#ifdef CONFIG_MX7
	222	switch (word) {
	223	case 0:
	224	writel(0, &regs->data1);
	225	writel(0, &regs->data2);
	226	writel(0, &regs->data3);
	227	writel(val, &regs->data0);
	228	break;
	229	case 1:
	230	writel(val, &regs->data1);
	231	writel(0, &regs->data2);
	232	writel(0, &regs->data3);
	233	writel(0, &regs->data0);
	234	break;
	235	case 2:
	236	writel(0, &regs->data1);
	237	writel(val, &regs->data2);
	238	writel(0, &regs->data3);
	239	writel(0, &regs->data0);
	240	break;
	241	case 3:
	242	writel(0, &regs->data1);
	243	writel(0, &regs->data2);
	244	writel(val, &regs->data3);
	245	writel(0, &regs->data0);
	246	break;
	247	}
	248	wait_busy(regs, BV_TIMING_PROG_US);
	249	#else
112fd2ec BT	250	writel(val, &regs->data);
112fd2ec BT	251	wait_busy(regs, BV_TIMING_STROBE_PROG_US);
42c91c10	252	#endif
112fd2ec BT	253	udelay(WRITE_POSTAMBLE_US);
	254
	255	return finish_access(regs, __func__);
	256	}
	257
	258	int fuse_override(u32 bank, u32 word, u32 val)
	259	{
	260	struct ocotp_regs *regs;
	261	int ret;
	262
	263	ret = prepare_write(&regs, bank, word, __func__);
	264	if (ret)
	265	return ret;
	266
	267	writel(val, &regs->bank[bank].fuse_regs[word << 2]);
	268
	269	return finish_access(regs, __func__);
	270	}