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mmc: uniphier-sd: return error code if unsupported width is given
[people/ms/u-boot.git] / drivers / mmc / uniphier-sd.c
CommitLineData
a111bfbf 1/*
4e3d8406
MY		 2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
a111bfbf
MY		 4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <clk.h>
10#include <fdtdec.h>
a111bfbf
MY		 11#include <mmc.h>
12#include <dm/device.h>
13#include <linux/compat.h>
14#include <linux/io.h>
4f80501b 15#include <linux/sizes.h>
a111bfbf
MY		 16#include <asm/unaligned.h>
17#include <asm/dma-mapping.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21#define UNIPHIER_SD_CMD 0x000 /* command */
22#define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
23#define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */
24#define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */
25#define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */
26#define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
27#define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
28#define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */
29#define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
30#define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
31#define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
32#define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
33#define UNIPHIER_SD_ARG 0x008 /* command argument */
34#define UNIPHIER_SD_STOP 0x010 /* stop action control */
35#define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */
36#define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */
37#define UNIPHIER_SD_SECCNT 0x014 /* sector counter */
38#define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */
39#define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */
40#define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */
41#define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */
42#define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */
43#define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */
44#define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */
45#define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */
46#define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */
47#define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */
48#define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */
49#define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
50#define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */
51#define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */
52#define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */
53#define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
54#define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */
55#define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
56#define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
57#define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */
58#define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */
59#define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
60#define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
61#define UNIPHIER_SD_INFO1_MASK 0x040
62#define UNIPHIER_SD_INFO2_MASK 0x044
63#define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */
64#define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff
65#define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
66#define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
67#define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
68#define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
69#define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
70#define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
71#define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
72#define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
73#define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
74#define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
75#define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
76#define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
77#define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
78#define UNIPHIER_SD_SIZE 0x04c /* block size */
79#define UNIPHIER_SD_OPTION 0x050
80#define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13)
81#define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13)
82#define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13)
83#define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13)
84#define UNIPHIER_SD_BUF 0x060 /* read/write buffer */
85#define UNIPHIER_SD_EXTMODE 0x1b0
86#define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
87#define UNIPHIER_SD_SOFT_RST 0x1c0
88#define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
89#define UNIPHIER_SD_VERSION 0x1c4 /* version register */
90#define UNIPHIER_SD_VERSION_IP 0xff /* IP version */
91#define UNIPHIER_SD_HOST_MODE 0x1c8
92#define UNIPHIER_SD_IF_MODE 0x1cc
93#define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */
94#define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */
95#define UNIPHIER_SD_VOLT_MASK (3 << 0)
96#define UNIPHIER_SD_VOLT_OFF (0 << 0)
97#define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */
98#define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */
99#define UNIPHIER_SD_DMA_MODE 0x410
100#define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
101#define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
102#define UNIPHIER_SD_DMA_CTL 0x414
103#define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
104#define UNIPHIER_SD_DMA_RST 0x418
105#define UNIPHIER_SD_DMA_RST_RD BIT(9)
106#define UNIPHIER_SD_DMA_RST_WR BIT(8)
107#define UNIPHIER_SD_DMA_INFO1 0x420
108#define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/
109#define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */
110#define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
111#define UNIPHIER_SD_DMA_INFO1_MASK 0x424
112#define UNIPHIER_SD_DMA_INFO2 0x428
113#define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17)
114#define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16)
115#define UNIPHIER_SD_DMA_INFO2_MASK 0x42c
116#define UNIPHIER_SD_DMA_ADDR_L 0x440
117#define UNIPHIER_SD_DMA_ADDR_H 0x444
118
119/* alignment required by the DMA engine of this controller */
120#define UNIPHIER_SD_DMA_MINALIGN 0x10
121
122struct uniphier_sd_priv {
123 struct mmc_config cfg;
124 struct mmc *mmc;
a111bfbf
MY		 125 void __iomem *regbase;
126 unsigned long mclk;
127 unsigned int version;
128 u32 caps;
129#define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
130#define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
131#define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
132};
133
134static dma_addr_t __dma_map_single(void *ptr, size_t size,
135 enum dma_data_direction dir)
136{
137 unsigned long addr = (unsigned long)ptr;
138
139 if (dir == DMA_FROM_DEVICE)
140 invalidate_dcache_range(addr, addr + size);
141 else
142 flush_dcache_range(addr, addr + size);
143
144 return addr;
145}
146
147static void __dma_unmap_single(dma_addr_t addr, size_t size,
148 enum dma_data_direction dir)
149{
150 if (dir != DMA_TO_DEVICE)
151 invalidate_dcache_range(addr, addr + size);
152}
153
3937404f 154static int uniphier_sd_check_error(struct udevice *dev)
a111bfbf 155{
3937404f 156 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 157 u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2);
158
159 if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
160 /*
161 * TIMEOUT must be returned for unsupported command. Do not
162 * display error log since this might be a part of sequence to
163 * distinguish between SD and MMC.
164 */
915ffa52 165 return -ETIMEDOUT;
a111bfbf
MY		 166 }
167
168 if (info2 & UNIPHIER_SD_INFO2_ERR_TO) {
3937404f 169 dev_err(dev, "timeout error\n");
a111bfbf
MY		 170 return -ETIMEDOUT;
171 }
172
173 if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC |
174 UNIPHIER_SD_INFO2_ERR_IDX)) {
3937404f 175 dev_err(dev, "communication out of sync\n");
a111bfbf
MY		 176 return -EILSEQ;
177 }
178
179 if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR |
180 UNIPHIER_SD_INFO2_ERR_ILW)) {
3937404f 181 dev_err(dev, "illegal access\n");
a111bfbf
MY		 182 return -EIO;
183 }
184
185 return 0;
186}
187
3937404f
MY		 188static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
189 u32 flag)
a111bfbf 190{
3937404f 191 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 192 long wait = 1000000;
193 int ret;
194
195 while (!(readl(priv->regbase + reg) & flag)) {
196 if (wait-- < 0) {
3937404f 197 dev_err(dev, "timeout\n");
a111bfbf
MY		 198 return -ETIMEDOUT;
199 }
200
3937404f 201 ret = uniphier_sd_check_error(dev);
a111bfbf
MY		 202 if (ret)
203 return ret;
204
205 udelay(1);
206 }
207
208 return 0;
209}
210
3937404f 211static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
a111bfbf
MY		 212 uint blocksize)
213{
3937404f 214 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 215 int i, ret;
216
217 /* wait until the buffer is filled with data */
3937404f 218 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
a111bfbf
MY		 219 UNIPHIER_SD_INFO2_BRE);
220 if (ret)
221 return ret;
222
223 /*
224 * Clear the status flag _before_ read the buffer out because
225 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
226 */
227 writel(0, priv->regbase + UNIPHIER_SD_INFO2);
228
229 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
230 for (i = 0; i < blocksize / 4; i++)
231 *(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF);
232 } else {
233 for (i = 0; i < blocksize / 4; i++)
234 put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF),
235 (*pbuf)++);
236 }
237
238 return 0;
239}
240
3937404f
MY		 241static int uniphier_sd_pio_write_one_block(struct udevice *dev,
242 const u32 **pbuf, uint blocksize)
a111bfbf 243{
3937404f 244 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 245 int i, ret;
246
247 /* wait until the buffer becomes empty */
3937404f 248 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO2,
a111bfbf
MY		 249 UNIPHIER_SD_INFO2_BWE);
250 if (ret)
251 return ret;
252
253 writel(0, priv->regbase + UNIPHIER_SD_INFO2);
254
255 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
256 for (i = 0; i < blocksize / 4; i++)
257 writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF);
258 } else {
259 for (i = 0; i < blocksize / 4; i++)
260 writel(get_unaligned((*pbuf)++),
261 priv->regbase + UNIPHIER_SD_BUF);
262 }
263
264 return 0;
265}
266
3937404f 267static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
a111bfbf
MY		 268{
269 u32 *dest = (u32 *)data->dest;
270 const u32 *src = (const u32 *)data->src;
271 int i, ret;
272
273 for (i = 0; i < data->blocks; i++) {
274 if (data->flags & MMC_DATA_READ)
3937404f 275 ret = uniphier_sd_pio_read_one_block(dev, &dest,
a111bfbf
MY		 276 data->blocksize);
277 else
3937404f 278 ret = uniphier_sd_pio_write_one_block(dev, &src,
a111bfbf
MY		 279 data->blocksize);
280 if (ret)
281 return ret;
282 }
283
284 return 0;
285}
286
287static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
288 dma_addr_t dma_addr)
289{
290 u32 tmp;
291
292 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1);
293 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2);
294
295 /* enable DMA */
296 tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
297 tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
298 writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
299
300 writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L);
301
302 /* suppress the warning "right shift count >= width of type" */
303 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
304
305 writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H);
306
307 writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL);
308}
309
3937404f 310static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
a111bfbf
MY		 311 unsigned int blocks)
312{
3937404f 313 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 314 long wait = 1000000 + 10 * blocks;
315
316 while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) {
317 if (wait-- < 0) {
3937404f 318 dev_err(dev, "timeout during DMA\n");
a111bfbf
MY		 319 return -ETIMEDOUT;
320 }
321
322 udelay(10);
323 }
324
325 if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) {
3937404f 326 dev_err(dev, "error during DMA\n");
a111bfbf
MY		 327 return -EIO;
328 }
329
330 return 0;
331}
332
3937404f 333static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
a111bfbf 334{
3937404f 335 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 336 size_t len = data->blocks * data->blocksize;
337 void *buf;
338 enum dma_data_direction dir;
339 dma_addr_t dma_addr;
340 u32 poll_flag, tmp;
341 int ret;
342
343 tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
344
345 if (data->flags & MMC_DATA_READ) {
346 buf = data->dest;
347 dir = DMA_FROM_DEVICE;
348 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2;
349 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD;
350 } else {
351 buf = (void *)data->src;
352 dir = DMA_TO_DEVICE;
353 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR;
354 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
355 }
356
357 writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
358
359 dma_addr = __dma_map_single(buf, len, dir);
360
361 uniphier_sd_dma_start(priv, dma_addr);
362
3937404f 363 ret = uniphier_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
a111bfbf
MY		 364
365 __dma_unmap_single(dma_addr, len, dir);
366
367 return ret;
368}
369
370/* check if the address is DMA'able */
371static bool uniphier_sd_addr_is_dmaable(unsigned long addr)
372{
373 if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN))
374 return false;
375
376#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
377 defined(CONFIG_SPL_BUILD)
378 /*
379 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
380 * of L2, which is unreachable from the DMA engine.
381 */
382 if (addr < CONFIG_SPL_STACK)
383 return false;
384#endif
385
386 return true;
387}
388
3937404f 389static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
a111bfbf
MY		 390 struct mmc_data *data)
391{
3937404f 392 struct uniphier_sd_priv *priv = dev_get_priv(dev);
a111bfbf
MY		 393 int ret;
394 u32 tmp;
395
396 if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
3937404f 397 dev_err(dev, "command busy\n");
a111bfbf
MY		 398 return -EBUSY;
399 }
400
401 /* clear all status flags */
402 writel(0, priv->regbase + UNIPHIER_SD_INFO1);
403 writel(0, priv->regbase + UNIPHIER_SD_INFO2);
404
405 /* disable DMA once */
406 tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
407 tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
408 writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
409
410 writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG);
411
412 tmp = cmd->cmdidx;
413
414 if (data) {
415 writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE);
416 writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT);
417
418 /* Do not send CMD12 automatically */
419 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
420
421 if (data->blocks > 1)
422 tmp |= UNIPHIER_SD_CMD_MULTI;
423
424 if (data->flags & MMC_DATA_READ)
425 tmp |= UNIPHIER_SD_CMD_RD;
426 }
427
428 /*
429 * Do not use the response type auto-detection on this hardware.
430 * CMD8, for example, has different response types on SD and eMMC,
431 * while this controller always assumes the response type for SD.
432 * Set the response type manually.
433 */
434 switch (cmd->resp_type) {
435 case MMC_RSP_NONE:
436 tmp |= UNIPHIER_SD_CMD_RSP_NONE;
437 break;
438 case MMC_RSP_R1:
439 tmp |= UNIPHIER_SD_CMD_RSP_R1;
440 break;
441 case MMC_RSP_R1b:
442 tmp |= UNIPHIER_SD_CMD_RSP_R1B;
443 break;
444 case MMC_RSP_R2:
445 tmp |= UNIPHIER_SD_CMD_RSP_R2;
446 break;
447 case MMC_RSP_R3:
448 tmp |= UNIPHIER_SD_CMD_RSP_R3;
449 break;
450 default:
3937404f 451 dev_err(dev, "unknown response type\n");
a111bfbf
MY		 452 return -EINVAL;
453 }
454
3937404f 455 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
a111bfbf
MY		 456 cmd->cmdidx, tmp, cmd->cmdarg);
457 writel(tmp, priv->regbase + UNIPHIER_SD_CMD);
458
3937404f 459 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
a111bfbf
MY		 460 UNIPHIER_SD_INFO1_RSP);
461 if (ret)
462 return ret;
463
464 if (cmd->resp_type & MMC_RSP_136) {
465 u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76);
466 u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54);
467 u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32);
468 u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10);
469
470 cmd->response[0] = (rsp_127_104 & 0xffffff) << 8 |
471 (rsp_103_72 & 0xff);
472 cmd->response[1] = (rsp_103_72 & 0xffffff) << 8 |
473 (rsp_71_40 & 0xff);
474 cmd->response[2] = (rsp_71_40 & 0xffffff) << 8 |
475 (rsp_39_8 & 0xff);
476 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
477 } else {
478 /* bit 39-8 */
479 cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10);
480 }
481
482 if (data) {
483 /* use DMA if the HW supports it and the buffer is aligned */
484 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL &&
485 uniphier_sd_addr_is_dmaable((long)data->src))
3937404f 486 ret = uniphier_sd_dma_xfer(dev, data);
a111bfbf 487 else
3937404f 488 ret = uniphier_sd_pio_xfer(dev, data);
a111bfbf 489
3937404f 490 ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
a111bfbf
MY		 491 UNIPHIER_SD_INFO1_CMP);
492 if (ret)
493 return ret;
494 }
495
496 return ret;
497}
498
8be12e28
MY		 499static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
500 struct mmc *mmc)
a111bfbf
MY		 501{
502 u32 val, tmp;
503
504 switch (mmc->bus_width) {
505 case 1:
506 val = UNIPHIER_SD_OPTION_WIDTH_1;
507 break;
508 case 4:
509 val = UNIPHIER_SD_OPTION_WIDTH_4;
510 break;
511 case 8:
512 val = UNIPHIER_SD_OPTION_WIDTH_8;
513 break;
514 default:
8be12e28 515 return -EINVAL;
a111bfbf
MY		 516 }
517
518 tmp = readl(priv->regbase + UNIPHIER_SD_OPTION);
519 tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
520 tmp |= val;
521 writel(tmp, priv->regbase + UNIPHIER_SD_OPTION);
8be12e28
MY		 522
523 return 0;
a111bfbf
MY		 524}
525
526static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
527 struct mmc *mmc)
528{
529 u32 tmp;
530
531 tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE);
532 if (mmc->ddr_mode)
533 tmp |= UNIPHIER_SD_IF_MODE_DDR;
534 else
535 tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
536 writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE);
537}
538
539static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
540 struct mmc *mmc)
541{
542 unsigned int divisor;
543 u32 val, tmp;
544
545 if (!mmc->clock)
546 return;
547
548 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
549
550 if (divisor <= 1)
551 val = UNIPHIER_SD_CLKCTL_DIV1;
552 else if (divisor <= 2)
553 val = UNIPHIER_SD_CLKCTL_DIV2;
554 else if (divisor <= 4)
555 val = UNIPHIER_SD_CLKCTL_DIV4;
556 else if (divisor <= 8)
557 val = UNIPHIER_SD_CLKCTL_DIV8;
558 else if (divisor <= 16)
559 val = UNIPHIER_SD_CLKCTL_DIV16;
560 else if (divisor <= 32)
561 val = UNIPHIER_SD_CLKCTL_DIV32;
562 else if (divisor <= 64)
563 val = UNIPHIER_SD_CLKCTL_DIV64;
564 else if (divisor <= 128)
565 val = UNIPHIER_SD_CLKCTL_DIV128;
566 else if (divisor <= 256)
567 val = UNIPHIER_SD_CLKCTL_DIV256;
568 else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024))
569 val = UNIPHIER_SD_CLKCTL_DIV512;
570 else
571 val = UNIPHIER_SD_CLKCTL_DIV1024;
572
573 tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL);
574
575 /* stop the clock before changing its rate to avoid a glitch signal */
576 tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
577 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
578
579 tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
580 tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
581 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
582
583 tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
584 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
585}
586
3937404f 587static int uniphier_sd_set_ios(struct udevice *dev)
a111bfbf 588{
3937404f
MY		 589 struct uniphier_sd_priv *priv = dev_get_priv(dev);
590 struct mmc *mmc = mmc_get_mmc_dev(dev);
8be12e28 591 int ret;
a111bfbf 592
3937404f 593 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
a111bfbf
MY		 594 mmc->clock, mmc->ddr_mode, mmc->bus_width);
595
8be12e28
MY		 596 ret = uniphier_sd_set_bus_width(priv, mmc);
597 if (ret)
598 return ret;
a111bfbf
MY		 599 uniphier_sd_set_ddr_mode(priv, mmc);
600 uniphier_sd_set_clk_rate(priv, mmc);
601
602 udelay(1000);
3937404f
MY		 603
604 return 0;
a111bfbf
MY		 605}
606
4eb00846
MY		 607static int uniphier_sd_get_cd(struct udevice *dev)
608{
609 struct uniphier_sd_priv *priv = dev_get_priv(dev);
610
611 if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
612 return 1;
613
614 return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) &
615 UNIPHIER_SD_INFO1_CD);
616}
617
618static const struct dm_mmc_ops uniphier_sd_ops = {
619 .send_cmd = uniphier_sd_send_cmd,
620 .set_ios = uniphier_sd_set_ios,
621 .get_cd = uniphier_sd_get_cd,
622};
623
624static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
a111bfbf 625{
a111bfbf
MY		 626 u32 tmp;
627
628 /* soft reset of the host */
629 tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST);
630 tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
631 writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
632 tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
633 writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
634
635 /* FIXME: implement eMMC hw_reset */
636
637 writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP);
638
639 /*
640 * Connected to 32bit AXI.
641 * This register dropped backward compatibility at version 0x10.
642 * Write an appropriate value depending on the IP version.
643 */
644 writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000,
645 priv->regbase + UNIPHIER_SD_HOST_MODE);
646
647 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
648 tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
649 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
650 writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
651 }
a111bfbf
MY		 652}
653
4a70d262 654static int uniphier_sd_probe(struct udevice *dev)
a111bfbf
MY		 655{
656 struct uniphier_sd_priv *priv = dev_get_priv(dev);
657 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
658 fdt_addr_t base;
135aa950 659 struct clk clk;
a111bfbf
MY		 660 int ret;
661
4f80501b
MY		 662 base = dev_get_addr(dev);
663 if (base == FDT_ADDR_T_NONE)
664 return -EINVAL;
665
4e3d8406 666 priv->regbase = devm_ioremap(dev, base, SZ_2K);
a111bfbf
MY		 667 if (!priv->regbase)
668 return -ENOMEM;
669
135aa950
SW		 670 ret = clk_get_by_index(dev, 0, &clk);
671 if (ret < 0) {
a111bfbf 672 dev_err(dev, "failed to get host clock\n");
135aa950 673 return ret;
a111bfbf
MY		 674 }
675
676 /* set to max rate */
135aa950 677 priv->mclk = clk_set_rate(&clk, ULONG_MAX);
a111bfbf
MY		 678 if (IS_ERR_VALUE(priv->mclk)) {
679 dev_err(dev, "failed to set rate for host clock\n");
135aa950 680 clk_free(&clk);
a111bfbf
MY		 681 return priv->mclk;
682 }
683
135aa950
SW		 684 ret = clk_enable(&clk);
685 clk_free(&clk);
a111bfbf
MY		 686 if (ret) {
687 dev_err(dev, "failed to enable host clock\n");
688 return ret;
689 }
690
691 priv->cfg.name = dev->name;
a111bfbf
MY		 692 priv->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
693
694 switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
695 case 8:
696 priv->cfg.host_caps |= MMC_MODE_8BIT;
697 break;
698 case 4:
699 priv->cfg.host_caps |= MMC_MODE_4BIT;
700 break;
701 case 1:
702 break;
703 default:
704 dev_err(dev, "Invalid \"bus-width\" value\n");
705 return -EINVAL;
706 }
707
708 if (fdt_get_property(gd->fdt_blob, dev->of_offset, "non-removable",
709 NULL))
710 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
711
712 priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) &
713 UNIPHIER_SD_VERSION_IP;
714 dev_dbg(dev, "version %x\n", priv->version);
715 if (priv->version >= 0x10) {
716 priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
717 priv->caps |= UNIPHIER_SD_CAP_DIV1024;
718 }
719
4eb00846 720 uniphier_sd_host_init(priv);
3937404f 721
a111bfbf
MY		 722 priv->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
723 priv->cfg.f_min = priv->mclk /
724 (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
725 priv->cfg.f_max = priv->mclk;
726 priv->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
727
728 priv->mmc = mmc_create(&priv->cfg, priv);
729 if (!priv->mmc)
730 return -EIO;
731
732 upriv->mmc = priv->mmc;
cffe5d86 733 priv->mmc->dev = dev;
a111bfbf
MY		 734
735 return 0;
736}
737
4a70d262 738static int uniphier_sd_remove(struct udevice *dev)
a111bfbf
MY		 739{
740 struct uniphier_sd_priv *priv = dev_get_priv(dev);
741
a111bfbf
MY		 742 mmc_destroy(priv->mmc);
743
744 return 0;
745}
746
747static const struct udevice_id uniphier_sd_match[] = {
748 { .compatible = "socionext,uniphier-sdhc" },
749 { /* sentinel */ }
750};
751
752U_BOOT_DRIVER(uniphier_mmc) = {
753 .name = "uniphier-mmc",
754 .id = UCLASS_MMC,
755 .of_match = uniphier_sd_match,
756 .probe = uniphier_sd_probe,
757 .remove = uniphier_sd_remove,
758 .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),
3937404f 759 .ops = &uniphier_sd_ops,
a111bfbf 760};
"Das U-Boot" Source Tree