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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / drivers / mtd / cfi_flash.c
CommitLineData
5653fc33 1/*
bf9e3b38 2 * (C) Copyright 2002-2004
5653fc33
WD		 3 * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
4 *
5 * Copyright (C) 2003 Arabella Software Ltd.
6 * Yuli Barcohen <yuli@arabellasw.com>
5653fc33 7 *
bf9e3b38
WD		 8 * Copyright (C) 2004
9 * Ed Okerson
260421a2
SR		 10 *
11 * Copyright (C) 2006
12 * Tolunay Orkun <listmember@orkun.us>
bf9e3b38 13 *
5653fc33
WD		 14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 *
5653fc33
WD		 32 */
33
34/* The DEBUG define must be before common to enable debugging */
2d1a537d
WD		 35/* #define DEBUG */
36
5653fc33
WD		 37#include <common.h>
38#include <asm/processor.h>
3a197b2f 39#include <asm/io.h>
4c0d4c3b 40#include <asm/byteorder.h>
2a8af187 41#include <environment.h>
028ab6b5 42
5653fc33 43/*
7e5b9b47
HS		 44 * This file implements a Common Flash Interface (CFI) driver for
45 * U-Boot.
46 *
47 * The width of the port and the width of the chips are determined at
48 * initialization. These widths are used to calculate the address for
49 * access CFI data structures.
5653fc33
WD		 50 *
51 * References
52 * JEDEC Standard JESD68 - Common Flash Interface (CFI)
53 * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
54 * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
55 * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
260421a2
SR		 56 * AMD CFI Specification, Release 2.0 December 1, 2001
57 * AMD/Spansion Application Note: Migration from Single-byte to Three-byte
58 * Device IDs, Publication Number 25538 Revision A, November 8, 2001
5653fc33 59 *
6d0f6bcf 60 * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
d0b6e140 61 * reading and writing ... (yes there is such a Hardware).
5653fc33
WD		 62 */
63
6d0f6bcf
JCPV		 64#ifndef CONFIG_SYS_FLASH_BANKS_LIST
65#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
bf9e3b38
WD		 66#endif
67
5653fc33
WD		 68#define FLASH_CMD_CFI 0x98
69#define FLASH_CMD_READ_ID 0x90
70#define FLASH_CMD_RESET 0xff
71#define FLASH_CMD_BLOCK_ERASE 0x20
72#define FLASH_CMD_ERASE_CONFIRM 0xD0
73#define FLASH_CMD_WRITE 0x40
74#define FLASH_CMD_PROTECT 0x60
75#define FLASH_CMD_PROTECT_SET 0x01
76#define FLASH_CMD_PROTECT_CLEAR 0xD0
77#define FLASH_CMD_CLEAR_STATUS 0x50
9c048b52 78#define FLASH_CMD_READ_STATUS 0x70
bf9e3b38 79#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
9c048b52 80#define FLASH_CMD_WRITE_BUFFER_PROG 0xE9
bf9e3b38 81#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
5653fc33
WD		 82
83#define FLASH_STATUS_DONE 0x80
84#define FLASH_STATUS_ESS 0x40
85#define FLASH_STATUS_ECLBS 0x20
86#define FLASH_STATUS_PSLBS 0x10
87#define FLASH_STATUS_VPENS 0x08
88#define FLASH_STATUS_PSS 0x04
89#define FLASH_STATUS_DPS 0x02
90#define FLASH_STATUS_R 0x01
91#define FLASH_STATUS_PROTECT 0x01
92
93#define AMD_CMD_RESET 0xF0
94#define AMD_CMD_WRITE 0xA0
95#define AMD_CMD_ERASE_START 0x80
96#define AMD_CMD_ERASE_SECTOR 0x30
855a496f
WD		 97#define AMD_CMD_UNLOCK_START 0xAA
98#define AMD_CMD_UNLOCK_ACK 0x55
79b4cda0
SR		 99#define AMD_CMD_WRITE_TO_BUFFER 0x25
100#define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29
5653fc33
WD		 101
102#define AMD_STATUS_TOGGLE 0x40
103#define AMD_STATUS_ERROR 0x20
79b4cda0 104
bc9019e1
RC		 105#define ATM_CMD_UNLOCK_SECT 0x70
106#define ATM_CMD_SOFTLOCK_START 0x80
107#define ATM_CMD_LOCK_SECT 0x40
108
260421a2
SR		 109#define FLASH_OFFSET_MANUFACTURER_ID 0x00
110#define FLASH_OFFSET_DEVICE_ID 0x01
111#define FLASH_OFFSET_DEVICE_ID2 0x0E
112#define FLASH_OFFSET_DEVICE_ID3 0x0F
5653fc33 113#define FLASH_OFFSET_CFI 0x55
92eb729b 114#define FLASH_OFFSET_CFI_ALT 0x555
5653fc33 115#define FLASH_OFFSET_CFI_RESP 0x10
bf9e3b38 116#define FLASH_OFFSET_PRIMARY_VENDOR 0x13
7e5b9b47
HS		 117/* extended query table primary address */
118#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15
5653fc33 119#define FLASH_OFFSET_WTOUT 0x1F
bf9e3b38 120#define FLASH_OFFSET_WBTOUT 0x20
5653fc33 121#define FLASH_OFFSET_ETOUT 0x21
bf9e3b38 122#define FLASH_OFFSET_CETOUT 0x22
5653fc33 123#define FLASH_OFFSET_WMAX_TOUT 0x23
bf9e3b38 124#define FLASH_OFFSET_WBMAX_TOUT 0x24
5653fc33 125#define FLASH_OFFSET_EMAX_TOUT 0x25
bf9e3b38 126#define FLASH_OFFSET_CEMAX_TOUT 0x26
5653fc33 127#define FLASH_OFFSET_SIZE 0x27
bf9e3b38
WD		 128#define FLASH_OFFSET_INTERFACE 0x28
129#define FLASH_OFFSET_BUFFER_SIZE 0x2A
5653fc33
WD		 130#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
131#define FLASH_OFFSET_ERASE_REGIONS 0x2D
132#define FLASH_OFFSET_PROTECT 0x02
bf9e3b38
WD		 133#define FLASH_OFFSET_USER_PROTECTION 0x85
134#define FLASH_OFFSET_INTEL_PROTECTION 0x81
5653fc33 135
260421a2
SR		 136#define CFI_CMDSET_NONE 0
137#define CFI_CMDSET_INTEL_EXTENDED 1
138#define CFI_CMDSET_AMD_STANDARD 2
139#define CFI_CMDSET_INTEL_STANDARD 3
140#define CFI_CMDSET_AMD_EXTENDED 4
141#define CFI_CMDSET_MITSU_STANDARD 256
142#define CFI_CMDSET_MITSU_EXTENDED 257
143#define CFI_CMDSET_SST 258
9c048b52 144#define CFI_CMDSET_INTEL_PROG_REGIONS 512
5653fc33 145
6d0f6bcf 146#ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */
f7d1572b 147# undef FLASH_CMD_RESET
260421a2 148# define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */
f7d1572b
WD		 149#endif
150
5653fc33
WD		 151typedef union {
152 unsigned char c;
153 unsigned short w;
154 unsigned long l;
155 unsigned long long ll;
156} cfiword_t;
157
260421a2 158#define NUM_ERASE_REGIONS 4 /* max. number of erase regions */
5653fc33 159
7e5b9b47 160static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT };
92eb729b 161
6d0f6bcf
JCPV		 162/* use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined */
163#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
164# define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT
e6f2e902 165#else
6d0f6bcf 166# define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS
e6f2e902 167#endif
5653fc33 168
2a112b23
WD		 169flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */
170
79b4cda0
SR		 171/*
172 * Check if chip width is defined. If not, start detecting with 8bit.
173 */
6d0f6bcf
JCPV		 174#ifndef CONFIG_SYS_FLASH_CFI_WIDTH
175#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
79b4cda0
SR		 176#endif
177
be60a902 178typedef unsigned long flash_sect_t;
5653fc33 179
e23741f4
HS		 180/* CFI standard query structure */
181struct cfi_qry {
182 u8 qry[3];
183 u16 p_id;
184 u16 p_adr;
185 u16 a_id;
186 u16 a_adr;
187 u8 vcc_min;
188 u8 vcc_max;
189 u8 vpp_min;
190 u8 vpp_max;
191 u8 word_write_timeout_typ;
192 u8 buf_write_timeout_typ;
193 u8 block_erase_timeout_typ;
194 u8 chip_erase_timeout_typ;
195 u8 word_write_timeout_max;
196 u8 buf_write_timeout_max;
197 u8 block_erase_timeout_max;
198 u8 chip_erase_timeout_max;
199 u8 dev_size;
200 u16 interface_desc;
201 u16 max_buf_write_size;
202 u8 num_erase_regions;
203 u32 erase_region_info[NUM_ERASE_REGIONS];
204} __attribute__((packed));
205
206struct cfi_pri_hdr {
207 u8 pri[3];
208 u8 major_version;
209 u8 minor_version;
210} __attribute__((packed));
211
cdbaefb5
HS		 212static void flash_write8(u8 value, void *addr)
213{
214 __raw_writeb(value, addr);
215}
216
217static void flash_write16(u16 value, void *addr)
218{
219 __raw_writew(value, addr);
220}
221
222static void flash_write32(u32 value, void *addr)
223{
224 __raw_writel(value, addr);
225}
226
227static void flash_write64(u64 value, void *addr)
228{
229 /* No architectures currently implement __raw_writeq() */
230 *(volatile u64 *)addr = value;
231}
232
233static u8 flash_read8(void *addr)
234{
235 return __raw_readb(addr);
236}
237
238static u16 flash_read16(void *addr)
239{
240 return __raw_readw(addr);
241}
242
243static u32 flash_read32(void *addr)
244{
245 return __raw_readl(addr);
246}
247
97bf85d7 248static u64 __flash_read64(void *addr)
cdbaefb5
HS		 249{
250 /* No architectures currently implement __raw_readq() */
251 return *(volatile u64 *)addr;
252}
253
97bf85d7
DH		 254u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64")));
255
5653fc33 256/*-----------------------------------------------------------------------
5653fc33 257 */
6d0f6bcf 258#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
be60a902
HS		 259static flash_info_t *flash_get_info(ulong base)
260{
261 int i;
262 flash_info_t * info = 0;
5653fc33 263
6d0f6bcf 264 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
be60a902
HS		 265 info = & flash_info[i];
266 if (info->size && info->start[0] <= base &&
267 base <= info->start[0] + info->size - 1)
268 break;
269 }
5653fc33 270
6d0f6bcf 271 return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
be60a902 272}
5653fc33
WD		 273#endif
274
12d30aa7
HS		 275unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect)
276{
277 if (sect != (info->sector_count - 1))
278 return info->start[sect + 1] - info->start[sect];
279 else
280 return info->start[0] + info->size - info->start[sect];
281}
282
bf9e3b38
WD		 283/*-----------------------------------------------------------------------
284 * create an address based on the offset and the port width
285 */
12d30aa7
HS		 286static inline void *
287flash_map (flash_info_t * info, flash_sect_t sect, uint offset)
bf9e3b38 288{
12d30aa7
HS		 289 unsigned int byte_offset = offset * info->portwidth;
290
291 return map_physmem(info->start[sect] + byte_offset,
292 flash_sector_size(info, sect) - byte_offset,
293 MAP_NOCACHE);
294}
295
296static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
297 unsigned int offset, void *addr)
298{
299 unsigned int byte_offset = offset * info->portwidth;
300
301 unmap_physmem(addr, flash_sector_size(info, sect) - byte_offset);
bf9e3b38
WD		 302}
303
be60a902
HS		 304/*-----------------------------------------------------------------------
305 * make a proper sized command based on the port and chip widths
306 */
7288f972 307static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
be60a902
HS		 308{
309 int i;
93c56f21
VL		 310 int cword_offset;
311 int cp_offset;
6d0f6bcf 312#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
340ccb26
SS		 313 u32 cmd_le = cpu_to_le32(cmd);
314#endif
93c56f21 315 uchar val;
be60a902
HS		 316 uchar *cp = (uchar *) cmdbuf;
317
93c56f21
VL		 318 for (i = info->portwidth; i > 0; i--){
319 cword_offset = (info->portwidth-i)%info->chipwidth;
6d0f6bcf 320#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
93c56f21 321 cp_offset = info->portwidth - i;
340ccb26 322 val = *((uchar*)&cmd_le + cword_offset);
be60a902 323#else
93c56f21 324 cp_offset = i - 1;
7288f972 325 val = *((uchar*)&cmd + sizeof(u32) - cword_offset - 1);
be60a902 326#endif
7288f972 327 cp[cp_offset] = (cword_offset >= sizeof(u32)) ? 0x00 : val;
93c56f21 328 }
be60a902
HS		 329}
330
5653fc33 331#ifdef DEBUG
bf9e3b38
WD		 332/*-----------------------------------------------------------------------
333 * Debug support
334 */
3055793b 335static void print_longlong (char *str, unsigned long long data)
5653fc33
WD		 336{
337 int i;
338 char *cp;
bf9e3b38
WD		 339
340 cp = (unsigned char *) &data;
341 for (i = 0; i < 8; i++)
342 sprintf (&str[i * 2], "%2.2x", *cp++);
343}
be60a902 344
e23741f4 345static void flash_printqry (struct cfi_qry *qry)
bf9e3b38 346{
e23741f4 347 u8 *p = (u8 *)qry;
bf9e3b38
WD		 348 int x, y;
349
e23741f4
HS		 350 for (x = 0; x < sizeof(struct cfi_qry); x += 16) {
351 debug("%02x : ", x);
352 for (y = 0; y < 16; y++)
353 debug("%2.2x ", p[x + y]);
354 debug(" ");
bf9e3b38 355 for (y = 0; y < 16; y++) {
e23741f4
HS		 356 unsigned char c = p[x + y];
357 if (c >= 0x20 && c <= 0x7e)
358 debug("%c", c);
359 else
360 debug(".");
bf9e3b38 361 }
e23741f4 362 debug("\n");
bf9e3b38 363 }
5653fc33
WD		 364}
365#endif
366
367
5653fc33
WD		 368/*-----------------------------------------------------------------------
369 * read a character at a port width address
370 */
3055793b 371static inline uchar flash_read_uchar (flash_info_t * info, uint offset)
5653fc33
WD		 372{
373 uchar *cp;
12d30aa7 374 uchar retval;
bf9e3b38 375
12d30aa7 376 cp = flash_map (info, 0, offset);
6d0f6bcf 377#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
12d30aa7 378 retval = flash_read8(cp);
bf9e3b38 379#else
12d30aa7 380 retval = flash_read8(cp + info->portwidth - 1);
bf9e3b38 381#endif
12d30aa7
HS		 382 flash_unmap (info, 0, offset, cp);
383 return retval;
5653fc33
WD		 384}
385
90447ecb
TK		 386/*-----------------------------------------------------------------------
387 * read a word at a port width address, assume 16bit bus
388 */
389static inline ushort flash_read_word (flash_info_t * info, uint offset)
390{
391 ushort *addr, retval;
392
393 addr = flash_map (info, 0, offset);
394 retval = flash_read16 (addr);
395 flash_unmap (info, 0, offset, addr);
396 return retval;
397}
398
399
5653fc33 400/*-----------------------------------------------------------------------
260421a2 401 * read a long word by picking the least significant byte of each maximum
5653fc33
WD		 402 * port size word. Swap for ppc format.
403 */
3055793b
HS		 404static ulong flash_read_long (flash_info_t * info, flash_sect_t sect,
405 uint offset)
5653fc33 406{
bf9e3b38
WD		 407 uchar *addr;
408 ulong retval;
409
410#ifdef DEBUG
411 int x;
412#endif
12d30aa7 413 addr = flash_map (info, sect, offset);
5653fc33 414
bf9e3b38
WD		 415#ifdef DEBUG
416 debug ("long addr is at %p info->portwidth = %d\n", addr,
417 info->portwidth);
418 for (x = 0; x < 4 * info->portwidth; x++) {
12d30aa7 419 debug ("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
bf9e3b38
WD		 420 }
421#endif
6d0f6bcf 422#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
12d30aa7
HS		 423 retval = ((flash_read8(addr) << 16) |
424 (flash_read8(addr + info->portwidth) << 24) |
425 (flash_read8(addr + 2 * info->portwidth)) |
426 (flash_read8(addr + 3 * info->portwidth) << 8));
bf9e3b38 427#else
12d30aa7
HS		 428 retval = ((flash_read8(addr + 2 * info->portwidth - 1) << 24) |
429 (flash_read8(addr + info->portwidth - 1) << 16) |
430 (flash_read8(addr + 4 * info->portwidth - 1) << 8) |
431 (flash_read8(addr + 3 * info->portwidth - 1)));
bf9e3b38 432#endif
12d30aa7
HS		 433 flash_unmap(info, sect, offset, addr);
434
bf9e3b38 435 return retval;
5653fc33
WD		 436}
437
be60a902
HS		 438/*
439 * Write a proper sized command to the correct address
81b20ccc 440 */
be60a902 441static void flash_write_cmd (flash_info_t * info, flash_sect_t sect,
7288f972 442 uint offset, u32 cmd)
81b20ccc 443{
7e5b9b47 444
cdbaefb5 445 void *addr;
be60a902 446 cfiword_t cword;
81b20ccc 447
12d30aa7 448 addr = flash_map (info, sect, offset);
be60a902
HS		 449 flash_make_cmd (info, cmd, &cword);
450 switch (info->portwidth) {
451 case FLASH_CFI_8BIT:
cdbaefb5 452 debug ("fwc addr %p cmd %x %x 8bit x %d bit\n", addr, cmd,
be60a902 453 cword.c, info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 454 flash_write8(cword.c, addr);
be60a902
HS		 455 break;
456 case FLASH_CFI_16BIT:
cdbaefb5 457 debug ("fwc addr %p cmd %x %4.4x 16bit x %d bit\n", addr,
be60a902
HS		 458 cmd, cword.w,
459 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 460 flash_write16(cword.w, addr);
be60a902
HS		 461 break;
462 case FLASH_CFI_32BIT:
cdbaefb5 463 debug ("fwc addr %p cmd %x %8.8lx 32bit x %d bit\n", addr,
be60a902
HS		 464 cmd, cword.l,
465 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
cdbaefb5 466 flash_write32(cword.l, addr);
be60a902
HS		 467 break;
468 case FLASH_CFI_64BIT:
469#ifdef DEBUG
470 {
471 char str[20];
7e5b9b47 472
be60a902
HS		 473 print_longlong (str, cword.ll);
474
475 debug ("fwrite addr %p cmd %x %s 64 bit x %d bit\n",
cdbaefb5 476 addr, cmd, str,
be60a902 477 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
81b20ccc 478 }
be60a902 479#endif
cdbaefb5 480 flash_write64(cword.ll, addr);
be60a902 481 break;
81b20ccc 482 }
be60a902
HS		 483
484 /* Ensure all the instructions are fully finished */
485 sync();
12d30aa7
HS		 486
487 flash_unmap(info, sect, offset, addr);
81b20ccc 488}
be60a902
HS		 489
490static void flash_unlock_seq (flash_info_t * info, flash_sect_t sect)
81b20ccc 491{
be60a902
HS		 492 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_UNLOCK_START);
493 flash_write_cmd (info, sect, info->addr_unlock2, AMD_CMD_UNLOCK_ACK);
81b20ccc 494}
81b20ccc 495
5653fc33
WD		 496/*-----------------------------------------------------------------------
497 */
be60a902
HS		 498static int flash_isequal (flash_info_t * info, flash_sect_t sect,
499 uint offset, uchar cmd)
5653fc33 500{
cdbaefb5 501 void *addr;
be60a902
HS		 502 cfiword_t cword;
503 int retval;
5653fc33 504
12d30aa7 505 addr = flash_map (info, sect, offset);
be60a902 506 flash_make_cmd (info, cmd, &cword);
2662b40c 507
cdbaefb5 508 debug ("is= cmd %x(%c) addr %p ", cmd, cmd, addr);
be60a902
HS		 509 switch (info->portwidth) {
510 case FLASH_CFI_8BIT:
cdbaefb5
HS		 511 debug ("is= %x %x\n", flash_read8(addr), cword.c);
512 retval = (flash_read8(addr) == cword.c);
be60a902
HS		 513 break;
514 case FLASH_CFI_16BIT:
cdbaefb5
HS		 515 debug ("is= %4.4x %4.4x\n", flash_read16(addr), cword.w);
516 retval = (flash_read16(addr) == cword.w);
be60a902
HS		 517 break;
518 case FLASH_CFI_32BIT:
52514699 519 debug ("is= %8.8x %8.8lx\n", flash_read32(addr), cword.l);
cdbaefb5 520 retval = (flash_read32(addr) == cword.l);
be60a902
HS		 521 break;
522 case FLASH_CFI_64BIT:
523#ifdef DEBUG
524 {
525 char str1[20];
526 char str2[20];
81b20ccc 527
cdbaefb5 528 print_longlong (str1, flash_read64(addr));
be60a902
HS		 529 print_longlong (str2, cword.ll);
530 debug ("is= %s %s\n", str1, str2);
5653fc33 531 }
be60a902 532#endif
cdbaefb5 533 retval = (flash_read64(addr) == cword.ll);
be60a902
HS		 534 break;
535 default:
536 retval = 0;
537 break;
538 }
12d30aa7
HS		 539 flash_unmap(info, sect, offset, addr);
540
be60a902
HS		 541 return retval;
542}
79b4cda0 543
be60a902
HS		 544/*-----------------------------------------------------------------------
545 */
546static int flash_isset (flash_info_t * info, flash_sect_t sect,
547 uint offset, uchar cmd)
548{
cdbaefb5 549 void *addr;
be60a902
HS		 550 cfiword_t cword;
551 int retval;
2662b40c 552
12d30aa7 553 addr = flash_map (info, sect, offset);
be60a902
HS		 554 flash_make_cmd (info, cmd, &cword);
555 switch (info->portwidth) {
556 case FLASH_CFI_8BIT:
cdbaefb5 557 retval = ((flash_read8(addr) & cword.c) == cword.c);
be60a902
HS		 558 break;
559 case FLASH_CFI_16BIT:
cdbaefb5 560 retval = ((flash_read16(addr) & cword.w) == cword.w);
be60a902
HS		 561 break;
562 case FLASH_CFI_32BIT:
47cc23cb 563 retval = ((flash_read32(addr) & cword.l) == cword.l);
be60a902
HS		 564 break;
565 case FLASH_CFI_64BIT:
cdbaefb5 566 retval = ((flash_read64(addr) & cword.ll) == cword.ll);
be60a902
HS		 567 break;
568 default:
569 retval = 0;
570 break;
571 }
12d30aa7
HS		 572 flash_unmap(info, sect, offset, addr);
573
be60a902
HS		 574 return retval;
575}
2662b40c 576
be60a902
HS		 577/*-----------------------------------------------------------------------
578 */
579static int flash_toggle (flash_info_t * info, flash_sect_t sect,
580 uint offset, uchar cmd)
581{
cdbaefb5 582 void *addr;
be60a902
HS		 583 cfiword_t cword;
584 int retval;
656658dd 585
12d30aa7 586 addr = flash_map (info, sect, offset);
be60a902
HS		 587 flash_make_cmd (info, cmd, &cword);
588 switch (info->portwidth) {
589 case FLASH_CFI_8BIT:
fb8c061e 590 retval = flash_read8(addr) != flash_read8(addr);
be60a902
HS		 591 break;
592 case FLASH_CFI_16BIT:
fb8c061e 593 retval = flash_read16(addr) != flash_read16(addr);
be60a902
HS		 594 break;
595 case FLASH_CFI_32BIT:
fb8c061e 596 retval = flash_read32(addr) != flash_read32(addr);
be60a902
HS		 597 break;
598 case FLASH_CFI_64BIT:
fb8c061e 599 retval = flash_read64(addr) != flash_read64(addr);
be60a902
HS		 600 break;
601 default:
602 retval = 0;
603 break;
604 }
12d30aa7
HS		 605 flash_unmap(info, sect, offset, addr);
606
be60a902 607 return retval;
5653fc33
WD		 608}
609
be60a902
HS		 610/*
611 * flash_is_busy - check to see if the flash is busy
612 *
613 * This routine checks the status of the chip and returns true if the
614 * chip is busy.
7680c140 615 */
be60a902 616static int flash_is_busy (flash_info_t * info, flash_sect_t sect)
7680c140 617{
be60a902 618 int retval;
7680c140 619
be60a902 620 switch (info->vendor) {
9c048b52 621 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 622 case CFI_CMDSET_INTEL_STANDARD:
623 case CFI_CMDSET_INTEL_EXTENDED:
624 retval = !flash_isset (info, sect, 0, FLASH_STATUS_DONE);
625 break;
626 case CFI_CMDSET_AMD_STANDARD:
627 case CFI_CMDSET_AMD_EXTENDED:
628#ifdef CONFIG_FLASH_CFI_LEGACY
629 case CFI_CMDSET_AMD_LEGACY:
630#endif
631 retval = flash_toggle (info, sect, 0, AMD_STATUS_TOGGLE);
632 break;
633 default:
634 retval = 0;
7680c140 635 }
be60a902
HS		 636 debug ("flash_is_busy: %d\n", retval);
637 return retval;
7680c140
WD		 638}
639
5653fc33 640/*-----------------------------------------------------------------------
be60a902
HS		 641 * wait for XSR.7 to be set. Time out with an error if it does not.
642 * This routine does not set the flash to read-array mode.
5653fc33 643 */
be60a902
HS		 644static int flash_status_check (flash_info_t * info, flash_sect_t sector,
645 ulong tout, char *prompt)
5653fc33 646{
be60a902 647 ulong start;
5653fc33 648
6d0f6bcf
JCPV		 649#if CONFIG_SYS_HZ != 1000
650 tout *= CONFIG_SYS_HZ/1000;
be60a902 651#endif
5653fc33 652
be60a902
HS		 653 /* Wait for command completion */
654 start = get_timer (0);
655 while (flash_is_busy (info, sector)) {
656 if (get_timer (start) > tout) {
657 printf ("Flash %s timeout at address %lx data %lx\n",
658 prompt, info->start[sector],
659 flash_read_long (info, sector, 0));
660 flash_write_cmd (info, sector, 0, info->cmd_reset);
661 return ERR_TIMOUT;
5653fc33 662 }
be60a902 663 udelay (1); /* also triggers watchdog */
5653fc33 664 }
be60a902
HS		 665 return ERR_OK;
666}
5653fc33 667
be60a902
HS		 668/*-----------------------------------------------------------------------
669 * Wait for XSR.7 to be set, if it times out print an error, otherwise
670 * do a full status check.
671 *
672 * This routine sets the flash to read-array mode.
673 */
674static int flash_full_status_check (flash_info_t * info, flash_sect_t sector,
675 ulong tout, char *prompt)
676{
677 int retcode;
5653fc33 678
be60a902
HS		 679 retcode = flash_status_check (info, sector, tout, prompt);
680 switch (info->vendor) {
9c048b52 681 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 682 case CFI_CMDSET_INTEL_EXTENDED:
683 case CFI_CMDSET_INTEL_STANDARD:
0d01f66d 684 if ((retcode != ERR_OK)
be60a902
HS		 685 && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
686 retcode = ERR_INVAL;
687 printf ("Flash %s error at address %lx\n", prompt,
688 info->start[sector]);
689 if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS |
690 FLASH_STATUS_PSLBS)) {
691 puts ("Command Sequence Error.\n");
692 } else if (flash_isset (info, sector, 0,
693 FLASH_STATUS_ECLBS)) {
694 puts ("Block Erase Error.\n");
695 retcode = ERR_NOT_ERASED;
696 } else if (flash_isset (info, sector, 0,
697 FLASH_STATUS_PSLBS)) {
698 puts ("Locking Error\n");
5653fc33 699 }
be60a902
HS		 700 if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
701 puts ("Block locked.\n");
702 retcode = ERR_PROTECTED;
703 }
704 if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
705 puts ("Vpp Low Error.\n");
5653fc33 706 }
be60a902
HS		 707 flash_write_cmd (info, sector, 0, info->cmd_reset);
708 break;
709 default:
710 break;
5653fc33 711 }
be60a902 712 return retcode;
5653fc33
WD		 713}
714
715/*-----------------------------------------------------------------------
716 */
be60a902 717static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
5653fc33 718{
6d0f6bcf 719#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 720 unsigned short w;
721 unsigned int l;
722 unsigned long long ll;
723#endif
5653fc33 724
be60a902
HS		 725 switch (info->portwidth) {
726 case FLASH_CFI_8BIT:
727 cword->c = c;
728 break;
729 case FLASH_CFI_16BIT:
6d0f6bcf 730#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 731 w = c;
732 w <<= 8;
733 cword->w = (cword->w >> 8) | w;
734#else
735 cword->w = (cword->w << 8) | c;
81b20ccc 736#endif
be60a902
HS		 737 break;
738 case FLASH_CFI_32BIT:
6d0f6bcf 739#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 740 l = c;
741 l <<= 24;
742 cword->l = (cword->l >> 8) | l;
743#else
744 cword->l = (cword->l << 8) | c;
745#endif
746 break;
747 case FLASH_CFI_64BIT:
6d0f6bcf 748#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
be60a902
HS		 749 ll = c;
750 ll <<= 56;
751 cword->ll = (cword->ll >> 8) | ll;
752#else
753 cword->ll = (cword->ll << 8) | c;
754#endif
755 break;
260421a2 756 }
be60a902 757}
5653fc33 758
be60a902
HS		 759/* loop through the sectors from the highest address when the passed
760 * address is greater or equal to the sector address we have a match
761 */
762static flash_sect_t find_sector (flash_info_t * info, ulong addr)
763{
764 flash_sect_t sector;
5653fc33 765
be60a902
HS		 766 for (sector = info->sector_count - 1; sector >= 0; sector--) {
767 if (addr >= info->start[sector])
768 break;
5653fc33 769 }
be60a902 770 return sector;
5653fc33
WD		 771}
772
773/*-----------------------------------------------------------------------
5653fc33 774 */
be60a902
HS		 775static int flash_write_cfiword (flash_info_t * info, ulong dest,
776 cfiword_t cword)
5653fc33 777{
cdbaefb5 778 void *dstaddr;
be60a902 779 int flag;
0d01f66d 780 flash_sect_t sect;
5653fc33 781
12d30aa7 782 dstaddr = map_physmem(dest, info->portwidth, MAP_NOCACHE);
5653fc33 783
be60a902
HS		 784 /* Check if Flash is (sufficiently) erased */
785 switch (info->portwidth) {
786 case FLASH_CFI_8BIT:
cdbaefb5 787 flag = ((flash_read8(dstaddr) & cword.c) == cword.c);
be60a902
HS		 788 break;
789 case FLASH_CFI_16BIT:
cdbaefb5 790 flag = ((flash_read16(dstaddr) & cword.w) == cword.w);
be60a902
HS		 791 break;
792 case FLASH_CFI_32BIT:
cdbaefb5 793 flag = ((flash_read32(dstaddr) & cword.l) == cword.l);
be60a902
HS		 794 break;
795 case FLASH_CFI_64BIT:
cdbaefb5 796 flag = ((flash_read64(dstaddr) & cword.ll) == cword.ll);
be60a902
HS		 797 break;
798 default:
12d30aa7
HS		 799 flag = 0;
800 break;
5653fc33 801 }
12d30aa7
HS		 802 if (!flag) {
803 unmap_physmem(dstaddr, info->portwidth);
0dc80e27 804 return ERR_NOT_ERASED;
12d30aa7 805 }
5653fc33 806
be60a902
HS		 807 /* Disable interrupts which might cause a timeout here */
808 flag = disable_interrupts ();
79b4cda0 809
be60a902 810 switch (info->vendor) {
9c048b52 811 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 812 case CFI_CMDSET_INTEL_EXTENDED:
813 case CFI_CMDSET_INTEL_STANDARD:
814 flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
815 flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
816 break;
817 case CFI_CMDSET_AMD_EXTENDED:
818 case CFI_CMDSET_AMD_STANDARD:
819#ifdef CONFIG_FLASH_CFI_LEGACY
820 case CFI_CMDSET_AMD_LEGACY:
821#endif
0d01f66d
ES		 822 sect = find_sector(info, dest);
823 flash_unlock_seq (info, sect);
824 flash_write_cmd (info, sect, info->addr_unlock1, AMD_CMD_WRITE);
be60a902 825 break;
5653fc33
WD		 826 }
827
be60a902
HS		 828 switch (info->portwidth) {
829 case FLASH_CFI_8BIT:
cdbaefb5 830 flash_write8(cword.c, dstaddr);
be60a902
HS		 831 break;
832 case FLASH_CFI_16BIT:
cdbaefb5 833 flash_write16(cword.w, dstaddr);
be60a902
HS		 834 break;
835 case FLASH_CFI_32BIT:
cdbaefb5 836 flash_write32(cword.l, dstaddr);
be60a902
HS		 837 break;
838 case FLASH_CFI_64BIT:
cdbaefb5 839 flash_write64(cword.ll, dstaddr);
be60a902 840 break;
5653fc33
WD		 841 }
842
be60a902
HS		 843 /* re-enable interrupts if necessary */
844 if (flag)
845 enable_interrupts ();
5653fc33 846
12d30aa7
HS		 847 unmap_physmem(dstaddr, info->portwidth);
848
be60a902
HS		 849 return flash_full_status_check (info, find_sector (info, dest),
850 info->write_tout, "write");
5653fc33
WD		 851}
852
6d0f6bcf 853#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
5653fc33 854
be60a902
HS		 855static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
856 int len)
5653fc33 857{
be60a902
HS		 858 flash_sect_t sector;
859 int cnt;
860 int retcode;
cdbaefb5 861 void *src = cp;
12d30aa7 862 void *dst = map_physmem(dest, len, MAP_NOCACHE);
0dc80e27
SR		 863 void *dst2 = dst;
864 int flag = 0;
96ef831f
GL		 865 uint offset = 0;
866 unsigned int shift;
9c048b52 867 uchar write_cmd;
cdbaefb5 868
0dc80e27
SR		 869 switch (info->portwidth) {
870 case FLASH_CFI_8BIT:
96ef831f 871 shift = 0;
0dc80e27
SR		 872 break;
873 case FLASH_CFI_16BIT:
96ef831f 874 shift = 1;
0dc80e27
SR		 875 break;
876 case FLASH_CFI_32BIT:
96ef831f 877 shift = 2;
0dc80e27
SR		 878 break;
879 case FLASH_CFI_64BIT:
96ef831f 880 shift = 3;
0dc80e27
SR		 881 break;
882 default:
883 retcode = ERR_INVAL;
884 goto out_unmap;
885 }
886
96ef831f
GL		 887 cnt = len >> shift;
888
0dc80e27
SR		 889 while ((cnt-- > 0) && (flag == 0)) {
890 switch (info->portwidth) {
891 case FLASH_CFI_8BIT:
892 flag = ((flash_read8(dst2) & flash_read8(src)) ==
893 flash_read8(src));
894 src += 1, dst2 += 1;
895 break;
896 case FLASH_CFI_16BIT:
897 flag = ((flash_read16(dst2) & flash_read16(src)) ==
898 flash_read16(src));
899 src += 2, dst2 += 2;
900 break;
901 case FLASH_CFI_32BIT:
902 flag = ((flash_read32(dst2) & flash_read32(src)) ==
903 flash_read32(src));
904 src += 4, dst2 += 4;
905 break;
906 case FLASH_CFI_64BIT:
907 flag = ((flash_read64(dst2) & flash_read64(src)) ==
908 flash_read64(src));
909 src += 8, dst2 += 8;
910 break;
911 }
912 }
913 if (!flag) {
914 retcode = ERR_NOT_ERASED;
915 goto out_unmap;
916 }
917
918 src = cp;
cdbaefb5 919 sector = find_sector (info, dest);
bf9e3b38
WD		 920
921 switch (info->vendor) {
9c048b52 922 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 923 case CFI_CMDSET_INTEL_STANDARD:
924 case CFI_CMDSET_INTEL_EXTENDED:
9c048b52
VL		 925 write_cmd = (info->vendor == CFI_CMDSET_INTEL_PROG_REGIONS) ?
926 FLASH_CMD_WRITE_BUFFER_PROG : FLASH_CMD_WRITE_TO_BUFFER;
be60a902 927 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
9c048b52
VL		 928 flash_write_cmd (info, sector, 0, FLASH_CMD_READ_STATUS);
929 flash_write_cmd (info, sector, 0, write_cmd);
be60a902
HS		 930 retcode = flash_status_check (info, sector,
931 info->buffer_write_tout,
932 "write to buffer");
933 if (retcode == ERR_OK) {
934 /* reduce the number of loops by the width of
935 * the port */
96ef831f 936 cnt = len >> shift;
93c56f21 937 flash_write_cmd (info, sector, 0, cnt - 1);
be60a902
HS		 938 while (cnt-- > 0) {
939 switch (info->portwidth) {
940 case FLASH_CFI_8BIT:
cdbaefb5
HS		 941 flash_write8(flash_read8(src), dst);
942 src += 1, dst += 1;
be60a902
HS		 943 break;
944 case FLASH_CFI_16BIT:
cdbaefb5
HS		 945 flash_write16(flash_read16(src), dst);
946 src += 2, dst += 2;
be60a902
HS		 947 break;
948 case FLASH_CFI_32BIT:
cdbaefb5
HS		 949 flash_write32(flash_read32(src), dst);
950 src += 4, dst += 4;
be60a902
HS		 951 break;
952 case FLASH_CFI_64BIT:
cdbaefb5
HS		 953 flash_write64(flash_read64(src), dst);
954 src += 8, dst += 8;
be60a902
HS		 955 break;
956 default:
12d30aa7
HS		 957 retcode = ERR_INVAL;
958 goto out_unmap;
be60a902
HS		 959 }
960 }
961 flash_write_cmd (info, sector, 0,
962 FLASH_CMD_WRITE_BUFFER_CONFIRM);
963 retcode = flash_full_status_check (
964 info, sector, info->buffer_write_tout,
965 "buffer write");
966 }
12d30aa7
HS		 967
968 break;
be60a902 969
5653fc33
WD		 970 case CFI_CMDSET_AMD_STANDARD:
971 case CFI_CMDSET_AMD_EXTENDED:
be60a902 972 flash_unlock_seq(info,0);
96ef831f
GL		 973
974#ifdef CONFIG_FLASH_SPANSION_S29WS_N
975 offset = ((unsigned long)dst - info->start[sector]) >> shift;
976#endif
977 flash_write_cmd(info, sector, offset, AMD_CMD_WRITE_TO_BUFFER);
978 cnt = len >> shift;
979 flash_write_cmd(info, sector, offset, (uchar)cnt - 1);
be60a902
HS		 980
981 switch (info->portwidth) {
982 case FLASH_CFI_8BIT:
cdbaefb5
HS		 983 while (cnt-- > 0) {
984 flash_write8(flash_read8(src), dst);
985 src += 1, dst += 1;
986 }
be60a902
HS		 987 break;
988 case FLASH_CFI_16BIT:
cdbaefb5
HS		 989 while (cnt-- > 0) {
990 flash_write16(flash_read16(src), dst);
991 src += 2, dst += 2;
992 }
be60a902
HS		 993 break;
994 case FLASH_CFI_32BIT:
cdbaefb5
HS		 995 while (cnt-- > 0) {
996 flash_write32(flash_read32(src), dst);
997 src += 4, dst += 4;
998 }
be60a902
HS		 999 break;
1000 case FLASH_CFI_64BIT:
cdbaefb5
HS		 1001 while (cnt-- > 0) {
1002 flash_write64(flash_read64(src), dst);
1003 src += 8, dst += 8;
1004 }
be60a902
HS		 1005 break;
1006 default:
12d30aa7
HS		 1007 retcode = ERR_INVAL;
1008 goto out_unmap;
be60a902
HS		 1009 }
1010
1011 flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM);
1012 retcode = flash_full_status_check (info, sector,
1013 info->buffer_write_tout,
1014 "buffer write");
12d30aa7 1015 break;
be60a902 1016
5653fc33 1017 default:
be60a902 1018 debug ("Unknown Command Set\n");
12d30aa7
HS		 1019 retcode = ERR_INVAL;
1020 break;
5653fc33 1021 }
12d30aa7
HS		 1022
1023out_unmap:
1024 unmap_physmem(dst, len);
1025 return retcode;
5653fc33 1026}
6d0f6bcf 1027#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
be60a902 1028
bf9e3b38 1029
5653fc33 1030/*-----------------------------------------------------------------------
5653fc33 1031 */
be60a902 1032int flash_erase (flash_info_t * info, int s_first, int s_last)
5653fc33 1033{
be60a902
HS		 1034 int rcode = 0;
1035 int prot;
1036 flash_sect_t sect;
5653fc33 1037
be60a902
HS		 1038 if (info->flash_id != FLASH_MAN_CFI) {
1039 puts ("Can't erase unknown flash type - aborted\n");
1040 return 1;
1041 }
1042 if ((s_first < 0) || (s_first > s_last)) {
1043 puts ("- no sectors to erase\n");
1044 return 1;
1045 }
2662b40c 1046
be60a902
HS		 1047 prot = 0;
1048 for (sect = s_first; sect <= s_last; ++sect) {
1049 if (info->protect[sect]) {
1050 prot++;
5653fc33
WD		 1051 }
1052 }
be60a902
HS		 1053 if (prot) {
1054 printf ("- Warning: %d protected sectors will not be erased!\n",
1055 prot);
1056 } else {
1057 putc ('\n');
1058 }
bf9e3b38 1059
bf9e3b38 1060
be60a902
HS		 1061 for (sect = s_first; sect <= s_last; sect++) {
1062 if (info->protect[sect] == 0) { /* not protected */
1063 switch (info->vendor) {
9c048b52 1064 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1065 case CFI_CMDSET_INTEL_STANDARD:
1066 case CFI_CMDSET_INTEL_EXTENDED:
1067 flash_write_cmd (info, sect, 0,
1068 FLASH_CMD_CLEAR_STATUS);
1069 flash_write_cmd (info, sect, 0,
1070 FLASH_CMD_BLOCK_ERASE);
1071 flash_write_cmd (info, sect, 0,
1072 FLASH_CMD_ERASE_CONFIRM);
1073 break;
1074 case CFI_CMDSET_AMD_STANDARD:
1075 case CFI_CMDSET_AMD_EXTENDED:
1076 flash_unlock_seq (info, sect);
1077 flash_write_cmd (info, sect,
1078 info->addr_unlock1,
1079 AMD_CMD_ERASE_START);
1080 flash_unlock_seq (info, sect);
1081 flash_write_cmd (info, sect, 0,
1082 AMD_CMD_ERASE_SECTOR);
1083 break;
1084#ifdef CONFIG_FLASH_CFI_LEGACY
1085 case CFI_CMDSET_AMD_LEGACY:
1086 flash_unlock_seq (info, 0);
1087 flash_write_cmd (info, 0, info->addr_unlock1,
1088 AMD_CMD_ERASE_START);
1089 flash_unlock_seq (info, 0);
1090 flash_write_cmd (info, sect, 0,
1091 AMD_CMD_ERASE_SECTOR);
1092 break;
1093#endif
1094 default:
1095 debug ("Unkown flash vendor %d\n",
1096 info->vendor);
1097 break;
bf9e3b38 1098 }
be60a902
HS		 1099
1100 if (flash_full_status_check
1101 (info, sect, info->erase_blk_tout, "erase")) {
1102 rcode = 1;
1103 } else
1104 putc ('.');
5653fc33 1105 }
5653fc33 1106 }
be60a902
HS		 1107 puts (" done\n");
1108 return rcode;
5653fc33 1109}
bf9e3b38 1110
5653fc33
WD		 1111/*-----------------------------------------------------------------------
1112 */
be60a902 1113void flash_print_info (flash_info_t * info)
5653fc33 1114{
be60a902 1115 int i;
4d13cbad 1116
be60a902
HS		 1117 if (info->flash_id != FLASH_MAN_CFI) {
1118 puts ("missing or unknown FLASH type\n");
1119 return;
1120 }
1121
1122 printf ("%s FLASH (%d x %d)",
1123 info->name,
1124 (info->portwidth << 3), (info->chipwidth << 3));
1125 if (info->size < 1024*1024)
1126 printf (" Size: %ld kB in %d Sectors\n",
1127 info->size >> 10, info->sector_count);
1128 else
1129 printf (" Size: %ld MB in %d Sectors\n",
1130 info->size >> 20, info->sector_count);
1131 printf (" ");
1132 switch (info->vendor) {
9c048b52
VL		 1133 case CFI_CMDSET_INTEL_PROG_REGIONS:
1134 printf ("Intel Prog Regions");
1135 break;
be60a902
HS		 1136 case CFI_CMDSET_INTEL_STANDARD:
1137 printf ("Intel Standard");
1138 break;
1139 case CFI_CMDSET_INTEL_EXTENDED:
1140 printf ("Intel Extended");
1141 break;
1142 case CFI_CMDSET_AMD_STANDARD:
1143 printf ("AMD Standard");
1144 break;
1145 case CFI_CMDSET_AMD_EXTENDED:
1146 printf ("AMD Extended");
1147 break;
1148#ifdef CONFIG_FLASH_CFI_LEGACY
1149 case CFI_CMDSET_AMD_LEGACY:
1150 printf ("AMD Legacy");
1151 break;
4d13cbad 1152#endif
be60a902
HS		 1153 default:
1154 printf ("Unknown (%d)", info->vendor);
1155 break;
1156 }
1157 printf (" command set, Manufacturer ID: 0x%02X, Device ID: 0x%02X",
1158 info->manufacturer_id, info->device_id);
1159 if (info->device_id == 0x7E) {
1160 printf("%04X", info->device_id2);
1161 }
1162 printf ("\n Erase timeout: %ld ms, write timeout: %ld ms\n",
1163 info->erase_blk_tout,
1164 info->write_tout);
1165 if (info->buffer_size > 1) {
1166 printf (" Buffer write timeout: %ld ms, "
1167 "buffer size: %d bytes\n",
1168 info->buffer_write_tout,
1169 info->buffer_size);
5653fc33 1170 }
5653fc33 1171
be60a902
HS		 1172 puts ("\n Sector Start Addresses:");
1173 for (i = 0; i < info->sector_count; ++i) {
1174 if ((i % 5) == 0)
1175 printf ("\n");
6d0f6bcf 1176#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
be60a902
HS		 1177 int k;
1178 int size;
1179 int erased;
1180 volatile unsigned long *flash;
5653fc33 1181
be60a902
HS		 1182 /*
1183 * Check if whole sector is erased
1184 */
12d30aa7 1185 size = flash_sector_size(info, i);
be60a902
HS		 1186 erased = 1;
1187 flash = (volatile unsigned long *) info->start[i];
1188 size = size >> 2; /* divide by 4 for longword access */
1189 for (k = 0; k < size; k++) {
1190 if (*flash++ != 0xffffffff) {
1191 erased = 0;
1192 break;
1193 }
1194 }
bf9e3b38 1195
be60a902
HS		 1196 /* print empty and read-only info */
1197 printf (" %08lX %c %s ",
1198 info->start[i],
1199 erased ? 'E' : ' ',
1200 info->protect[i] ? "RO" : " ");
6d0f6bcf 1201#else /* ! CONFIG_SYS_FLASH_EMPTY_INFO */
be60a902
HS		 1202 printf (" %08lX %s ",
1203 info->start[i],
1204 info->protect[i] ? "RO" : " ");
bf9e3b38 1205#endif
be60a902
HS		 1206 }
1207 putc ('\n');
1208 return;
5653fc33
WD		 1209}
1210
9a042e9c
JVB		 1211/*-----------------------------------------------------------------------
1212 * This is used in a few places in write_buf() to show programming
1213 * progress. Making it a function is nasty because it needs to do side
1214 * effect updates to digit and dots. Repeated code is nasty too, so
1215 * we define it once here.
1216 */
f0105727
SR		 1217#ifdef CONFIG_FLASH_SHOW_PROGRESS
1218#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub) \
1219 dots -= dots_sub; \
9a042e9c
JVB		 1220 if ((scale > 0) && (dots <= 0)) { \
1221 if ((digit % 5) == 0) \
1222 printf ("%d", digit / 5); \
1223 else \
1224 putc ('.'); \
1225 digit--; \
1226 dots += scale; \
1227 }
f0105727
SR		 1228#else
1229#define FLASH_SHOW_PROGRESS(scale, dots, digit, dots_sub)
1230#endif
9a042e9c 1231
be60a902
HS		 1232/*-----------------------------------------------------------------------
1233 * Copy memory to flash, returns:
1234 * 0 - OK
1235 * 1 - write timeout
1236 * 2 - Flash not erased
5653fc33 1237 */
be60a902 1238int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
5653fc33 1239{
be60a902 1240 ulong wp;
12d30aa7 1241 uchar *p;
be60a902 1242 int aln;
5653fc33 1243 cfiword_t cword;
be60a902 1244 int i, rc;
6d0f6bcf 1245#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902 1246 int buffered_size;
5653fc33 1247#endif
9a042e9c
JVB		 1248#ifdef CONFIG_FLASH_SHOW_PROGRESS
1249 int digit = CONFIG_FLASH_SHOW_PROGRESS;
1250 int scale = 0;
1251 int dots = 0;
1252
1253 /*
1254 * Suppress if there are fewer than CONFIG_FLASH_SHOW_PROGRESS writes.
1255 */
1256 if (cnt >= CONFIG_FLASH_SHOW_PROGRESS) {
1257 scale = (int)((cnt + CONFIG_FLASH_SHOW_PROGRESS - 1) /
1258 CONFIG_FLASH_SHOW_PROGRESS);
1259 }
1260#endif
1261
be60a902
HS		 1262 /* get lower aligned address */
1263 wp = (addr & ~(info->portwidth - 1));
3a197b2f 1264
be60a902
HS		 1265 /* handle unaligned start */
1266 if ((aln = addr - wp) != 0) {
1267 cword.l = 0;
12d30aa7
HS		 1268 p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
1269 for (i = 0; i < aln; ++i)
1270 flash_add_byte (info, &cword, flash_read8(p + i));
5653fc33 1271
be60a902
HS		 1272 for (; (i < info->portwidth) && (cnt > 0); i++) {
1273 flash_add_byte (info, &cword, *src++);
1274 cnt--;
be60a902 1275 }
12d30aa7
HS		 1276 for (; (cnt == 0) && (i < info->portwidth); ++i)
1277 flash_add_byte (info, &cword, flash_read8(p + i));
1278
1279 rc = flash_write_cfiword (info, wp, cword);
1280 unmap_physmem(p, info->portwidth);
1281 if (rc != 0)
be60a902 1282 return rc;
12d30aa7
HS		 1283
1284 wp += i;
f0105727 1285 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS		 1286 }
1287
1288 /* handle the aligned part */
6d0f6bcf 1289#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
be60a902
HS		 1290 buffered_size = (info->portwidth / info->chipwidth);
1291 buffered_size *= info->buffer_size;
1292 while (cnt >= info->portwidth) {
1293 /* prohibit buffer write when buffer_size is 1 */
1294 if (info->buffer_size == 1) {
1295 cword.l = 0;
1296 for (i = 0; i < info->portwidth; i++)
1297 flash_add_byte (info, &cword, *src++);
1298 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1299 return rc;
1300 wp += info->portwidth;
1301 cnt -= info->portwidth;
1302 continue;
1303 }
1304
1305 /* write buffer until next buffered_size aligned boundary */
1306 i = buffered_size - (wp % buffered_size);
1307 if (i > cnt)
1308 i = cnt;
1309 if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
1310 return rc;
1311 i -= i & (info->portwidth - 1);
1312 wp += i;
1313 src += i;
1314 cnt -= i;
f0105727 1315 FLASH_SHOW_PROGRESS(scale, dots, digit, i);
be60a902
HS		 1316 }
1317#else
1318 while (cnt >= info->portwidth) {
1319 cword.l = 0;
1320 for (i = 0; i < info->portwidth; i++) {
1321 flash_add_byte (info, &cword, *src++);
1322 }
1323 if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
1324 return rc;
1325 wp += info->portwidth;
1326 cnt -= info->portwidth;
f0105727 1327 FLASH_SHOW_PROGRESS(scale, dots, digit, info->portwidth);
be60a902 1328 }
6d0f6bcf 1329#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
9a042e9c 1330
be60a902
HS		 1331 if (cnt == 0) {
1332 return (0);
1333 }
1334
1335 /*
1336 * handle unaligned tail bytes
1337 */
1338 cword.l = 0;
12d30aa7
HS		 1339 p = map_physmem(wp, info->portwidth, MAP_NOCACHE);
1340 for (i = 0; (i < info->portwidth) && (cnt > 0); ++i) {
be60a902
HS		 1341 flash_add_byte (info, &cword, *src++);
1342 --cnt;
1343 }
12d30aa7
HS		 1344 for (; i < info->portwidth; ++i)
1345 flash_add_byte (info, &cword, flash_read8(p + i));
1346 unmap_physmem(p, info->portwidth);
be60a902
HS		 1347
1348 return flash_write_cfiword (info, wp, cword);
5653fc33 1349}
bf9e3b38 1350
5653fc33
WD		 1351/*-----------------------------------------------------------------------
1352 */
6d0f6bcf 1353#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902
HS		 1354
1355int flash_real_protect (flash_info_t * info, long sector, int prot)
5653fc33 1356{
be60a902 1357 int retcode = 0;
5653fc33 1358
bc9019e1
RC		 1359 switch (info->vendor) {
1360 case CFI_CMDSET_INTEL_PROG_REGIONS:
1361 case CFI_CMDSET_INTEL_STANDARD:
9e8e63cc 1362 case CFI_CMDSET_INTEL_EXTENDED:
bc9019e1
RC		 1363 flash_write_cmd (info, sector, 0,
1364 FLASH_CMD_CLEAR_STATUS);
1365 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
1366 if (prot)
1367 flash_write_cmd (info, sector, 0,
1368 FLASH_CMD_PROTECT_SET);
1369 else
1370 flash_write_cmd (info, sector, 0,
1371 FLASH_CMD_PROTECT_CLEAR);
1372 break;
1373 case CFI_CMDSET_AMD_EXTENDED:
1374 case CFI_CMDSET_AMD_STANDARD:
bc9019e1
RC		 1375 /* U-Boot only checks the first byte */
1376 if (info->manufacturer_id == (uchar)ATM_MANUFACT) {
1377 if (prot) {
1378 flash_unlock_seq (info, 0);
1379 flash_write_cmd (info, 0,
1380 info->addr_unlock1,
1381 ATM_CMD_SOFTLOCK_START);
1382 flash_unlock_seq (info, 0);
1383 flash_write_cmd (info, sector, 0,
1384 ATM_CMD_LOCK_SECT);
1385 } else {
1386 flash_write_cmd (info, 0,
1387 info->addr_unlock1,
1388 AMD_CMD_UNLOCK_START);
1389 if (info->device_id == ATM_ID_BV6416)
1390 flash_write_cmd (info, sector,
1391 0, ATM_CMD_UNLOCK_SECT);
1392 }
1393 }
1394 break;
4e00acde
TL		 1395#ifdef CONFIG_FLASH_CFI_LEGACY
1396 case CFI_CMDSET_AMD_LEGACY:
1397 flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
1398 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
1399 if (prot)
1400 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
1401 else
1402 flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
1403#endif
bc9019e1 1404 };
bf9e3b38 1405
be60a902
HS		 1406 if ((retcode =
1407 flash_full_status_check (info, sector, info->erase_blk_tout,
1408 prot ? "protect" : "unprotect")) == 0) {
bf9e3b38 1409
be60a902
HS		 1410 info->protect[sector] = prot;
1411
1412 /*
1413 * On some of Intel's flash chips (marked via legacy_unlock)
1414 * unprotect unprotects all locking.
1415 */
1416 if ((prot == 0) && (info->legacy_unlock)) {
1417 flash_sect_t i;
1418
1419 for (i = 0; i < info->sector_count; i++) {
1420 if (info->protect[i])
1421 flash_real_protect (info, i, 1);
1422 }
5653fc33 1423 }
5653fc33 1424 }
be60a902 1425 return retcode;
5653fc33 1426}
bf9e3b38 1427
5653fc33 1428/*-----------------------------------------------------------------------
be60a902 1429 * flash_read_user_serial - read the OneTimeProgramming cells
5653fc33 1430 */
be60a902
HS		 1431void flash_read_user_serial (flash_info_t * info, void *buffer, int offset,
1432 int len)
5653fc33 1433{
be60a902
HS		 1434 uchar *src;
1435 uchar *dst;
bf9e3b38 1436
be60a902 1437 dst = buffer;
12d30aa7 1438 src = flash_map (info, 0, FLASH_OFFSET_USER_PROTECTION);
be60a902
HS		 1439 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1440 memcpy (dst, src + offset, len);
1441 flash_write_cmd (info, 0, 0, info->cmd_reset);
12d30aa7 1442 flash_unmap(info, 0, FLASH_OFFSET_USER_PROTECTION, src);
5653fc33
WD		 1443}
1444
be60a902
HS		 1445/*
1446 * flash_read_factory_serial - read the device Id from the protection area
5653fc33 1447 */
be60a902
HS		 1448void flash_read_factory_serial (flash_info_t * info, void *buffer, int offset,
1449 int len)
5653fc33 1450{
be60a902 1451 uchar *src;
bf9e3b38 1452
12d30aa7 1453 src = flash_map (info, 0, FLASH_OFFSET_INTEL_PROTECTION);
be60a902
HS		 1454 flash_write_cmd (info, 0, 0, FLASH_CMD_READ_ID);
1455 memcpy (buffer, src + offset, len);
1456 flash_write_cmd (info, 0, 0, info->cmd_reset);
12d30aa7 1457 flash_unmap(info, 0, FLASH_OFFSET_INTEL_PROTECTION, src);
5653fc33
WD		 1458}
1459
6d0f6bcf 1460#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 1461
0ddf06dd
HS		 1462/*-----------------------------------------------------------------------
1463 * Reverse the order of the erase regions in the CFI QRY structure.
1464 * This is needed for chips that are either a) correctly detected as
1465 * top-boot, or b) buggy.
1466 */
1467static void cfi_reverse_geometry(struct cfi_qry *qry)
1468{
1469 unsigned int i, j;
1470 u32 tmp;
1471
1472 for (i = 0, j = qry->num_erase_regions - 1; i < j; i++, j--) {
1473 tmp = qry->erase_region_info[i];
1474 qry->erase_region_info[i] = qry->erase_region_info[j];
1475 qry->erase_region_info[j] = tmp;
1476 }
1477}
be60a902 1478
260421a2
SR		 1479/*-----------------------------------------------------------------------
1480 * read jedec ids from device and set corresponding fields in info struct
1481 *
1482 * Note: assume cfi->vendor, cfi->portwidth and cfi->chipwidth are correct
1483 *
0ddf06dd
HS		 1484 */
1485static void cmdset_intel_read_jedec_ids(flash_info_t *info)
1486{
1487 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1488 flash_write_cmd(info, 0, 0, FLASH_CMD_READ_ID);
1489 udelay(1000); /* some flash are slow to respond */
1490 info->manufacturer_id = flash_read_uchar (info,
1491 FLASH_OFFSET_MANUFACTURER_ID);
1492 info->device_id = flash_read_uchar (info,
1493 FLASH_OFFSET_DEVICE_ID);
1494 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1495}
1496
1497static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry)
1498{
1499 info->cmd_reset = FLASH_CMD_RESET;
1500
1501 cmdset_intel_read_jedec_ids(info);
1502 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1503
6d0f6bcf 1504#ifdef CONFIG_SYS_FLASH_PROTECTION
0ddf06dd
HS		 1505 /* read legacy lock/unlock bit from intel flash */
1506 if (info->ext_addr) {
1507 info->legacy_unlock = flash_read_uchar (info,
1508 info->ext_addr + 5) & 0x08;
1509 }
1510#endif
1511
1512 return 0;
1513}
1514
1515static void cmdset_amd_read_jedec_ids(flash_info_t *info)
1516{
1517 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1518 flash_unlock_seq(info, 0);
1519 flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID);
1520 udelay(1000); /* some flash are slow to respond */
90447ecb 1521
0ddf06dd
HS		 1522 info->manufacturer_id = flash_read_uchar (info,
1523 FLASH_OFFSET_MANUFACTURER_ID);
90447ecb
TK		 1524
1525 switch (info->chipwidth){
1526 case FLASH_CFI_8BIT:
1527 info->device_id = flash_read_uchar (info,
1528 FLASH_OFFSET_DEVICE_ID);
1529 if (info->device_id == 0x7E) {
1530 /* AMD 3-byte (expanded) device ids */
1531 info->device_id2 = flash_read_uchar (info,
1532 FLASH_OFFSET_DEVICE_ID2);
1533 info->device_id2 <<= 8;
1534 info->device_id2 |= flash_read_uchar (info,
1535 FLASH_OFFSET_DEVICE_ID3);
1536 }
1537 break;
1538 case FLASH_CFI_16BIT:
1539 info->device_id = flash_read_word (info,
1540 FLASH_OFFSET_DEVICE_ID);
1541 break;
1542 default:
1543 break;
0ddf06dd
HS		 1544 }
1545 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
1546}
1547
1548static int cmdset_amd_init(flash_info_t *info, struct cfi_qry *qry)
1549{
1550 info->cmd_reset = AMD_CMD_RESET;
1551
1552 cmdset_amd_read_jedec_ids(info);
1553 flash_write_cmd(info, 0, info->cfi_offset, FLASH_CMD_CFI);
1554
0ddf06dd
HS		 1555 return 0;
1556}
1557
1558#ifdef CONFIG_FLASH_CFI_LEGACY
260421a2
SR		 1559static void flash_read_jedec_ids (flash_info_t * info)
1560{
1561 info->manufacturer_id = 0;
1562 info->device_id = 0;
1563 info->device_id2 = 0;
1564
1565 switch (info->vendor) {
9c048b52 1566 case CFI_CMDSET_INTEL_PROG_REGIONS:
260421a2
SR		 1567 case CFI_CMDSET_INTEL_STANDARD:
1568 case CFI_CMDSET_INTEL_EXTENDED:
8225d1e3 1569 cmdset_intel_read_jedec_ids(info);
260421a2
SR		 1570 break;
1571 case CFI_CMDSET_AMD_STANDARD:
1572 case CFI_CMDSET_AMD_EXTENDED:
8225d1e3 1573 cmdset_amd_read_jedec_ids(info);
260421a2
SR		 1574 break;
1575 default:
1576 break;
1577 }
1578}
1579
5653fc33 1580/*-----------------------------------------------------------------------
be60a902
HS		 1581 * Call board code to request info about non-CFI flash.
1582 * board_flash_get_legacy needs to fill in at least:
1583 * info->portwidth, info->chipwidth and info->interface for Jedec probing.
7e5b9b47 1584 */
be60a902 1585static int flash_detect_legacy(ulong base, int banknum)
5653fc33 1586{
be60a902 1587 flash_info_t *info = &flash_info[banknum];
7e5b9b47 1588
be60a902
HS		 1589 if (board_flash_get_legacy(base, banknum, info)) {
1590 /* board code may have filled info completely. If not, we
1591 use JEDEC ID probing. */
1592 if (!info->vendor) {
1593 int modes[] = {
1594 CFI_CMDSET_AMD_STANDARD,
1595 CFI_CMDSET_INTEL_STANDARD
1596 };
1597 int i;
7e5b9b47 1598
be60a902
HS		 1599 for (i = 0; i < sizeof(modes) / sizeof(modes[0]); i++) {
1600 info->vendor = modes[i];
1601 info->start[0] = base;
1602 if (info->portwidth == FLASH_CFI_8BIT
1603 && info->interface == FLASH_CFI_X8X16) {
1604 info->addr_unlock1 = 0x2AAA;
1605 info->addr_unlock2 = 0x5555;
1606 } else {
1607 info->addr_unlock1 = 0x5555;
1608 info->addr_unlock2 = 0x2AAA;
1609 }
1610 flash_read_jedec_ids(info);
1611 debug("JEDEC PROBE: ID %x %x %x\n",
1612 info->manufacturer_id,
1613 info->device_id,
1614 info->device_id2);
1615 if (jedec_flash_match(info, base))
1616 break;
1617 }
1618 }
1619
1620 switch(info->vendor) {
9c048b52 1621 case CFI_CMDSET_INTEL_PROG_REGIONS:
be60a902
HS		 1622 case CFI_CMDSET_INTEL_STANDARD:
1623 case CFI_CMDSET_INTEL_EXTENDED:
1624 info->cmd_reset = FLASH_CMD_RESET;
1625 break;
1626 case CFI_CMDSET_AMD_STANDARD:
1627 case CFI_CMDSET_AMD_EXTENDED:
1628 case CFI_CMDSET_AMD_LEGACY:
1629 info->cmd_reset = AMD_CMD_RESET;
1630 break;
1631 }
1632 info->flash_id = FLASH_MAN_CFI;
1633 return 1;
1634 }
1635 return 0; /* use CFI */
1636}
1637#else
1638static inline int flash_detect_legacy(ulong base, int banknum)
1639{
1640 return 0; /* use CFI */
1641}
1642#endif
1643
1644/*-----------------------------------------------------------------------
1645 * detect if flash is compatible with the Common Flash Interface (CFI)
1646 * http://www.jedec.org/download/search/jesd68.pdf
1647 */
e23741f4
HS		 1648static void flash_read_cfi (flash_info_t *info, void *buf,
1649 unsigned int start, size_t len)
1650{
1651 u8 *p = buf;
1652 unsigned int i;
1653
1654 for (i = 0; i < len; i++)
1655 p[i] = flash_read_uchar(info, start + i);
1656}
1657
1658static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
be60a902
HS		 1659{
1660 int cfi_offset;
1661
1ba639da
MS		 1662 /* We do not yet know what kind of commandset to use, so we issue
1663 the reset command in both Intel and AMD variants, in the hope
1664 that AMD flash roms ignore the Intel command. */
1665 flash_write_cmd (info, 0, 0, AMD_CMD_RESET);
1666 flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
1667
be60a902
HS		 1668 for (cfi_offset=0;
1669 cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint);
1670 cfi_offset++) {
1671 flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset],
1672 FLASH_CMD_CFI);
1673 if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
1674 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R')
1675 && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
e23741f4
HS		 1676 flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP,
1677 sizeof(struct cfi_qry));
1678 info->interface = le16_to_cpu(qry->interface_desc);
1679
be60a902
HS		 1680 info->cfi_offset = flash_offset_cfi[cfi_offset];
1681 debug ("device interface is %d\n",
1682 info->interface);
1683 debug ("found port %d chip %d ",
1684 info->portwidth, info->chipwidth);
1685 debug ("port %d bits chip %d bits\n",
1686 info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1687 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1688
1689 /* calculate command offsets as in the Linux driver */
1690 info->addr_unlock1 = 0x555;
7e5b9b47
HS		 1691 info->addr_unlock2 = 0x2aa;
1692
1693 /*
1694 * modify the unlock address if we are
1695 * in compatibility mode
1696 */
1697 if ( /* x8/x16 in x8 mode */
1698 ((info->chipwidth == FLASH_CFI_BY8) &&
1699 (info->interface == FLASH_CFI_X8X16)) ||
1700 /* x16/x32 in x16 mode */
1701 ((info->chipwidth == FLASH_CFI_BY16) &&
1702 (info->interface == FLASH_CFI_X16X32)))
1703 {
1704 info->addr_unlock1 = 0xaaa;
1705 info->addr_unlock2 = 0x555;
1706 }
1707
1708 info->name = "CFI conformant";
1709 return 1;
1710 }
1711 }
1712
1713 return 0;
1714}
1715
e23741f4 1716static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry)
7e5b9b47 1717{
bf9e3b38
WD		 1718 debug ("flash detect cfi\n");
1719
6d0f6bcf 1720 for (info->portwidth = CONFIG_SYS_FLASH_CFI_WIDTH;
bf9e3b38
WD		 1721 info->portwidth <= FLASH_CFI_64BIT; info->portwidth <<= 1) {
1722 for (info->chipwidth = FLASH_CFI_BY8;
1723 info->chipwidth <= info->portwidth;
7e5b9b47 1724 info->chipwidth <<= 1)
e23741f4 1725 if (__flash_detect_cfi(info, qry))
7e5b9b47 1726 return 1;
5653fc33 1727 }
bf9e3b38 1728 debug ("not found\n");
5653fc33
WD		 1729 return 0;
1730}
bf9e3b38 1731
467bcee1
HS		 1732/*
1733 * Manufacturer-specific quirks. Add workarounds for geometry
1734 * reversal, etc. here.
1735 */
1736static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry)
1737{
1738 /* check if flash geometry needs reversal */
1739 if (qry->num_erase_regions > 1) {
1740 /* reverse geometry if top boot part */
1741 if (info->cfi_version < 0x3131) {
1742 /* CFI < 1.1, try to guess from device id */
1743 if ((info->device_id & 0x80) != 0)
1744 cfi_reverse_geometry(qry);
1745 } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) {
1746 /* CFI >= 1.1, deduct from top/bottom flag */
1747 /* note: ext_addr is valid since cfi_version > 0 */
1748 cfi_reverse_geometry(qry);
1749 }
1750 }
1751}
1752
1753static void flash_fixup_atmel(flash_info_t *info, struct cfi_qry *qry)
1754{
1755 int reverse_geometry = 0;
1756
1757 /* Check the "top boot" bit in the PRI */
1758 if (info->ext_addr && !(flash_read_uchar(info, info->ext_addr + 6) & 1))
1759 reverse_geometry = 1;
1760
1761 /* AT49BV6416(T) list the erase regions in the wrong order.
1762 * However, the device ID is identical with the non-broken
1763 * AT49BV642D since u-boot only reads the low byte (they
1764 * differ in the high byte.) So leave out this fixup for now.
1765 */
1766#if 0
1767 if (info->device_id == 0xd6 || info->device_id == 0xd2)
1768 reverse_geometry = !reverse_geometry;
1769#endif
1770
1771 if (reverse_geometry)
1772 cfi_reverse_geometry(qry);
1773}
1774
5653fc33
WD		 1775/*
1776 * The following code cannot be run from FLASH!
1777 *
1778 */
e6f2e902 1779ulong flash_get_size (ulong base, int banknum)
5653fc33 1780{
bf9e3b38 1781 flash_info_t *info = &flash_info[banknum];
5653fc33
WD		 1782 int i, j;
1783 flash_sect_t sect_cnt;
1784 unsigned long sector;
1785 unsigned long tmp;
1786 int size_ratio;
1787 uchar num_erase_regions;
bf9e3b38
WD		 1788 int erase_region_size;
1789 int erase_region_count;
e23741f4 1790 struct cfi_qry qry;
260421a2 1791
f979690e
KG		 1792 memset(&qry, 0, sizeof(qry));
1793
260421a2
SR		 1794 info->ext_addr = 0;
1795 info->cfi_version = 0;
6d0f6bcf 1796#ifdef CONFIG_SYS_FLASH_PROTECTION
2662b40c
SR		 1797 info->legacy_unlock = 0;
1798#endif
5653fc33
WD		 1799
1800 info->start[0] = base;
1801
e23741f4
HS		 1802 if (flash_detect_cfi (info, &qry)) {
1803 info->vendor = le16_to_cpu(qry.p_id);
1804 info->ext_addr = le16_to_cpu(qry.p_adr);
1805 num_erase_regions = qry.num_erase_regions;
1806
260421a2
SR		 1807 if (info->ext_addr) {
1808 info->cfi_version = (ushort) flash_read_uchar (info,
1809 info->ext_addr + 3) << 8;
1810 info->cfi_version |= (ushort) flash_read_uchar (info,
1811 info->ext_addr + 4);
1812 }
0ddf06dd 1813
bf9e3b38 1814#ifdef DEBUG
e23741f4 1815 flash_printqry (&qry);
bf9e3b38 1816#endif
0ddf06dd 1817
bf9e3b38 1818 switch (info->vendor) {
9c048b52 1819 case CFI_CMDSET_INTEL_PROG_REGIONS:
5653fc33
WD		 1820 case CFI_CMDSET_INTEL_STANDARD:
1821 case CFI_CMDSET_INTEL_EXTENDED:
0ddf06dd 1822 cmdset_intel_init(info, &qry);
5653fc33
WD		 1823 break;
1824 case CFI_CMDSET_AMD_STANDARD:
1825 case CFI_CMDSET_AMD_EXTENDED:
0ddf06dd 1826 cmdset_amd_init(info, &qry);
5653fc33 1827 break;
0ddf06dd
HS		 1828 default:
1829 printf("CFI: Unknown command set 0x%x\n",
1830 info->vendor);
1831 /*
1832 * Unfortunately, this means we don't know how
1833 * to get the chip back to Read mode. Might
1834 * as well try an Intel-style reset...
1835 */
1836 flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
1837 return 0;
5653fc33 1838 }
cd37d9e6 1839
467bcee1
HS		 1840 /* Do manufacturer-specific fixups */
1841 switch (info->manufacturer_id) {
1842 case 0x0001:
1843 flash_fixup_amd(info, &qry);
1844 break;
1845 case 0x001f:
1846 flash_fixup_atmel(info, &qry);
1847 break;
1848 }
1849
bf9e3b38 1850 debug ("manufacturer is %d\n", info->vendor);
260421a2
SR		 1851 debug ("manufacturer id is 0x%x\n", info->manufacturer_id);
1852 debug ("device id is 0x%x\n", info->device_id);
1853 debug ("device id2 is 0x%x\n", info->device_id2);
1854 debug ("cfi version is 0x%04x\n", info->cfi_version);
1855
5653fc33 1856 size_ratio = info->portwidth / info->chipwidth;
bf9e3b38
WD		 1857 /* if the chip is x8/x16 reduce the ratio by half */
1858 if ((info->interface == FLASH_CFI_X8X16)
1859 && (info->chipwidth == FLASH_CFI_BY8)) {
1860 size_ratio >>= 1;
1861 }
bf9e3b38
WD		 1862 debug ("size_ratio %d port %d bits chip %d bits\n",
1863 size_ratio, info->portwidth << CFI_FLASH_SHIFT_WIDTH,
1864 info->chipwidth << CFI_FLASH_SHIFT_WIDTH);
1865 debug ("found %d erase regions\n", num_erase_regions);
5653fc33
WD		 1866 sect_cnt = 0;
1867 sector = base;
bf9e3b38
WD		 1868 for (i = 0; i < num_erase_regions; i++) {
1869 if (i > NUM_ERASE_REGIONS) {
028ab6b5
WD		 1870 printf ("%d erase regions found, only %d used\n",
1871 num_erase_regions, NUM_ERASE_REGIONS);
5653fc33
WD		 1872 break;
1873 }
e23741f4 1874
0ddf06dd
HS		 1875 tmp = le32_to_cpu(qry.erase_region_info[i]);
1876 debug("erase region %u: 0x%08lx\n", i, tmp);
e23741f4
HS		 1877
1878 erase_region_count = (tmp & 0xffff) + 1;
1879 tmp >>= 16;
bf9e3b38
WD		 1880 erase_region_size =
1881 (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
4c0d4c3b 1882 debug ("erase_region_count = %d erase_region_size = %d\n",
028ab6b5 1883 erase_region_count, erase_region_size);
bf9e3b38 1884 for (j = 0; j < erase_region_count; j++) {
6d0f6bcf 1885 if (sect_cnt >= CONFIG_SYS_MAX_FLASH_SECT) {
81b20ccc
MS		 1886 printf("ERROR: too many flash sectors\n");
1887 break;
1888 }
5653fc33
WD		 1889 info->start[sect_cnt] = sector;
1890 sector += (erase_region_size * size_ratio);
a1191902
WD		 1891
1892 /*
7e5b9b47
HS		 1893 * Only read protection status from
1894 * supported devices (intel...)
a1191902
WD		 1895 */
1896 switch (info->vendor) {
9c048b52 1897 case CFI_CMDSET_INTEL_PROG_REGIONS:
a1191902
WD		 1898 case CFI_CMDSET_INTEL_EXTENDED:
1899 case CFI_CMDSET_INTEL_STANDARD:
1900 info->protect[sect_cnt] =
1901 flash_isset (info, sect_cnt,
1902 FLASH_OFFSET_PROTECT,
1903 FLASH_STATUS_PROTECT);
1904 break;
1905 default:
7e5b9b47
HS		 1906 /* default: not protected */
1907 info->protect[sect_cnt] = 0;
a1191902
WD		 1908 }
1909
5653fc33
WD		 1910 sect_cnt++;
1911 }
1912 }
1913
1914 info->sector_count = sect_cnt;
e23741f4 1915 info->size = 1 << qry.dev_size;
5653fc33 1916 /* multiply the size by the number of chips */
7e5b9b47 1917 info->size *= size_ratio;
e23741f4
HS		 1918 info->buffer_size = 1 << le16_to_cpu(qry.max_buf_write_size);
1919 tmp = 1 << qry.block_erase_timeout_typ;
7e5b9b47 1920 info->erase_blk_tout = tmp *
e23741f4
HS		 1921 (1 << qry.block_erase_timeout_max);
1922 tmp = (1 << qry.buf_write_timeout_typ) *
1923 (1 << qry.buf_write_timeout_max);
1924
7e5b9b47 1925 /* round up when converting to ms */
e23741f4
HS		 1926 info->buffer_write_tout = (tmp + 999) / 1000;
1927 tmp = (1 << qry.word_write_timeout_typ) *
1928 (1 << qry.word_write_timeout_max);
7e5b9b47 1929 /* round up when converting to ms */
e23741f4 1930 info->write_tout = (tmp + 999) / 1000;
5653fc33 1931 info->flash_id = FLASH_MAN_CFI;
7e5b9b47
HS		 1932 if ((info->interface == FLASH_CFI_X8X16) &&
1933 (info->chipwidth == FLASH_CFI_BY8)) {
1934 /* XXX - Need to test on x8/x16 in parallel. */
1935 info->portwidth >>= 1;
855a496f 1936 }
2215987e
MF		 1937
1938 flash_write_cmd (info, 0, 0, info->cmd_reset);
5653fc33
WD		 1939 }
1940
bf9e3b38 1941 return (info->size);
5653fc33
WD		 1942}
1943
5653fc33
WD		 1944/*-----------------------------------------------------------------------
1945 */
be60a902 1946unsigned long flash_init (void)
5653fc33 1947{
be60a902
HS		 1948 unsigned long size = 0;
1949 int i;
6d0f6bcf 1950#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
c63ad632
MF		 1951 struct apl_s {
1952 ulong start;
1953 ulong size;
6d0f6bcf 1954 } apl[] = CONFIG_SYS_FLASH_AUTOPROTECT_LIST;
c63ad632 1955#endif
5653fc33 1956
6d0f6bcf 1957#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902 1958 char *s = getenv("unlock");
81b20ccc 1959#endif
5653fc33 1960
6d0f6bcf 1961#define BANK_BASE(i) (((unsigned long [CFI_MAX_FLASH_BANKS])CONFIG_SYS_FLASH_BANKS_LIST)[i])
2a112b23 1962
be60a902 1963 /* Init: no FLASHes known */
6d0f6bcf 1964 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
be60a902 1965 flash_info[i].flash_id = FLASH_UNKNOWN;
5653fc33 1966
2a112b23
WD		 1967 if (!flash_detect_legacy (BANK_BASE(i), i))
1968 flash_get_size (BANK_BASE(i), i);
be60a902
HS		 1969 size += flash_info[i].size;
1970 if (flash_info[i].flash_id == FLASH_UNKNOWN) {
6d0f6bcf 1971#ifndef CONFIG_SYS_FLASH_QUIET_TEST
be60a902
HS		 1972 printf ("## Unknown FLASH on Bank %d "
1973 "- Size = 0x%08lx = %ld MB\n",
1974 i+1, flash_info[i].size,
1975 flash_info[i].size << 20);
6d0f6bcf 1976#endif /* CONFIG_SYS_FLASH_QUIET_TEST */
be60a902 1977 }
6d0f6bcf 1978#ifdef CONFIG_SYS_FLASH_PROTECTION
be60a902
HS		 1979 else if ((s != NULL) && (strcmp(s, "yes") == 0)) {
1980 /*
1981 * Only the U-Boot image and it's environment
1982 * is protected, all other sectors are
1983 * unprotected (unlocked) if flash hardware
6d0f6bcf 1984 * protection is used (CONFIG_SYS_FLASH_PROTECTION)
be60a902
HS		 1985 * and the environment variable "unlock" is
1986 * set to "yes".
1987 */
1988 if (flash_info[i].legacy_unlock) {
1989 int k;
5653fc33 1990
be60a902
HS		 1991 /*
1992 * Disable legacy_unlock temporarily,
1993 * since flash_real_protect would
1994 * relock all other sectors again
1995 * otherwise.
1996 */
1997 flash_info[i].legacy_unlock = 0;
5653fc33 1998
be60a902
HS		 1999 /*
2000 * Legacy unlocking (e.g. Intel J3) ->
2001 * unlock only one sector. This will
2002 * unlock all sectors.
2003 */
2004 flash_real_protect (&flash_info[i], 0, 0);
5653fc33 2005
be60a902 2006 flash_info[i].legacy_unlock = 1;
5653fc33 2007
be60a902
HS		 2008 /*
2009 * Manually mark other sectors as
2010 * unlocked (unprotected)
2011 */
2012 for (k = 1; k < flash_info[i].sector_count; k++)
2013 flash_info[i].protect[k] = 0;
2014 } else {
2015 /*
2016 * No legancy unlocking -> unlock all sectors
2017 */
2018 flash_protect (FLAG_PROTECT_CLEAR,
2019 flash_info[i].start[0],
2020 flash_info[i].start[0]
2021 + flash_info[i].size - 1,
2022 &flash_info[i]);
79b4cda0 2023 }
79b4cda0 2024 }
6d0f6bcf 2025#endif /* CONFIG_SYS_FLASH_PROTECTION */
be60a902 2026 }
79b4cda0 2027
be60a902 2028 /* Monitor protection ON by default */
6d0f6bcf 2029#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
be60a902 2030 flash_protect (FLAG_PROTECT_SET,
6d0f6bcf
JCPV		 2031 CONFIG_SYS_MONITOR_BASE,
2032 CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
2033 flash_get_info(CONFIG_SYS_MONITOR_BASE));
be60a902 2034#endif
79b4cda0 2035
be60a902 2036 /* Environment protection ON by default */
5a1aceb0 2037#ifdef CONFIG_ENV_IS_IN_FLASH
be60a902 2038 flash_protect (FLAG_PROTECT_SET,
0e8d1586
JCPV		 2039 CONFIG_ENV_ADDR,
2040 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
2041 flash_get_info(CONFIG_ENV_ADDR));
be60a902 2042#endif
79b4cda0 2043
be60a902 2044 /* Redundant environment protection ON by default */
0e8d1586 2045#ifdef CONFIG_ENV_ADDR_REDUND
be60a902 2046 flash_protect (FLAG_PROTECT_SET,
0e8d1586
JCPV		 2047 CONFIG_ENV_ADDR_REDUND,
2048 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
2049 flash_get_info(CONFIG_ENV_ADDR_REDUND));
be60a902 2050#endif
c63ad632 2051
6d0f6bcf 2052#if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST)
c63ad632
MF		 2053 for (i = 0; i < (sizeof(apl) / sizeof(struct apl_s)); i++) {
2054 debug("autoprotecting from %08x to %08x\n",
2055 apl[i].start, apl[i].start + apl[i].size - 1);
2056 flash_protect (FLAG_PROTECT_SET,
2057 apl[i].start,
2058 apl[i].start + apl[i].size - 1,
2059 flash_get_info(apl[i].start));
2060 }
2061#endif
be60a902 2062 return (size);
5653fc33 2063}
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