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Commit | Line | Data |
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c74b2108 SK |
1 | /* |
2 | * Ethernet driver for TI TMS320DM644x (DaVinci) chips. | |
3 | * | |
4 | * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> | |
5 | * | |
6 | * Parts shamelessly stolen from TI's dm644x_emac.c. Original copyright | |
7 | * follows: | |
8 | * | |
9 | * ---------------------------------------------------------------------------- | |
10 | * | |
11 | * dm644x_emac.c | |
12 | * | |
13 | * TI DaVinci (DM644X) EMAC peripheral driver source for DV-EVM | |
14 | * | |
15 | * Copyright (C) 2005 Texas Instruments. | |
16 | * | |
17 | * ---------------------------------------------------------------------------- | |
18 | * | |
1a459660 | 19 | * SPDX-License-Identifier: GPL-2.0+ |
c74b2108 | 20 | * |
c74b2108 SK |
21 | * Modifications: |
22 | * ver. 1.0: Sep 2005, Anant Gole - Created EMAC version for uBoot. | |
23 | * ver 1.1: Nov 2005, Anant Gole - Extended the RX logic for multiple descriptors | |
c74b2108 SK |
24 | */ |
25 | #include <common.h> | |
26 | #include <command.h> | |
27 | #include <net.h> | |
28 | #include <miiphy.h> | |
8453587e | 29 | #include <malloc.h> |
2aa87202 | 30 | #include <linux/compiler.h> |
c74b2108 | 31 | #include <asm/arch/emac_defs.h> |
d7e35437 | 32 | #include <asm/io.h> |
7c587d32 | 33 | #include "davinci_emac.h" |
c74b2108 | 34 | |
c74b2108 SK |
35 | unsigned int emac_dbg = 0; |
36 | #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) | |
37 | ||
82b77217 IY |
38 | #ifdef EMAC_HW_RAM_ADDR |
39 | static inline unsigned long BD_TO_HW(unsigned long x) | |
40 | { | |
41 | if (x == 0) | |
42 | return 0; | |
43 | ||
44 | return x - EMAC_WRAPPER_RAM_ADDR + EMAC_HW_RAM_ADDR; | |
45 | } | |
46 | ||
47 | static inline unsigned long HW_TO_BD(unsigned long x) | |
48 | { | |
49 | if (x == 0) | |
50 | return 0; | |
51 | ||
52 | return x - EMAC_HW_RAM_ADDR + EMAC_WRAPPER_RAM_ADDR; | |
53 | } | |
54 | #else | |
55 | #define BD_TO_HW(x) (x) | |
56 | #define HW_TO_BD(x) (x) | |
57 | #endif | |
58 | ||
d7e35437 | 59 | #ifdef DAVINCI_EMAC_GIG_ENABLE |
fb1d6332 | 60 | #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) |
d7e35437 | 61 | #else |
fb1d6332 | 62 | #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ |
d7e35437 NT |
63 | #endif |
64 | ||
882ecfa3 HS |
65 | #if !defined(CONFIG_SYS_EMAC_TI_CLKDIV) |
66 | #define CONFIG_SYS_EMAC_TI_CLKDIV ((EMAC_MDIO_BUS_FREQ / \ | |
67 | EMAC_MDIO_CLOCK_FREQ) - 1) | |
68 | #endif | |
69 | ||
fcaac589 | 70 | static void davinci_eth_mdio_enable(void); |
c74b2108 SK |
71 | |
72 | static int gen_init_phy(int phy_addr); | |
73 | static int gen_is_phy_connected(int phy_addr); | |
74 | static int gen_get_link_speed(int phy_addr); | |
75 | static int gen_auto_negotiate(int phy_addr); | |
76 | ||
c74b2108 SK |
77 | void eth_mdio_enable(void) |
78 | { | |
fcaac589 | 79 | davinci_eth_mdio_enable(); |
c74b2108 | 80 | } |
c74b2108 | 81 | |
c74b2108 SK |
82 | /* EMAC Addresses */ |
83 | static volatile emac_regs *adap_emac = (emac_regs *)EMAC_BASE_ADDR; | |
84 | static volatile ewrap_regs *adap_ewrap = (ewrap_regs *)EMAC_WRAPPER_BASE_ADDR; | |
85 | static volatile mdio_regs *adap_mdio = (mdio_regs *)EMAC_MDIO_BASE_ADDR; | |
86 | ||
87 | /* EMAC descriptors */ | |
88 | static volatile emac_desc *emac_rx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE); | |
89 | static volatile emac_desc *emac_tx_desc = (emac_desc *)(EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); | |
90 | static volatile emac_desc *emac_rx_active_head = 0; | |
91 | static volatile emac_desc *emac_rx_active_tail = 0; | |
92 | static int emac_rx_queue_active = 0; | |
93 | ||
94 | /* Receive packet buffers */ | |
2aa87202 IY |
95 | static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * EMAC_RXBUF_SIZE] |
96 | __aligned(ARCH_DMA_MINALIGN); | |
c74b2108 | 97 | |
dc02bada HS |
98 | #ifndef CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT |
99 | #define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 3 | |
100 | #endif | |
062fe7d3 | 101 | |
c74b2108 | 102 | /* PHY address for a discovered PHY (0xff - not found) */ |
dc02bada | 103 | static u_int8_t active_phy_addr[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; |
062fe7d3 MH |
104 | |
105 | /* number of PHY found active */ | |
106 | static u_int8_t num_phy; | |
c74b2108 | 107 | |
dc02bada | 108 | phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; |
c74b2108 | 109 | |
2aa87202 IY |
110 | static inline void davinci_flush_rx_descs(void) |
111 | { | |
112 | /* flush the whole RX descs area */ | |
113 | flush_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, | |
114 | EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); | |
115 | } | |
116 | ||
117 | static inline void davinci_invalidate_rx_descs(void) | |
118 | { | |
119 | /* invalidate the whole RX descs area */ | |
120 | invalidate_dcache_range(EMAC_WRAPPER_RAM_ADDR + EMAC_RX_DESC_BASE, | |
121 | EMAC_WRAPPER_RAM_ADDR + EMAC_TX_DESC_BASE); | |
122 | } | |
123 | ||
124 | static inline void davinci_flush_desc(emac_desc *desc) | |
125 | { | |
126 | flush_dcache_range((unsigned long)desc, | |
127 | (unsigned long)desc + sizeof(*desc)); | |
128 | } | |
129 | ||
7b37a27e BG |
130 | static int davinci_eth_set_mac_addr(struct eth_device *dev) |
131 | { | |
132 | unsigned long mac_hi; | |
133 | unsigned long mac_lo; | |
134 | ||
135 | /* | |
136 | * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast | |
137 | * receive) | |
138 | * Using channel 0 only - other channels are disabled | |
139 | * */ | |
140 | writel(0, &adap_emac->MACINDEX); | |
141 | mac_hi = (dev->enetaddr[3] << 24) | | |
142 | (dev->enetaddr[2] << 16) | | |
143 | (dev->enetaddr[1] << 8) | | |
144 | (dev->enetaddr[0]); | |
145 | mac_lo = (dev->enetaddr[5] << 8) | | |
146 | (dev->enetaddr[4]); | |
147 | ||
148 | writel(mac_hi, &adap_emac->MACADDRHI); | |
149 | #if defined(DAVINCI_EMAC_VERSION2) | |
150 | writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, | |
151 | &adap_emac->MACADDRLO); | |
152 | #else | |
153 | writel(mac_lo, &adap_emac->MACADDRLO); | |
154 | #endif | |
155 | ||
156 | writel(0, &adap_emac->MACHASH1); | |
157 | writel(0, &adap_emac->MACHASH2); | |
158 | ||
159 | /* Set source MAC address - REQUIRED */ | |
160 | writel(mac_hi, &adap_emac->MACSRCADDRHI); | |
161 | writel(mac_lo, &adap_emac->MACSRCADDRLO); | |
162 | ||
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
fcaac589 | 167 | static void davinci_eth_mdio_enable(void) |
c74b2108 SK |
168 | { |
169 | u_int32_t clkdiv; | |
170 | ||
882ecfa3 | 171 | clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; |
c74b2108 | 172 | |
d7e35437 NT |
173 | writel((clkdiv & 0xff) | |
174 | MDIO_CONTROL_ENABLE | | |
175 | MDIO_CONTROL_FAULT | | |
176 | MDIO_CONTROL_FAULT_ENABLE, | |
177 | &adap_mdio->CONTROL); | |
c74b2108 | 178 | |
d7e35437 NT |
179 | while (readl(&adap_mdio->CONTROL) & MDIO_CONTROL_IDLE) |
180 | ; | |
c74b2108 SK |
181 | } |
182 | ||
183 | /* | |
184 | * Tries to find an active connected PHY. Returns 1 if address if found. | |
185 | * If no active PHY (or more than one PHY) found returns 0. | |
186 | * Sets active_phy_addr variable. | |
187 | */ | |
fcaac589 | 188 | static int davinci_eth_phy_detect(void) |
c74b2108 SK |
189 | { |
190 | u_int32_t phy_act_state; | |
191 | int i; | |
062fe7d3 MH |
192 | int j; |
193 | unsigned int count = 0; | |
194 | ||
dc02bada HS |
195 | for (i = 0; i < CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT; i++) |
196 | active_phy_addr[i] = 0xff; | |
c74b2108 | 197 | |
062fe7d3 MH |
198 | udelay(1000); |
199 | phy_act_state = readl(&adap_mdio->ALIVE); | |
c74b2108 | 200 | |
d7e35437 | 201 | if (phy_act_state == 0) |
062fe7d3 | 202 | return 0; /* No active PHYs */ |
c74b2108 | 203 | |
fcaac589 | 204 | debug_emac("davinci_eth_phy_detect(), ALIVE = 0x%08x\n", phy_act_state); |
c74b2108 | 205 | |
062fe7d3 | 206 | for (i = 0, j = 0; i < 32; i++) |
c74b2108 | 207 | if (phy_act_state & (1 << i)) { |
062fe7d3 | 208 | count++; |
b6090098 | 209 | if (count <= CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT) { |
dc02bada HS |
210 | active_phy_addr[j++] = i; |
211 | } else { | |
212 | printf("%s: to many PHYs detected.\n", | |
213 | __func__); | |
214 | count = 0; | |
215 | break; | |
216 | } | |
c74b2108 | 217 | } |
c74b2108 | 218 | |
062fe7d3 MH |
219 | num_phy = count; |
220 | ||
221 | return count; | |
c74b2108 SK |
222 | } |
223 | ||
224 | ||
225 | /* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ | |
fcaac589 | 226 | int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) |
c74b2108 SK |
227 | { |
228 | int tmp; | |
229 | ||
d7e35437 NT |
230 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
231 | ; | |
c74b2108 | 232 | |
d7e35437 NT |
233 | writel(MDIO_USERACCESS0_GO | |
234 | MDIO_USERACCESS0_WRITE_READ | | |
235 | ((reg_num & 0x1f) << 21) | | |
236 | ((phy_addr & 0x1f) << 16), | |
237 | &adap_mdio->USERACCESS0); | |
c74b2108 SK |
238 | |
239 | /* Wait for command to complete */ | |
d7e35437 NT |
240 | while ((tmp = readl(&adap_mdio->USERACCESS0)) & MDIO_USERACCESS0_GO) |
241 | ; | |
c74b2108 SK |
242 | |
243 | if (tmp & MDIO_USERACCESS0_ACK) { | |
244 | *data = tmp & 0xffff; | |
245 | return(1); | |
246 | } | |
247 | ||
248 | *data = -1; | |
249 | return(0); | |
250 | } | |
251 | ||
252 | /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ | |
fcaac589 | 253 | int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) |
c74b2108 SK |
254 | { |
255 | ||
d7e35437 NT |
256 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
257 | ; | |
c74b2108 | 258 | |
d7e35437 NT |
259 | writel(MDIO_USERACCESS0_GO | |
260 | MDIO_USERACCESS0_WRITE_WRITE | | |
261 | ((reg_num & 0x1f) << 21) | | |
262 | ((phy_addr & 0x1f) << 16) | | |
263 | (data & 0xffff), | |
264 | &adap_mdio->USERACCESS0); | |
c74b2108 SK |
265 | |
266 | /* Wait for command to complete */ | |
d7e35437 NT |
267 | while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) |
268 | ; | |
c74b2108 SK |
269 | |
270 | return(1); | |
271 | } | |
272 | ||
273 | /* PHY functions for a generic PHY */ | |
274 | static int gen_init_phy(int phy_addr) | |
275 | { | |
276 | int ret = 1; | |
277 | ||
278 | if (gen_get_link_speed(phy_addr)) { | |
279 | /* Try another time */ | |
280 | ret = gen_get_link_speed(phy_addr); | |
281 | } | |
282 | ||
283 | return(ret); | |
284 | } | |
285 | ||
286 | static int gen_is_phy_connected(int phy_addr) | |
287 | { | |
288 | u_int16_t dummy; | |
289 | ||
062fe7d3 MH |
290 | return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); |
291 | } | |
292 | ||
293 | static int get_active_phy(void) | |
294 | { | |
295 | int i; | |
296 | ||
297 | for (i = 0; i < num_phy; i++) | |
298 | if (phy[i].get_link_speed(active_phy_addr[i])) | |
299 | return i; | |
300 | ||
301 | return -1; /* Return error if no link */ | |
c74b2108 SK |
302 | } |
303 | ||
304 | static int gen_get_link_speed(int phy_addr) | |
305 | { | |
306 | u_int16_t tmp; | |
307 | ||
d2607401 SR |
308 | if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp) && |
309 | (tmp & 0x04)) { | |
310 | #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ | |
311 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) | |
7d2fade7 | 312 | davinci_eth_phy_read(phy_addr, MII_LPA, &tmp); |
d2607401 SR |
313 | |
314 | /* Speed doesn't matter, there is no setting for it in EMAC. */ | |
7d2fade7 | 315 | if (tmp & (LPA_100FULL | LPA_10FULL)) { |
d2607401 SR |
316 | /* set EMAC for Full Duplex */ |
317 | writel(EMAC_MACCONTROL_MIIEN_ENABLE | | |
318 | EMAC_MACCONTROL_FULLDUPLEX_ENABLE, | |
319 | &adap_emac->MACCONTROL); | |
320 | } else { | |
321 | /*set EMAC for Half Duplex */ | |
322 | writel(EMAC_MACCONTROL_MIIEN_ENABLE, | |
323 | &adap_emac->MACCONTROL); | |
324 | } | |
325 | ||
7d2fade7 | 326 | if (tmp & (LPA_100FULL | LPA_100HALF)) |
d2607401 SR |
327 | writel(readl(&adap_emac->MACCONTROL) | |
328 | EMAC_MACCONTROL_RMIISPEED_100, | |
329 | &adap_emac->MACCONTROL); | |
330 | else | |
331 | writel(readl(&adap_emac->MACCONTROL) & | |
332 | ~EMAC_MACCONTROL_RMIISPEED_100, | |
333 | &adap_emac->MACCONTROL); | |
334 | #endif | |
c74b2108 | 335 | return(1); |
d2607401 | 336 | } |
c74b2108 SK |
337 | |
338 | return(0); | |
339 | } | |
340 | ||
341 | static int gen_auto_negotiate(int phy_addr) | |
342 | { | |
343 | u_int16_t tmp; | |
cc4bd47f MH |
344 | u_int16_t val; |
345 | unsigned long cntr = 0; | |
346 | ||
347 | if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) | |
348 | return 0; | |
349 | ||
350 | val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE | | |
351 | BMCR_SPEED100; | |
352 | davinci_eth_phy_write(phy_addr, MII_BMCR, val); | |
353 | ||
354 | if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val)) | |
355 | return 0; | |
356 | ||
357 | val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | | |
358 | ADVERTISE_10HALF); | |
359 | davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val); | |
c74b2108 | 360 | |
8ef583a0 | 361 | if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) |
c74b2108 SK |
362 | return(0); |
363 | ||
364 | /* Restart Auto_negotiation */ | |
cc4bd47f | 365 | tmp |= BMCR_ANRESTART; |
8ef583a0 | 366 | davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); |
c74b2108 SK |
367 | |
368 | /*check AutoNegotiate complete */ | |
cc4bd47f MH |
369 | do { |
370 | udelay(40000); | |
371 | if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) | |
372 | return 0; | |
373 | ||
374 | if (tmp & BMSR_ANEGCOMPLETE) | |
375 | break; | |
376 | ||
377 | cntr++; | |
378 | } while (cntr < 200); | |
379 | ||
8ef583a0 | 380 | if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) |
c74b2108 SK |
381 | return(0); |
382 | ||
8ef583a0 | 383 | if (!(tmp & BMSR_ANEGCOMPLETE)) |
c74b2108 SK |
384 | return(0); |
385 | ||
386 | return(gen_get_link_speed(phy_addr)); | |
387 | } | |
388 | /* End of generic PHY functions */ | |
389 | ||
390 | ||
afaac86f | 391 | #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) |
5700bb63 | 392 | static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) |
c74b2108 | 393 | { |
fcaac589 | 394 | return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); |
c74b2108 SK |
395 | } |
396 | ||
5700bb63 | 397 | static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) |
c74b2108 | 398 | { |
fcaac589 | 399 | return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); |
c74b2108 | 400 | } |
c74b2108 SK |
401 | #endif |
402 | ||
fb1d6332 | 403 | static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) |
d7e35437 NT |
404 | { |
405 | u_int16_t data; | |
406 | ||
fb1d6332 | 407 | if (davinci_eth_phy_read(phy_addr, 0, &data)) { |
d7e35437 NT |
408 | if (data & (1 << 6)) { /* speed selection MSB */ |
409 | /* | |
410 | * Check if link detected is giga-bit | |
411 | * If Gigabit mode detected, enable gigbit in MAC | |
412 | */ | |
4b9b9e7c SP |
413 | writel(readl(&adap_emac->MACCONTROL) | |
414 | EMAC_MACCONTROL_GIGFORCE | | |
415 | EMAC_MACCONTROL_GIGABIT_ENABLE, | |
416 | &adap_emac->MACCONTROL); | |
d7e35437 NT |
417 | } |
418 | } | |
419 | } | |
c74b2108 SK |
420 | |
421 | /* Eth device open */ | |
8453587e | 422 | static int davinci_eth_open(struct eth_device *dev, bd_t *bis) |
c74b2108 SK |
423 | { |
424 | dv_reg_p addr; | |
425 | u_int32_t clkdiv, cnt; | |
426 | volatile emac_desc *rx_desc; | |
062fe7d3 | 427 | int index; |
c74b2108 SK |
428 | |
429 | debug_emac("+ emac_open\n"); | |
430 | ||
431 | /* Reset EMAC module and disable interrupts in wrapper */ | |
d7e35437 NT |
432 | writel(1, &adap_emac->SOFTRESET); |
433 | while (readl(&adap_emac->SOFTRESET) != 0) | |
434 | ; | |
435 | #if defined(DAVINCI_EMAC_VERSION2) | |
436 | writel(1, &adap_ewrap->softrst); | |
437 | while (readl(&adap_ewrap->softrst) != 0) | |
438 | ; | |
439 | #else | |
440 | writel(0, &adap_ewrap->EWCTL); | |
c74b2108 | 441 | for (cnt = 0; cnt < 5; cnt++) { |
d7e35437 | 442 | clkdiv = readl(&adap_ewrap->EWCTL); |
c74b2108 | 443 | } |
d7e35437 | 444 | #endif |
c74b2108 | 445 | |
d2607401 SR |
446 | #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ |
447 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) | |
448 | adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; | |
449 | adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; | |
450 | adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; | |
451 | #endif | |
c74b2108 SK |
452 | rx_desc = emac_rx_desc; |
453 | ||
d7e35437 NT |
454 | writel(1, &adap_emac->TXCONTROL); |
455 | writel(1, &adap_emac->RXCONTROL); | |
c74b2108 | 456 | |
7b37a27e | 457 | davinci_eth_set_mac_addr(dev); |
c74b2108 SK |
458 | |
459 | /* Set DMA 8 TX / 8 RX Head pointers to 0 */ | |
460 | addr = &adap_emac->TX0HDP; | |
461 | for(cnt = 0; cnt < 16; cnt++) | |
d7e35437 | 462 | writel(0, addr++); |
c74b2108 SK |
463 | |
464 | addr = &adap_emac->RX0HDP; | |
465 | for(cnt = 0; cnt < 16; cnt++) | |
d7e35437 | 466 | writel(0, addr++); |
c74b2108 SK |
467 | |
468 | /* Clear Statistics (do this before setting MacControl register) */ | |
469 | addr = &adap_emac->RXGOODFRAMES; | |
470 | for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) | |
d7e35437 | 471 | writel(0, addr++); |
c74b2108 SK |
472 | |
473 | /* No multicast addressing */ | |
d7e35437 NT |
474 | writel(0, &adap_emac->MACHASH1); |
475 | writel(0, &adap_emac->MACHASH2); | |
c74b2108 SK |
476 | |
477 | /* Create RX queue and set receive process in place */ | |
478 | emac_rx_active_head = emac_rx_desc; | |
479 | for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { | |
82b77217 | 480 | rx_desc->next = BD_TO_HW((u_int32_t)(rx_desc + 1)); |
2aa87202 | 481 | rx_desc->buffer = &emac_rx_buffers[cnt * EMAC_RXBUF_SIZE]; |
c74b2108 SK |
482 | rx_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; |
483 | rx_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; | |
484 | rx_desc++; | |
485 | } | |
486 | ||
d7e35437 | 487 | /* Finalize the rx desc list */ |
c74b2108 SK |
488 | rx_desc--; |
489 | rx_desc->next = 0; | |
490 | emac_rx_active_tail = rx_desc; | |
491 | emac_rx_queue_active = 1; | |
492 | ||
2aa87202 IY |
493 | davinci_flush_rx_descs(); |
494 | ||
c74b2108 | 495 | /* Enable TX/RX */ |
d7e35437 NT |
496 | writel(EMAC_MAX_ETHERNET_PKT_SIZE, &adap_emac->RXMAXLEN); |
497 | writel(0, &adap_emac->RXBUFFEROFFSET); | |
c74b2108 | 498 | |
d7e35437 NT |
499 | /* |
500 | * No fancy configs - Use this for promiscous debug | |
501 | * - EMAC_RXMBPENABLE_RXCAFEN_ENABLE | |
502 | */ | |
503 | writel(EMAC_RXMBPENABLE_RXBROADEN, &adap_emac->RXMBPENABLE); | |
c74b2108 SK |
504 | |
505 | /* Enable ch 0 only */ | |
d7e35437 | 506 | writel(1, &adap_emac->RXUNICASTSET); |
c74b2108 SK |
507 | |
508 | /* Enable MII interface and Full duplex mode */ | |
80deda5d IY |
509 | #if defined(CONFIG_SOC_DA8XX) || \ |
510 | (defined(CONFIG_OMAP34XX) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII)) | |
d7e35437 NT |
511 | writel((EMAC_MACCONTROL_MIIEN_ENABLE | |
512 | EMAC_MACCONTROL_FULLDUPLEX_ENABLE | | |
513 | EMAC_MACCONTROL_RMIISPEED_100), | |
514 | &adap_emac->MACCONTROL); | |
515 | #else | |
516 | writel((EMAC_MACCONTROL_MIIEN_ENABLE | | |
517 | EMAC_MACCONTROL_FULLDUPLEX_ENABLE), | |
518 | &adap_emac->MACCONTROL); | |
519 | #endif | |
c74b2108 SK |
520 | |
521 | /* Init MDIO & get link state */ | |
882ecfa3 | 522 | clkdiv = CONFIG_SYS_EMAC_TI_CLKDIV; |
d7e35437 NT |
523 | writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, |
524 | &adap_mdio->CONTROL); | |
525 | ||
526 | /* We need to wait for MDIO to start */ | |
527 | udelay(1000); | |
c74b2108 | 528 | |
062fe7d3 MH |
529 | index = get_active_phy(); |
530 | if (index == -1) | |
c74b2108 SK |
531 | return(0); |
532 | ||
fb1d6332 | 533 | emac_gigabit_enable(active_phy_addr[index]); |
d7e35437 | 534 | |
c74b2108 | 535 | /* Start receive process */ |
82b77217 | 536 | writel(BD_TO_HW((u_int32_t)emac_rx_desc), &adap_emac->RX0HDP); |
c74b2108 SK |
537 | |
538 | debug_emac("- emac_open\n"); | |
539 | ||
540 | return(1); | |
541 | } | |
542 | ||
543 | /* EMAC Channel Teardown */ | |
fcaac589 | 544 | static void davinci_eth_ch_teardown(int ch) |
c74b2108 SK |
545 | { |
546 | dv_reg dly = 0xff; | |
547 | dv_reg cnt; | |
548 | ||
549 | debug_emac("+ emac_ch_teardown\n"); | |
550 | ||
551 | if (ch == EMAC_CH_TX) { | |
552 | /* Init TX channel teardown */ | |
ba511f77 | 553 | writel(0, &adap_emac->TXTEARDOWN); |
d7e35437 NT |
554 | do { |
555 | /* | |
556 | * Wait here for Tx teardown completion interrupt to | |
557 | * occur. Note: A task delay can be called here to pend | |
558 | * rather than occupying CPU cycles - anyway it has | |
559 | * been found that teardown takes very few cpu cycles | |
560 | * and does not affect functionality | |
561 | */ | |
562 | dly--; | |
563 | udelay(1); | |
564 | if (dly == 0) | |
53677ef1 | 565 | break; |
d7e35437 NT |
566 | cnt = readl(&adap_emac->TX0CP); |
567 | } while (cnt != 0xfffffffc); | |
568 | writel(cnt, &adap_emac->TX0CP); | |
569 | writel(0, &adap_emac->TX0HDP); | |
c74b2108 SK |
570 | } else { |
571 | /* Init RX channel teardown */ | |
ba511f77 | 572 | writel(0, &adap_emac->RXTEARDOWN); |
d7e35437 NT |
573 | do { |
574 | /* | |
575 | * Wait here for Rx teardown completion interrupt to | |
576 | * occur. Note: A task delay can be called here to pend | |
577 | * rather than occupying CPU cycles - anyway it has | |
578 | * been found that teardown takes very few cpu cycles | |
579 | * and does not affect functionality | |
580 | */ | |
581 | dly--; | |
582 | udelay(1); | |
583 | if (dly == 0) | |
53677ef1 | 584 | break; |
d7e35437 NT |
585 | cnt = readl(&adap_emac->RX0CP); |
586 | } while (cnt != 0xfffffffc); | |
587 | writel(cnt, &adap_emac->RX0CP); | |
588 | writel(0, &adap_emac->RX0HDP); | |
c74b2108 SK |
589 | } |
590 | ||
591 | debug_emac("- emac_ch_teardown\n"); | |
592 | } | |
593 | ||
594 | /* Eth device close */ | |
8453587e | 595 | static void davinci_eth_close(struct eth_device *dev) |
c74b2108 SK |
596 | { |
597 | debug_emac("+ emac_close\n"); | |
598 | ||
fcaac589 SP |
599 | davinci_eth_ch_teardown(EMAC_CH_TX); /* TX Channel teardown */ |
600 | davinci_eth_ch_teardown(EMAC_CH_RX); /* RX Channel teardown */ | |
c74b2108 SK |
601 | |
602 | /* Reset EMAC module and disable interrupts in wrapper */ | |
d7e35437 NT |
603 | writel(1, &adap_emac->SOFTRESET); |
604 | #if defined(DAVINCI_EMAC_VERSION2) | |
605 | writel(1, &adap_ewrap->softrst); | |
606 | #else | |
607 | writel(0, &adap_ewrap->EWCTL); | |
608 | #endif | |
c74b2108 | 609 | |
d2607401 SR |
610 | #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ |
611 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) | |
612 | adap_ewrap->c0rxen = adap_ewrap->c1rxen = adap_ewrap->c2rxen = 0; | |
613 | adap_ewrap->c0txen = adap_ewrap->c1txen = adap_ewrap->c2txen = 0; | |
614 | adap_ewrap->c0miscen = adap_ewrap->c1miscen = adap_ewrap->c2miscen = 0; | |
615 | #endif | |
c74b2108 | 616 | debug_emac("- emac_close\n"); |
c74b2108 SK |
617 | } |
618 | ||
619 | static int tx_send_loop = 0; | |
620 | ||
621 | /* | |
622 | * This function sends a single packet on the network and returns | |
623 | * positive number (number of bytes transmitted) or negative for error | |
624 | */ | |
8453587e | 625 | static int davinci_eth_send_packet (struct eth_device *dev, |
bbcdefb3 | 626 | void *packet, int length) |
c74b2108 SK |
627 | { |
628 | int ret_status = -1; | |
062fe7d3 | 629 | int index; |
c74b2108 SK |
630 | tx_send_loop = 0; |
631 | ||
062fe7d3 MH |
632 | index = get_active_phy(); |
633 | if (index == -1) { | |
634 | printf(" WARN: emac_send_packet: No link\n"); | |
c74b2108 SK |
635 | return (ret_status); |
636 | } | |
637 | ||
fb1d6332 | 638 | emac_gigabit_enable(active_phy_addr[index]); |
d7e35437 | 639 | |
c74b2108 | 640 | /* Check packet size and if < EMAC_MIN_ETHERNET_PKT_SIZE, pad it up */ |
53677ef1 | 641 | if (length < EMAC_MIN_ETHERNET_PKT_SIZE) { |
c74b2108 SK |
642 | length = EMAC_MIN_ETHERNET_PKT_SIZE; |
643 | } | |
644 | ||
645 | /* Populate the TX descriptor */ | |
53677ef1 WD |
646 | emac_tx_desc->next = 0; |
647 | emac_tx_desc->buffer = (u_int8_t *) packet; | |
c74b2108 SK |
648 | emac_tx_desc->buff_off_len = (length & 0xffff); |
649 | emac_tx_desc->pkt_flag_len = ((length & 0xffff) | | |
53677ef1 WD |
650 | EMAC_CPPI_SOP_BIT | |
651 | EMAC_CPPI_OWNERSHIP_BIT | | |
652 | EMAC_CPPI_EOP_BIT); | |
2aa87202 IY |
653 | |
654 | flush_dcache_range((unsigned long)packet, | |
655 | (unsigned long)packet + length); | |
656 | davinci_flush_desc(emac_tx_desc); | |
657 | ||
c74b2108 | 658 | /* Send the packet */ |
82b77217 | 659 | writel(BD_TO_HW((unsigned long)emac_tx_desc), &adap_emac->TX0HDP); |
c74b2108 SK |
660 | |
661 | /* Wait for packet to complete or link down */ | |
662 | while (1) { | |
062fe7d3 | 663 | if (!phy[index].get_link_speed(active_phy_addr[index])) { |
fcaac589 | 664 | davinci_eth_ch_teardown (EMAC_CH_TX); |
53677ef1 WD |
665 | return (ret_status); |
666 | } | |
d7e35437 | 667 | |
fb1d6332 | 668 | emac_gigabit_enable(active_phy_addr[index]); |
d7e35437 NT |
669 | |
670 | if (readl(&adap_emac->TXINTSTATRAW) & 0x01) { | |
53677ef1 WD |
671 | ret_status = length; |
672 | break; | |
c74b2108 | 673 | } |
53677ef1 | 674 | tx_send_loop++; |
c74b2108 SK |
675 | } |
676 | ||
53677ef1 | 677 | return (ret_status); |
c74b2108 SK |
678 | } |
679 | ||
680 | /* | |
681 | * This function handles receipt of a packet from the network | |
682 | */ | |
8453587e | 683 | static int davinci_eth_rcv_packet (struct eth_device *dev) |
c74b2108 | 684 | { |
53677ef1 WD |
685 | volatile emac_desc *rx_curr_desc; |
686 | volatile emac_desc *curr_desc; | |
687 | volatile emac_desc *tail_desc; | |
688 | int status, ret = -1; | |
c74b2108 | 689 | |
2aa87202 IY |
690 | davinci_invalidate_rx_descs(); |
691 | ||
c74b2108 SK |
692 | rx_curr_desc = emac_rx_active_head; |
693 | status = rx_curr_desc->pkt_flag_len; | |
694 | if ((rx_curr_desc) && ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0)) { | |
53677ef1 WD |
695 | if (status & EMAC_CPPI_RX_ERROR_FRAME) { |
696 | /* Error in packet - discard it and requeue desc */ | |
697 | printf ("WARN: emac_rcv_pkt: Error in packet\n"); | |
c74b2108 | 698 | } else { |
2aa87202 IY |
699 | unsigned long tmp = (unsigned long)rx_curr_desc->buffer; |
700 | ||
701 | invalidate_dcache_range(tmp, tmp + EMAC_RXBUF_SIZE); | |
53677ef1 WD |
702 | NetReceive (rx_curr_desc->buffer, |
703 | (rx_curr_desc->buff_off_len & 0xffff)); | |
c74b2108 | 704 | ret = rx_curr_desc->buff_off_len & 0xffff; |
53677ef1 | 705 | } |
c74b2108 | 706 | |
53677ef1 | 707 | /* Ack received packet descriptor */ |
82b77217 | 708 | writel(BD_TO_HW((ulong)rx_curr_desc), &adap_emac->RX0CP); |
53677ef1 WD |
709 | curr_desc = rx_curr_desc; |
710 | emac_rx_active_head = | |
82b77217 | 711 | (volatile emac_desc *) (HW_TO_BD(rx_curr_desc->next)); |
c74b2108 | 712 | |
53677ef1 WD |
713 | if (status & EMAC_CPPI_EOQ_BIT) { |
714 | if (emac_rx_active_head) { | |
82b77217 | 715 | writel(BD_TO_HW((ulong)emac_rx_active_head), |
d7e35437 | 716 | &adap_emac->RX0HDP); |
c74b2108 SK |
717 | } else { |
718 | emac_rx_queue_active = 0; | |
53677ef1 | 719 | printf ("INFO:emac_rcv_packet: RX Queue not active\n"); |
c74b2108 SK |
720 | } |
721 | } | |
722 | ||
723 | /* Recycle RX descriptor */ | |
724 | rx_curr_desc->buff_off_len = EMAC_MAX_ETHERNET_PKT_SIZE; | |
725 | rx_curr_desc->pkt_flag_len = EMAC_CPPI_OWNERSHIP_BIT; | |
726 | rx_curr_desc->next = 0; | |
2aa87202 | 727 | davinci_flush_desc(rx_curr_desc); |
c74b2108 SK |
728 | |
729 | if (emac_rx_active_head == 0) { | |
53677ef1 | 730 | printf ("INFO: emac_rcv_pkt: active queue head = 0\n"); |
c74b2108 SK |
731 | emac_rx_active_head = curr_desc; |
732 | emac_rx_active_tail = curr_desc; | |
733 | if (emac_rx_queue_active != 0) { | |
82b77217 | 734 | writel(BD_TO_HW((ulong)emac_rx_active_head), |
d7e35437 | 735 | &adap_emac->RX0HDP); |
53677ef1 | 736 | printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n"); |
c74b2108 SK |
737 | emac_rx_queue_active = 1; |
738 | } | |
739 | } else { | |
740 | tail_desc = emac_rx_active_tail; | |
741 | emac_rx_active_tail = curr_desc; | |
82b77217 | 742 | tail_desc->next = BD_TO_HW((ulong) curr_desc); |
c74b2108 SK |
743 | status = tail_desc->pkt_flag_len; |
744 | if (status & EMAC_CPPI_EOQ_BIT) { | |
2aa87202 | 745 | davinci_flush_desc(tail_desc); |
82b77217 | 746 | writel(BD_TO_HW((ulong)curr_desc), |
d7e35437 | 747 | &adap_emac->RX0HDP); |
c74b2108 SK |
748 | status &= ~EMAC_CPPI_EOQ_BIT; |
749 | tail_desc->pkt_flag_len = status; | |
750 | } | |
2aa87202 | 751 | davinci_flush_desc(tail_desc); |
c74b2108 | 752 | } |
53677ef1 | 753 | return (ret); |
c74b2108 | 754 | } |
53677ef1 | 755 | return (0); |
c74b2108 SK |
756 | } |
757 | ||
8cc13c13 BW |
758 | /* |
759 | * This function initializes the emac hardware. It does NOT initialize | |
760 | * EMAC modules power or pin multiplexors, that is done by board_init() | |
761 | * much earlier in bootup process. Returns 1 on success, 0 otherwise. | |
762 | */ | |
8453587e | 763 | int davinci_emac_initialize(void) |
8cc13c13 BW |
764 | { |
765 | u_int32_t phy_id; | |
766 | u_int16_t tmp; | |
767 | int i; | |
062fe7d3 | 768 | int ret; |
8453587e BW |
769 | struct eth_device *dev; |
770 | ||
771 | dev = malloc(sizeof *dev); | |
772 | ||
773 | if (dev == NULL) | |
774 | return -1; | |
775 | ||
776 | memset(dev, 0, sizeof *dev); | |
2a7d603f | 777 | sprintf(dev->name, "DaVinci-EMAC"); |
8453587e BW |
778 | |
779 | dev->iobase = 0; | |
780 | dev->init = davinci_eth_open; | |
781 | dev->halt = davinci_eth_close; | |
782 | dev->send = davinci_eth_send_packet; | |
783 | dev->recv = davinci_eth_rcv_packet; | |
7b37a27e | 784 | dev->write_hwaddr = davinci_eth_set_mac_addr; |
8453587e BW |
785 | |
786 | eth_register(dev); | |
8cc13c13 BW |
787 | |
788 | davinci_eth_mdio_enable(); | |
789 | ||
19fdf9a1 HS |
790 | /* let the EMAC detect the PHYs */ |
791 | udelay(5000); | |
792 | ||
8cc13c13 | 793 | for (i = 0; i < 256; i++) { |
d7e35437 | 794 | if (readl(&adap_mdio->ALIVE)) |
8cc13c13 | 795 | break; |
062fe7d3 | 796 | udelay(1000); |
8cc13c13 BW |
797 | } |
798 | ||
799 | if (i >= 256) { | |
800 | printf("No ETH PHY detected!!!\n"); | |
801 | return(0); | |
802 | } | |
803 | ||
062fe7d3 MH |
804 | /* Find if PHY(s) is/are connected */ |
805 | ret = davinci_eth_phy_detect(); | |
806 | if (!ret) | |
8cc13c13 | 807 | return(0); |
062fe7d3 | 808 | else |
dc02bada | 809 | debug_emac(" %d ETH PHY detected\n", ret); |
8cc13c13 BW |
810 | |
811 | /* Get PHY ID and initialize phy_ops for a detected PHY */ | |
062fe7d3 MH |
812 | for (i = 0; i < num_phy; i++) { |
813 | if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1, | |
814 | &tmp)) { | |
815 | active_phy_addr[i] = 0xff; | |
816 | continue; | |
817 | } | |
c74b2108 | 818 | |
062fe7d3 | 819 | phy_id = (tmp << 16) & 0xffff0000; |
8cc13c13 | 820 | |
062fe7d3 MH |
821 | if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2, |
822 | &tmp)) { | |
823 | active_phy_addr[i] = 0xff; | |
824 | continue; | |
825 | } | |
8cc13c13 | 826 | |
062fe7d3 | 827 | phy_id |= tmp & 0x0000ffff; |
8cc13c13 | 828 | |
062fe7d3 | 829 | switch (phy_id) { |
918588cf | 830 | #ifdef PHY_KSZ8873 |
062fe7d3 MH |
831 | case PHY_KSZ8873: |
832 | sprintf(phy[i].name, "KSZ8873 @ 0x%02x", | |
833 | active_phy_addr[i]); | |
834 | phy[i].init = ksz8873_init_phy; | |
835 | phy[i].is_phy_connected = ksz8873_is_phy_connected; | |
836 | phy[i].get_link_speed = ksz8873_get_link_speed; | |
837 | phy[i].auto_negotiate = ksz8873_auto_negotiate; | |
838 | break; | |
918588cf IY |
839 | #endif |
840 | #ifdef PHY_LXT972 | |
8cc13c13 | 841 | case PHY_LXT972: |
062fe7d3 MH |
842 | sprintf(phy[i].name, "LXT972 @ 0x%02x", |
843 | active_phy_addr[i]); | |
844 | phy[i].init = lxt972_init_phy; | |
845 | phy[i].is_phy_connected = lxt972_is_phy_connected; | |
846 | phy[i].get_link_speed = lxt972_get_link_speed; | |
847 | phy[i].auto_negotiate = lxt972_auto_negotiate; | |
8cc13c13 | 848 | break; |
918588cf IY |
849 | #endif |
850 | #ifdef PHY_DP83848 | |
8cc13c13 | 851 | case PHY_DP83848: |
062fe7d3 MH |
852 | sprintf(phy[i].name, "DP83848 @ 0x%02x", |
853 | active_phy_addr[i]); | |
854 | phy[i].init = dp83848_init_phy; | |
855 | phy[i].is_phy_connected = dp83848_is_phy_connected; | |
856 | phy[i].get_link_speed = dp83848_get_link_speed; | |
857 | phy[i].auto_negotiate = dp83848_auto_negotiate; | |
8cc13c13 | 858 | break; |
918588cf IY |
859 | #endif |
860 | #ifdef PHY_ET1011C | |
840f8923 | 861 | case PHY_ET1011C: |
062fe7d3 MH |
862 | sprintf(phy[i].name, "ET1011C @ 0x%02x", |
863 | active_phy_addr[i]); | |
864 | phy[i].init = gen_init_phy; | |
865 | phy[i].is_phy_connected = gen_is_phy_connected; | |
866 | phy[i].get_link_speed = et1011c_get_link_speed; | |
867 | phy[i].auto_negotiate = gen_auto_negotiate; | |
840f8923 | 868 | break; |
918588cf | 869 | #endif |
8cc13c13 | 870 | default: |
062fe7d3 MH |
871 | sprintf(phy[i].name, "GENERIC @ 0x%02x", |
872 | active_phy_addr[i]); | |
873 | phy[i].init = gen_init_phy; | |
874 | phy[i].is_phy_connected = gen_is_phy_connected; | |
875 | phy[i].get_link_speed = gen_get_link_speed; | |
876 | phy[i].auto_negotiate = gen_auto_negotiate; | |
877 | } | |
8cc13c13 | 878 | |
e0297a55 | 879 | debug("Ethernet PHY: %s\n", phy[i].name); |
8cc13c13 | 880 | |
062fe7d3 MH |
881 | miiphy_register(phy[i].name, davinci_mii_phy_read, |
882 | davinci_mii_phy_write); | |
883 | } | |
b78375a8 RS |
884 | |
885 | #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ | |
de575502 BR |
886 | defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \ |
887 | !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE) | |
b78375a8 RS |
888 | for (i = 0; i < num_phy; i++) { |
889 | if (phy[i].is_phy_connected(i)) | |
890 | phy[i].auto_negotiate(i); | |
891 | } | |
892 | #endif | |
8cc13c13 BW |
893 | return(1); |
894 | } |