projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5b1b1883 VK |
1 | /* |
| 2 | * (C) Copyright 2010 | |
| 3 | * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | #ifndef _DW_ETH_H | |
| 25 | #define _DW_ETH_H | |
| 26 | ||
| 27 | #define CONFIG_TX_DESCR_NUM 16 | |
| 28 | #define CONFIG_RX_DESCR_NUM 16 | |
| 29 | #define CONFIG_ETH_BUFSIZE 2048 | |
| 30 | #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) | |
| 31 | #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) | |
| 32 | ||
| 33 | #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) | |
| 34 | #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) | |
| 35 | #define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) | |
| 36 | #define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ) | |
| 37 | ||
| 38 | struct eth_mac_regs { | |
| 39 | u32 conf; /* 0x00 */ | |
| 40 | u32 framefilt; /* 0x04 */ | |
| 41 | u32 hashtablehigh; /* 0x08 */ | |
| 42 | u32 hashtablelow; /* 0x0c */ | |
| 43 | u32 miiaddr; /* 0x10 */ | |
| 44 | u32 miidata; /* 0x14 */ | |
| 45 | u32 flowcontrol; /* 0x18 */ | |
| 46 | u32 vlantag; /* 0x1c */ | |
| 47 | u32 version; /* 0x20 */ | |
| 48 | u8 reserved_1[20]; | |
| 49 | u32 intreg; /* 0x38 */ | |
| 50 | u32 intmask; /* 0x3c */ | |
| 51 | u32 macaddr0hi; /* 0x40 */ | |
| 52 | u32 macaddr0lo; /* 0x44 */ | |
| 53 | }; | |
| 54 | ||
| 55 | /* MAC configuration register definitions */ | |
| 56 | #define FRAMEBURSTENABLE (1 << 21) | |
| 57 | #define MII_PORTSELECT (1 << 15) | |
| 58 | #define FES_100 (1 << 14) | |
| 59 | #define DISABLERXOWN (1 << 13) | |
| 60 | #define FULLDPLXMODE (1 << 11) | |
| 61 | #define RXENABLE (1 << 2) | |
| 62 | #define TXENABLE (1 << 3) | |
| 63 | ||
| 64 | /* MII address register definitions */ | |
| 65 | #define MII_BUSY (1 << 0) | |
| 66 | #define MII_WRITE (1 << 1) | |
| 67 | #define MII_CLKRANGE_60_100M (0) | |
| 68 | #define MII_CLKRANGE_100_150M (0x4) | |
| 69 | #define MII_CLKRANGE_20_35M (0x8) | |
| 70 | #define MII_CLKRANGE_35_60M (0xC) | |
| 71 | #define MII_CLKRANGE_150_250M (0x10) | |
| 72 | #define MII_CLKRANGE_250_300M (0x14) | |
| 73 | ||
| 74 | #define MIIADDRSHIFT (11) | |
| 75 | #define MIIREGSHIFT (6) | |
| 76 | #define MII_REGMSK (0x1F << 6) | |
| 77 | #define MII_ADDRMSK (0x1F << 11) | |
| 78 | ||
| 79 | ||
| 80 | struct eth_dma_regs { | |
| 81 | u32 busmode; /* 0x00 */ | |
| 82 | u32 txpolldemand; /* 0x04 */ | |
| 83 | u32 rxpolldemand; /* 0x08 */ | |
| 84 | u32 rxdesclistaddr; /* 0x0c */ | |
| 85 | u32 txdesclistaddr; /* 0x10 */ | |
| 86 | u32 status; /* 0x14 */ | |
| 87 | u32 opmode; /* 0x18 */ | |
| 88 | u32 intenable; /* 0x1c */ | |
| 89 | u8 reserved[40]; | |
| 90 | u32 currhosttxdesc; /* 0x48 */ | |
| 91 | u32 currhostrxdesc; /* 0x4c */ | |
| 92 | u32 currhosttxbuffaddr; /* 0x50 */ | |
| 93 | u32 currhostrxbuffaddr; /* 0x54 */ | |
| 94 | }; | |
| 95 | ||
| 96 | #define DW_DMA_BASE_OFFSET (0x1000) | |
| 97 | ||
| 98 | /* Bus mode register definitions */ | |
| 99 | #define FIXEDBURST (1 << 16) | |
| 100 | #define PRIORXTX_41 (3 << 14) | |
| 101 | #define PRIORXTX_31 (2 << 14) | |
| 102 | #define PRIORXTX_21 (1 << 14) | |
| 103 | #define PRIORXTX_11 (0 << 14) | |
| 104 | #define BURST_1 (1 << 8) | |
| 105 | #define BURST_2 (2 << 8) | |
| 106 | #define BURST_4 (4 << 8) | |
| 107 | #define BURST_8 (8 << 8) | |
| 108 | #define BURST_16 (16 << 8) | |
| 109 | #define BURST_32 (32 << 8) | |
| 110 | #define RXHIGHPRIO (1 << 1) | |
| 111 | #define DMAMAC_SRST (1 << 0) | |
| 112 | ||
| 113 | /* Poll demand definitions */ | |
| 114 | #define POLL_DATA (0xFFFFFFFF) | |
| 115 | ||
| 116 | /* Operation mode definitions */ | |
| 117 | #define STOREFORWARD (1 << 21) | |
| 118 | #define FLUSHTXFIFO (1 << 20) | |
| 119 | #define TXSTART (1 << 13) | |
| 120 | #define TXSECONDFRAME (1 << 2) | |
| 121 | #define RXSTART (1 << 1) | |
| 122 | ||
| 123 | /* Descriptior related definitions */ | |
| 97a6caa6 | 124 | #define MAC_MAX_FRAME_SZ (1600) |
| 5b1b1883 VK |
125 | |
| 126 | struct dmamacdescr { | |
| 127 | u32 txrx_status; | |
| 128 | u32 dmamac_cntl; | |
| 129 | void *dmamac_addr; | |
| 130 | struct dmamacdescr *dmamac_next; | |
| 131 | }; | |
| 132 | ||
| 133 | /* | |
| 134 | * txrx_status definitions | |
| 135 | */ | |
| 136 | ||
| 137 | /* tx status bits definitions */ | |
| 138 | #if defined(CONFIG_DW_ALTDESCRIPTOR) | |
| 139 | ||
| 140 | #define DESC_TXSTS_OWNBYDMA (1 << 31) | |
| 141 | #define DESC_TXSTS_TXINT (1 << 30) | |
| 142 | #define DESC_TXSTS_TXLAST (1 << 29) | |
| 143 | #define DESC_TXSTS_TXFIRST (1 << 28) | |
| 144 | #define DESC_TXSTS_TXCRCDIS (1 << 27) | |
| 145 | ||
| 146 | #define DESC_TXSTS_TXPADDIS (1 << 26) | |
| 147 | #define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) | |
| 148 | #define DESC_TXSTS_TXRINGEND (1 << 21) | |
| 149 | #define DESC_TXSTS_TXCHAIN (1 << 20) | |
| 150 | #define DESC_TXSTS_MSK (0x1FFFF << 0) | |
| 151 | ||
| 152 | #else | |
| 153 | ||
| 154 | #define DESC_TXSTS_OWNBYDMA (1 << 31) | |
| 155 | #define DESC_TXSTS_MSK (0x1FFFF << 0) | |
| 156 | ||
| 157 | #endif | |
| 158 | ||
| 159 | /* rx status bits definitions */ | |
| 160 | #define DESC_RXSTS_OWNBYDMA (1 << 31) | |
| 161 | #define DESC_RXSTS_DAFILTERFAIL (1 << 30) | |
| 162 | #define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) | |
| 163 | #define DESC_RXSTS_FRMLENSHFT (16) | |
| 164 | ||
| 165 | #define DESC_RXSTS_ERROR (1 << 15) | |
| 166 | #define DESC_RXSTS_RXTRUNCATED (1 << 14) | |
| 167 | #define DESC_RXSTS_SAFILTERFAIL (1 << 13) | |
| 168 | #define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) | |
| 169 | #define DESC_RXSTS_RXDAMAGED (1 << 11) | |
| 170 | #define DESC_RXSTS_RXVLANTAG (1 << 10) | |
| 171 | #define DESC_RXSTS_RXFIRST (1 << 9) | |
| 172 | #define DESC_RXSTS_RXLAST (1 << 8) | |
| 173 | #define DESC_RXSTS_RXIPC_GIANT (1 << 7) | |
| 174 | #define DESC_RXSTS_RXCOLLISION (1 << 6) | |
| 175 | #define DESC_RXSTS_RXFRAMEETHER (1 << 5) | |
| 176 | #define DESC_RXSTS_RXWATCHDOG (1 << 4) | |
| 177 | #define DESC_RXSTS_RXMIIERROR (1 << 3) | |
| 178 | #define DESC_RXSTS_RXDRIBBLING (1 << 2) | |
| 179 | #define DESC_RXSTS_RXCRC (1 << 1) | |
| 180 | ||
| 181 | /* | |
| 182 | * dmamac_cntl definitions | |
| 183 | */ | |
| 184 | ||
| 185 | /* tx control bits definitions */ | |
| 186 | #if defined(CONFIG_DW_ALTDESCRIPTOR) | |
| 187 | ||
| 188 | #define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0) | |
| 189 | #define DESC_TXCTRL_SIZE1SHFT (0) | |
| 190 | #define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16) | |
| 191 | #define DESC_TXCTRL_SIZE2SHFT (16) | |
| 192 | ||
| 193 | #else | |
| 194 | ||
| 195 | #define DESC_TXCTRL_TXINT (1 << 31) | |
| 196 | #define DESC_TXCTRL_TXLAST (1 << 30) | |
| 197 | #define DESC_TXCTRL_TXFIRST (1 << 29) | |
| 198 | #define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) | |
| 199 | #define DESC_TXCTRL_TXCRCDIS (1 << 26) | |
| 200 | #define DESC_TXCTRL_TXRINGEND (1 << 25) | |
| 201 | #define DESC_TXCTRL_TXCHAIN (1 << 24) | |
| 202 | ||
| 203 | #define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) | |
| 204 | #define DESC_TXCTRL_SIZE1SHFT (0) | |
| 205 | #define DESC_TXCTRL_SIZE2MASK (0x7FF << 11) | |
| 206 | #define DESC_TXCTRL_SIZE2SHFT (11) | |
| 207 | ||
| 208 | #endif | |
| 209 | ||
| 210 | /* rx control bits definitions */ | |
| 211 | #if defined(CONFIG_DW_ALTDESCRIPTOR) | |
| 212 | ||
| 213 | #define DESC_RXCTRL_RXINTDIS (1 << 31) | |
| 214 | #define DESC_RXCTRL_RXRINGEND (1 << 15) | |
| 215 | #define DESC_RXCTRL_RXCHAIN (1 << 14) | |
| 216 | ||
| 217 | #define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) | |
| 218 | #define DESC_RXCTRL_SIZE1SHFT (0) | |
| 219 | #define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16) | |
| 220 | #define DESC_RXCTRL_SIZE2SHFT (16) | |
| 221 | ||
| 222 | #else | |
| 223 | ||
| 224 | #define DESC_RXCTRL_RXINTDIS (1 << 31) | |
| 225 | #define DESC_RXCTRL_RXRINGEND (1 << 25) | |
| 226 | #define DESC_RXCTRL_RXCHAIN (1 << 24) | |
| 227 | ||
| 228 | #define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) | |
| 229 | #define DESC_RXCTRL_SIZE1SHFT (0) | |
| 230 | #define DESC_RXCTRL_SIZE2MASK (0x7FF << 11) | |
| 231 | #define DESC_RXCTRL_SIZE2SHFT (11) | |
| 232 | ||
| 233 | #endif | |
| 234 | ||
| 235 | struct dw_eth_dev { | |
| 236 | u32 address; | |
| 237 | u32 speed; | |
| 238 | u32 duplex; | |
| 239 | u32 tx_currdescnum; | |
| 240 | u32 rx_currdescnum; | |
| 13edd170 | 241 | u32 phy_configured; |
| 5b1b1883 VK |
242 | u32 padding; |
| 243 | ||
| 244 | struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; | |
| 245 | struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; | |
| 246 | ||
| 247 | char txbuffs[TX_TOTAL_BUFSIZE]; | |
| 248 | char rxbuffs[RX_TOTAL_BUFSIZE]; | |
| 249 | ||
| 250 | struct eth_mac_regs *mac_regs_p; | |
| 251 | struct eth_dma_regs *dma_regs_p; | |
| 252 | ||
| 253 | struct eth_device *dev; | |
| 254 | } __attribute__ ((aligned(8))); | |
| 255 | ||
| 256 | /* Speed specific definitions */ | |
| 257 | #define SPEED_10M 1 | |
| 258 | #define SPEED_100M 2 | |
| 259 | #define SPEED_1000M 3 | |
| 260 | ||
| 261 | /* Duplex mode specific definitions */ | |
| 262 | #define HALF_DUPLEX 1 | |
| 263 | #define FULL_DUPLEX 2 | |
| 264 | ||
| 265 | #endif |