[people/ms/u-boot.git] / drivers / net / fm / b4860.c

/*
 * Copyright 2012 Freescale Semiconductor, Inc.
 *	Roy Zang <tie-fei.zang@freescale.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#include <hwconfig.h>

u32 port_to_devdisr[] = {
	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
	[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
	[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
	[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
	[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
	[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
	[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
	[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
};

static int is_device_disabled(enum fm_port port)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 devdisr2 = in_be32(&gur->devdisr2);

	return port_to_devdisr[port] & devdisr2;
}

void fman_disable_port(enum fm_port port)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}

void fman_enable_port(enum fm_port port)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}

phy_interface_t fman_port_enet_if(enum fm_port port)
{
#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
	u32 serdes2_prtcl;
	char buffer[HWCONFIG_BUFFER_SIZE];
	char *buf = NULL;
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif

	if (is_device_disabled(port))
		return PHY_INTERFACE_MODE_NONE;

	/*B4860 has two 10Gig Mac*/
	if ((port == FM1_10GEC1 || port == FM1_10GEC2)	&&
	    ((is_serdes_configured(XAUI_FM1_MAC9))	||
	     #if (!defined(CONFIG_TARGET_B4860QDS) && \
		  !defined(CONFIG_TARGET_B4R420QDS))
	     (is_serdes_configured(XFI_FM1_MAC9))	||
	     (is_serdes_configured(XFI_FM1_MAC10))	||
	     #endif
	     (is_serdes_configured(XAUI_FM1_MAC10))
	     ))
		return PHY_INTERFACE_MODE_XGMII;

#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
			FSL_CORENET2_RCWSR4_SRDS2_PRTCL;

	if (serdes2_prtcl) {
		serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
		switch (serdes2_prtcl) {
		case 0x80:
		case 0x81:
		case 0x82:
		case 0x83:
		case 0x84:
		case 0x85:
		case 0x86:
		case 0x87:
		case 0x88:
		case 0x89:
		case 0x8a:
		case 0x8b:
		case 0x8c:
		case 0x8d:
		case 0x8e:
		case 0xb1:
		case 0xb2:
			/*
			 * Extract hwconfig from environment since environment
			 * is not setup yet
			 */
			env_get_f("hwconfig", buffer, sizeof(buffer));
			buf = buffer;

			/* check if XFI interface enable in hwconfig for 10g */
			if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
						  "sfp_amc", "sfp", buf)) {
				if ((port == FM1_10GEC1 ||
				     port == FM1_10GEC2) &&
				    ((is_serdes_configured(XFI_FM1_MAC9)) ||
				    (is_serdes_configured(XFI_FM1_MAC10))))
					return PHY_INTERFACE_MODE_XGMII;
				else if ((port == FM1_DTSEC1) ||
					 (port == FM1_DTSEC2) ||
					 (port == FM1_DTSEC3) ||
					 (port == FM1_DTSEC4))
					return PHY_INTERFACE_MODE_NONE;
			}
		}
	}
#endif

	/* Fix me need to handle RGMII here first */

	switch (port) {
	case FM1_DTSEC1:
	case FM1_DTSEC2:
	case FM1_DTSEC3:
	case FM1_DTSEC4:
	case FM1_DTSEC5:
	case FM1_DTSEC6:
		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
			return PHY_INTERFACE_MODE_SGMII;
		break;
	default:
		return PHY_INTERFACE_MODE_NONE;
	}

	return PHY_INTERFACE_MODE_NONE;
}
Commit	Line	Data
e394ceb1 PA	1	/*
	2	* Copyright 2012 Freescale Semiconductor, Inc.
	3	* Roy Zang <tie-fei.zang@freescale.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
e394ceb1 PA	6	*/
	7	#include <common.h>
	8	#include <phy.h>
	9	#include <fm_eth.h>
	10	#include <asm/io.h>
	11	#include <asm/immap_85xx.h>
	12	#include <asm/fsl_serdes.h>
e2544e7a	13	#include <hwconfig.h>
e394ceb1 PA	14
	15	u32 port_to_devdisr[] = {
	16	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
	17	[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
	18	[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
	19	[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
	20	[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
	21	[FM1_DTSEC6] = FSL_CORENET_DEVDISR2_DTSEC1_6,
	22	[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1,
	23	[FM1_10GEC2] = FSL_CORENET_DEVDISR2_10GEC1_2,
	24	};
	25
	26	static int is_device_disabled(enum fm_port port)
	27	{
	28	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	29	u32 devdisr2 = in_be32(&gur->devdisr2);
	30
	31	return port_to_devdisr[port] & devdisr2;
	32	}
	33
	34	void fman_disable_port(enum fm_port port)
	35	{
	36	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	37
	38	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
	39	}
	40
f51d3b71 VL	41	void fman_enable_port(enum fm_port port)
	42	{
	43	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	44
	45	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
	46	}
	47
e394ceb1 PA	48	phy_interface_t fman_port_enet_if(enum fm_port port)
e394ceb1 PA	49	{
d46a4a13	50	#if defined(CONFIG_TARGET_B4860QDS) \|\| defined(CONFIG_TARGET_B4420QDS)
e2544e7a SG	51	u32 serdes2_prtcl;
	52	char buffer[HWCONFIG_BUFFER_SIZE];
	53	char *buf = NULL;
	54	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	55	#endif
	56
e394ceb1 PA	57	if (is_device_disabled(port))
	58	return PHY_INTERFACE_MODE_NONE;
	59
16d88f41 SG	60	/B4860 has two 10Gig Mac/
	61	if ((port == FM1_10GEC1 \|\| port == FM1_10GEC2) &&
	62	((is_serdes_configured(XAUI_FM1_MAC9)) \|\|
d46a4a13 YS	63	#if (!defined(CONFIG_TARGET_B4860QDS) && \
d46a4a13 YS	64	!defined(CONFIG_TARGET_B4R420QDS))
89b94d85	65	(is_serdes_configured(XFI_FM1_MAC9)) \|\|
e2544e7a SG	66	(is_serdes_configured(XFI_FM1_MAC10)) \|\|
	67	#endif
	68	(is_serdes_configured(XAUI_FM1_MAC10))
	69	))
e394ceb1 PA	70	return PHY_INTERFACE_MODE_XGMII;
e394ceb1 PA	71
d46a4a13	72	#if defined(CONFIG_TARGET_B4860QDS) \|\| defined(CONFIG_TARGET_B4420QDS)
e2544e7a SG	73	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
	74	FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
	75
	76	if (serdes2_prtcl) {
	77	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
	78	switch (serdes2_prtcl) {
	79	case 0x80:
	80	case 0x81:
	81	case 0x82:
	82	case 0x83:
	83	case 0x84:
	84	case 0x85:
	85	case 0x86:
	86	case 0x87:
	87	case 0x88:
	88	case 0x89:
	89	case 0x8a:
	90	case 0x8b:
	91	case 0x8c:
	92	case 0x8d:
	93	case 0x8e:
	94	case 0xb1:
	95	case 0xb2:
	96	/*
	97	* Extract hwconfig from environment since environment
	98	* is not setup yet
	99	*/
00caae6d	100	env_get_f("hwconfig", buffer, sizeof(buffer));
e2544e7a SG	101	buf = buffer;
	102
	103	/* check if XFI interface enable in hwconfig for 10g */
	104	if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
	105	"sfp_amc", "sfp", buf)) {
	106	if ((port == FM1_10GEC1 \|\|
	107	port == FM1_10GEC2) &&
	108	((is_serdes_configured(XFI_FM1_MAC9)) \|\|
	109	(is_serdes_configured(XFI_FM1_MAC10))))
	110	return PHY_INTERFACE_MODE_XGMII;
	111	else if ((port == FM1_DTSEC1) \|\|
	112	(port == FM1_DTSEC2) \|\|
	113	(port == FM1_DTSEC3) \|\|
	114	(port == FM1_DTSEC4))
	115	return PHY_INTERFACE_MODE_NONE;
	116	}
	117	}
	118	}
	119	#endif
	120
e394ceb1 PA	121	/* Fix me need to handle RGMII here first */
	122
	123	switch (port) {
	124	case FM1_DTSEC1:
	125	case FM1_DTSEC2:
	126	case FM1_DTSEC3:
	127	case FM1_DTSEC4:
	128	case FM1_DTSEC5:
	129	case FM1_DTSEC6:
	130	if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
	131	return PHY_INTERFACE_MODE_SGMII;
	132	break;
	133	default:
	134	return PHY_INTERFACE_MODE_NONE;
	135	}
	136
	137	return PHY_INTERFACE_MODE_NONE;
	138	}