[people/ms/u-boot.git] / drivers / net / phy / micrel_ksz90x1.c

/*
 * Micrel PHY drivers
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 * author Andy Fleming
 * (C) 2012 NetModule AG, David Andrey, added KSZ9031
 * (C) Copyright 2017 Adaptrum, Inc.
 * Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
 */
#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <micrel.h>
#include <phy.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * KSZ9021 - KSZ9031 common
 */

#define MII_KSZ90xx_PHY_CTL		0x1f
#define MIIM_KSZ90xx_PHYCTL_1000	(1 << 6)
#define MIIM_KSZ90xx_PHYCTL_100		(1 << 5)
#define MIIM_KSZ90xx_PHYCTL_10		(1 << 4)
#define MIIM_KSZ90xx_PHYCTL_DUPLEX	(1 << 3)

/* KSZ9021 PHY Registers */
#define MII_KSZ9021_EXTENDED_CTRL	0x0b
#define MII_KSZ9021_EXTENDED_DATAW	0x0c
#define MII_KSZ9021_EXTENDED_DATAR	0x0d

#define CTRL1000_PREFER_MASTER		(1 << 10)
#define CTRL1000_CONFIG_MASTER		(1 << 11)
#define CTRL1000_MANUAL_CONFIG		(1 << 12)

/* KSZ9031 PHY Registers */
#define MII_KSZ9031_MMD_ACCES_CTRL	0x0d
#define MII_KSZ9031_MMD_REG_DATA	0x0e

static int ksz90xx_startup(struct phy_device *phydev)
{
	unsigned phy_ctl;
	int ret;

	ret = genphy_update_link(phydev);
	if (ret)
		return ret;

	phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);

	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
		phydev->duplex = DUPLEX_FULL;
	else
		phydev->duplex = DUPLEX_HALF;

	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
		phydev->speed = SPEED_1000;
	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
		phydev->speed = SPEED_100;
	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
		phydev->speed = SPEED_10;
	return 0;
}

/* Common OF config bits for KSZ9021 and KSZ9031 */
#ifdef CONFIG_DM_ETH
struct ksz90x1_reg_field {
	const char	*name;
	const u8	size;	/* Size of the bitfield, in bits */
	const u8	off;	/* Offset from bit 0 */
	const u8	dflt;	/* Default value */
};

struct ksz90x1_ofcfg {
	const u16			reg;
	const u16			devad;
	const struct ksz90x1_reg_field	*grp;
	const u16			grpsz;
};

static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
	{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
	{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
};

static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
	{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
	{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
};

static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
	{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
	{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
};

static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
	{ "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
};

static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
	{ "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
};

static int ksz90x1_of_config_group(struct phy_device *phydev,
				   struct ksz90x1_ofcfg *ofcfg)
{
	struct udevice *dev = phydev->dev;
	struct phy_driver *drv = phydev->drv;
	const int ps_to_regval = 60;
	int val[4];
	int i, changed = 0, offset, max;
	u16 regval = 0;

	if (!drv || !drv->writeext)
		return -EOPNOTSUPP;

	for (i = 0; i < ofcfg->grpsz; i++) {
		val[i] = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
					 ofcfg->grp[i].name, -1);
		offset = ofcfg->grp[i].off;
		if (val[i] == -1) {
			/* Default register value for KSZ9021 */
			regval |= ofcfg->grp[i].dflt << offset;
		} else {
			changed = 1;	/* Value was changed in OF */
			/* Calculate the register value and fix corner cases */
			if (val[i] > ps_to_regval * 0xf) {
				max = (1 << ofcfg->grp[i].size) - 1;
				regval |= max << offset;
			} else {
				regval |= (val[i] / ps_to_regval) << offset;
			}
		}
	}

	if (!changed)
		return 0;

	return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
}

static int ksz9021_of_config(struct phy_device *phydev)
{
	struct ksz90x1_ofcfg ofcfg[] = {
		{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
		{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
		{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
	};
	int i, ret = 0;

	for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
		if (ret)
			return ret;
	}

	return 0;
}

static int ksz9031_of_config(struct phy_device *phydev)
{
	struct ksz90x1_ofcfg ofcfg[] = {
		{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
		{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
		{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
		{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
	};
	int i, ret = 0;

	for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
		ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
		if (ret)
			return ret;
	}

	return 0;
}

static int ksz9031_center_flp_timing(struct phy_device *phydev)
{
	struct phy_driver *drv = phydev->drv;
	int ret = 0;

	if (!drv || !drv->writeext)
		return -EOPNOTSUPP;

	ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
	if (ret)
		return ret;

	ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
	return ret;
}

#else /* !CONFIG_DM_ETH */
static int ksz9021_of_config(struct phy_device *phydev)
{
	return 0;
}

static int ksz9031_of_config(struct phy_device *phydev)
{
	return 0;
}

static int ksz9031_center_flp_timing(struct phy_device *phydev)
{
	return 0;
}
#endif

/*
 * KSZ9021
 */
int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
{
	/* extended registers */
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9021_EXTENDED_CTRL, regnum | 0x8000);
	return phy_write(phydev, MDIO_DEVAD_NONE,
			 MII_KSZ9021_EXTENDED_DATAW, val);
}

int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
{
	/* extended registers */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
}


static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
			       int regnum)
{
	return ksz9021_phy_extended_read(phydev, regnum);
}

static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
				int devaddr, int regnum, u16 val)
{
	return ksz9021_phy_extended_write(phydev, regnum, val);
}

static int ksz9021_config(struct phy_device *phydev)
{
	unsigned ctrl1000 = 0;
	const unsigned master = CTRL1000_PREFER_MASTER |
	CTRL1000_CONFIG_MASTER | CTRL1000_MANUAL_CONFIG;
	unsigned features = phydev->drv->features;
	int ret;

	ret = ksz9021_of_config(phydev);
	if (ret)
		return ret;

	if (env_get("disable_giga"))
		features &= ~(SUPPORTED_1000baseT_Half |
		SUPPORTED_1000baseT_Full);
	/* force master mode for 1000BaseT due to chip errata */
	if (features & SUPPORTED_1000baseT_Half)
		ctrl1000 |= ADVERTISE_1000HALF | master;
	if (features & SUPPORTED_1000baseT_Full)
		ctrl1000 |= ADVERTISE_1000FULL | master;
	phydev->advertising = features;
	phydev->supported = features;
	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
	genphy_config_aneg(phydev);
	genphy_restart_aneg(phydev);
	return 0;
}

static struct phy_driver ksz9021_driver = {
	.name = "Micrel ksz9021",
	.uid  = 0x221610,
	.mask = 0xfffff0,
	.features = PHY_GBIT_FEATURES,
	.config = &ksz9021_config,
	.startup = &ksz90xx_startup,
	.shutdown = &genphy_shutdown,
	.writeext = &ksz9021_phy_extwrite,
	.readext = &ksz9021_phy_extread,
};

/*
 * KSZ9031
 */
int ksz9031_phy_extended_write(struct phy_device *phydev,
			       int devaddr, int regnum, u16 mode, u16 val)
{
	/*select register addr for mmd*/
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	/*select register for mmd*/
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_REG_DATA, regnum);
	/*setup mode*/
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, (mode | devaddr));
	/*write the value*/
	return	phy_write(phydev, MDIO_DEVAD_NONE,
			  MII_KSZ9031_MMD_REG_DATA, val);
}

int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
			      int regnum, u16 mode)
{
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_REG_DATA, regnum);
	phy_write(phydev, MDIO_DEVAD_NONE,
		  MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | mode));
	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
}

static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
			       int regnum)
{
	return ksz9031_phy_extended_read(phydev, devaddr, regnum,
					 MII_KSZ9031_MOD_DATA_NO_POST_INC);
}

static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
				int devaddr, int regnum, u16 val)
{
	return ksz9031_phy_extended_write(phydev, devaddr, regnum,
					  MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
}

static int ksz9031_config(struct phy_device *phydev)
{
	int ret;

	ret = ksz9031_of_config(phydev);
	if (ret)
		return ret;
	ret = ksz9031_center_flp_timing(phydev);
	if (ret)
		return ret;

	/* add an option to disable the gigabit feature of this PHY */
	if (env_get("disable_giga")) {
		unsigned features;
		unsigned bmcr;

		/* disable speed 1000 in features supported by the PHY */
		features = phydev->drv->features;
		features &= ~(SUPPORTED_1000baseT_Half |
				SUPPORTED_1000baseT_Full);
		phydev->advertising = phydev->supported = features;

		/* disable speed 1000 in Basic Control Register */
		bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
		bmcr &= ~(1 << 6);
		phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);

		/* disable speed 1000 in 1000Base-T Control Register */
		phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);

		/* start autoneg */
		genphy_config_aneg(phydev);
		genphy_restart_aneg(phydev);

		return 0;
	}

	return genphy_config(phydev);
}

static struct phy_driver ksz9031_driver = {
	.name = "Micrel ksz9031",
	.uid  = 0x221620,
	.mask = 0xfffff0,
	.features = PHY_GBIT_FEATURES,
	.config   = &ksz9031_config,
	.startup  = &ksz90xx_startup,
	.shutdown = &genphy_shutdown,
	.writeext = &ksz9031_phy_extwrite,
	.readext = &ksz9031_phy_extread,
};

int phy_micrel_ksz90x1_init(void)
{
	phy_register(&ksz9021_driver);
	phy_register(&ksz9031_driver);
	return 0;
}
Commit	Line	Data
9082eeac AF	1	/*
	2	* Micrel PHY drivers
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
9082eeac AF	5	*
	6	* Copyright 2010-2011 Freescale Semiconductor, Inc.
	7	* author Andy Fleming
62d7dba7	8	* (C) 2012 NetModule AG, David Andrey, added KSZ9031
d397f7c4 AG	9	* (C) Copyright 2017 Adaptrum, Inc.
d397f7c4 AG	10	* Written by Alexandru Gagniuc <alex.g@adaptrum.com> for Adaptrum, Inc.
9082eeac	11	*/
8682aba7 TK	12	#include <config.h>
8682aba7 TK	13	#include <common.h>
22854bda MV	14	#include <dm.h>
	15	#include <errno.h>
	16	#include <fdtdec.h>
8682aba7	17	#include <micrel.h>
9082eeac AF	18	#include <phy.h>
9082eeac AF	19
22854bda MV	20	DECLARE_GLOBAL_DATA_PTR;
22854bda MV	21
58ec63d6	22	/*
62d7dba7 DA	23	* KSZ9021 - KSZ9031 common
	24	*/
	25
	26	#define MII_KSZ90xx_PHY_CTL 0x1f
	27	#define MIIM_KSZ90xx_PHYCTL_1000 (1 << 6)
	28	#define MIIM_KSZ90xx_PHYCTL_100 (1 << 5)
	29	#define MIIM_KSZ90xx_PHYCTL_10 (1 << 4)
	30	#define MIIM_KSZ90xx_PHYCTL_DUPLEX (1 << 3)
	31
d397f7c4 AG	32	/* KSZ9021 PHY Registers */
	33	#define MII_KSZ9021_EXTENDED_CTRL 0x0b
	34	#define MII_KSZ9021_EXTENDED_DATAW 0x0c
	35	#define MII_KSZ9021_EXTENDED_DATAR 0x0d
	36
	37	#define CTRL1000_PREFER_MASTER (1 << 10)
	38	#define CTRL1000_CONFIG_MASTER (1 << 11)
	39	#define CTRL1000_MANUAL_CONFIG (1 << 12)
	40
	41	/* KSZ9031 PHY Registers */
	42	#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
	43	#define MII_KSZ9031_MMD_REG_DATA 0x0e
	44
62d7dba7 DA	45	static int ksz90xx_startup(struct phy_device *phydev)
	46	{
	47	unsigned phy_ctl;
b733c278 MS	48	int ret;
	49
	50	ret = genphy_update_link(phydev);
	51	if (ret)
	52	return ret;
	53
62d7dba7 DA	54	phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL);
	55
	56	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_DUPLEX)
	57	phydev->duplex = DUPLEX_FULL;
	58	else
	59	phydev->duplex = DUPLEX_HALF;
	60
	61	if (phy_ctl & MIIM_KSZ90xx_PHYCTL_1000)
	62	phydev->speed = SPEED_1000;
	63	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_100)
	64	phydev->speed = SPEED_100;
	65	else if (phy_ctl & MIIM_KSZ90xx_PHYCTL_10)
	66	phydev->speed = SPEED_10;
	67	return 0;
	68	}
62d7dba7	69
22854bda	70	/* Common OF config bits for KSZ9021 and KSZ9031 */
22854bda MV	71	#ifdef CONFIG_DM_ETH
	72	struct ksz90x1_reg_field {
	73	const char *name;
	74	const u8 size; /* Size of the bitfield, in bits */
	75	const u8 off; /* Offset from bit 0 */
	76	const u8 dflt; /* Default value */
	77	};
	78
	79	struct ksz90x1_ofcfg {
	80	const u16 reg;
	81	const u16 devad;
	82	const struct ksz90x1_reg_field *grp;
	83	const u16 grpsz;
	84	};
	85
	86	static const struct ksz90x1_reg_field ksz90x1_rxd_grp[] = {
	87	{ "rxd0-skew-ps", 4, 0, 0x7 }, { "rxd1-skew-ps", 4, 4, 0x7 },
	88	{ "rxd2-skew-ps", 4, 8, 0x7 }, { "rxd3-skew-ps", 4, 12, 0x7 }
	89	};
	90
	91	static const struct ksz90x1_reg_field ksz90x1_txd_grp[] = {
	92	{ "txd0-skew-ps", 4, 0, 0x7 }, { "txd1-skew-ps", 4, 4, 0x7 },
	93	{ "txd2-skew-ps", 4, 8, 0x7 }, { "txd3-skew-ps", 4, 12, 0x7 },
	94	};
	95
d397f7c4 AG	96	static const struct ksz90x1_reg_field ksz9021_clk_grp[] = {
	97	{ "txen-skew-ps", 4, 0, 0x7 }, { "txc-skew-ps", 4, 4, 0x7 },
	98	{ "rxdv-skew-ps", 4, 8, 0x7 }, { "rxc-skew-ps", 4, 12, 0x7 },
	99	};
	100
	101	static const struct ksz90x1_reg_field ksz9031_ctl_grp[] = {
	102	{ "txen-skew-ps", 4, 0, 0x7 }, { "rxdv-skew-ps", 4, 4, 0x7 }
	103	};
	104
	105	static const struct ksz90x1_reg_field ksz9031_clk_grp[] = {
	106	{ "rxc-skew-ps", 5, 0, 0xf }, { "txc-skew-ps", 5, 5, 0xf }
	107	};
	108
22854bda MV	109	static int ksz90x1_of_config_group(struct phy_device *phydev,
	110	struct ksz90x1_ofcfg *ofcfg)
	111	{
	112	struct udevice *dev = phydev->dev;
	113	struct phy_driver *drv = phydev->drv;
ff7bd212	114	const int ps_to_regval = 60;
22854bda MV	115	int val[4];
	116	int i, changed = 0, offset, max;
	117	u16 regval = 0;
	118
	119	if (!drv \|\| !drv->writeext)
	120	return -EOPNOTSUPP;
	121
	122	for (i = 0; i < ofcfg->grpsz; i++) {
e160f7d4	123	val[i] = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
22854bda MV	124	ofcfg->grp[i].name, -1);
	125	offset = ofcfg->grp[i].off;
	126	if (val[i] == -1) {
	127	/* Default register value for KSZ9021 */
	128	regval \|= ofcfg->grp[i].dflt << offset;
	129	} else {
	130	changed = 1; /* Value was changed in OF */
	131	/* Calculate the register value and fix corner cases */
	132	if (val[i] > ps_to_regval * 0xf) {
	133	max = (1 << ofcfg->grp[i].size) - 1;
	134	regval \|= max << offset;
	135	} else {
	136	regval \|= (val[i] / ps_to_regval) << offset;
	137	}
	138	}
	139	}
	140
	141	if (!changed)
	142	return 0;
	143
	144	return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval);
	145	}
22854bda MV	146
	147	static int ksz9021_of_config(struct phy_device *phydev)
	148	{
	149	struct ksz90x1_ofcfg ofcfg[] = {
	150	{ MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0, ksz90x1_rxd_grp, 4 },
	151	{ MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0, ksz90x1_txd_grp, 4 },
	152	{ MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0, ksz9021_clk_grp, 4 },
	153	};
	154	int i, ret = 0;
	155
75c056d7	156	for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
22854bda MV	157	ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
	158	if (ret)
	159	return ret;
75c056d7	160	}
22854bda MV	161
	162	return 0;
	163	}
d397f7c4 AG	164
	165	static int ksz9031_of_config(struct phy_device *phydev)
	166	{
	167	struct ksz90x1_ofcfg ofcfg[] = {
	168	{ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 2, ksz9031_ctl_grp, 2 },
	169	{ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 2, ksz90x1_rxd_grp, 4 },
	170	{ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 2, ksz90x1_txd_grp, 4 },
	171	{ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 2, ksz9031_clk_grp, 2 },
	172	};
	173	int i, ret = 0;
	174
	175	for (i = 0; i < ARRAY_SIZE(ofcfg); i++) {
	176	ret = ksz90x1_of_config_group(phydev, &(ofcfg[i]));
	177	if (ret)
	178	return ret;
	179	}
	180
	181	return 0;
	182	}
	183
	184	static int ksz9031_center_flp_timing(struct phy_device *phydev)
	185	{
	186	struct phy_driver *drv = phydev->drv;
	187	int ret = 0;
	188
	189	if (!drv \|\| !drv->writeext)
	190	return -EOPNOTSUPP;
	191
	192	ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_LO, 0x1A80);
	193	if (ret)
	194	return ret;
	195
	196	ret = drv->writeext(phydev, 0, 0, MII_KSZ9031_FLP_BURST_TX_HI, 0x6);
	197	return ret;
	198	}
	199
	200	#else /* !CONFIG_DM_ETH */
22854bda MV	201	static int ksz9021_of_config(struct phy_device *phydev)
	202	{
	203	return 0;
	204	}
d397f7c4 AG	205
	206	static int ksz9031_of_config(struct phy_device *phydev)
	207	{
	208	return 0;
	209	}
	210
	211	static int ksz9031_center_flp_timing(struct phy_device *phydev)
	212	{
	213	return 0;
	214	}
22854bda MV	215	#endif
22854bda MV	216
d397f7c4 AG	217	/*
	218	* KSZ9021
	219	*/
8682aba7 TK	220	int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val)
	221	{
	222	/* extended registers */
	223	phy_write(phydev, MDIO_DEVAD_NONE,
d397f7c4	224	MII_KSZ9021_EXTENDED_CTRL, regnum \| 0x8000);
8682aba7	225	return phy_write(phydev, MDIO_DEVAD_NONE,
d397f7c4	226	MII_KSZ9021_EXTENDED_DATAW, val);
8682aba7 TK	227	}
	228
	229	int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum)
	230	{
	231	/* extended registers */
	232	phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum);
	233	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
	234	}
	235
9ced16fe SB	236
9ced16fe SB	237	static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
d397f7c4	238	int regnum)
9ced16fe SB	239	{
	240	return ksz9021_phy_extended_read(phydev, regnum);
	241	}
	242
	243	static int ksz9021_phy_extwrite(struct phy_device *phydev, int addr,
d397f7c4	244	int devaddr, int regnum, u16 val)
9ced16fe SB	245	{
	246	return ksz9021_phy_extended_write(phydev, regnum, val);
	247	}
	248
8682aba7 TK	249	static int ksz9021_config(struct phy_device *phydev)
	250	{
	251	unsigned ctrl1000 = 0;
	252	const unsigned master = CTRL1000_PREFER_MASTER \|
d397f7c4	253	CTRL1000_CONFIG_MASTER \| CTRL1000_MANUAL_CONFIG;
8682aba7	254	unsigned features = phydev->drv->features;
22854bda MV	255	int ret;
	256
	257	ret = ksz9021_of_config(phydev);
	258	if (ret)
	259	return ret;
8682aba7	260
00caae6d	261	if (env_get("disable_giga"))
8682aba7	262	features &= ~(SUPPORTED_1000baseT_Half \|
d397f7c4	263	SUPPORTED_1000baseT_Full);
8682aba7 TK	264	/* force master mode for 1000BaseT due to chip errata */
	265	if (features & SUPPORTED_1000baseT_Half)
	266	ctrl1000 \|= ADVERTISE_1000HALF \| master;
	267	if (features & SUPPORTED_1000baseT_Full)
	268	ctrl1000 \|= ADVERTISE_1000FULL \| master;
d397f7c4 AG	269	phydev->advertising = features;
d397f7c4 AG	270	phydev->supported = features;
8682aba7 TK	271	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
	272	genphy_config_aneg(phydev);
	273	genphy_restart_aneg(phydev);
	274	return 0;
	275	}
	276
8682aba7 TK	277	static struct phy_driver ksz9021_driver = {
	278	.name = "Micrel ksz9021",
	279	.uid = 0x221610,
	280	.mask = 0xfffff0,
	281	.features = PHY_GBIT_FEATURES,
	282	.config = &ksz9021_config,
62d7dba7	283	.startup = &ksz90xx_startup,
8682aba7	284	.shutdown = &genphy_shutdown,
9ced16fe SB	285	.writeext = &ksz9021_phy_extwrite,
9ced16fe SB	286	.readext = &ksz9021_phy_extread,
8682aba7 TK	287	};
8682aba7 TK	288
d397f7c4	289	/*
62d7dba7 DA	290	* KSZ9031
62d7dba7 DA	291	*/
42a7cb50 SL	292	int ksz9031_phy_extended_write(struct phy_device *phydev,
	293	int devaddr, int regnum, u16 mode, u16 val)
	294	{
	295	/select register addr for mmd/
	296	phy_write(phydev, MDIO_DEVAD_NONE,
	297	MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	298	/select register for mmd/
	299	phy_write(phydev, MDIO_DEVAD_NONE,
	300	MII_KSZ9031_MMD_REG_DATA, regnum);
	301	/setup mode/
	302	phy_write(phydev, MDIO_DEVAD_NONE,
	303	MII_KSZ9031_MMD_ACCES_CTRL, (mode \| devaddr));
	304	/write the value/
	305	return phy_write(phydev, MDIO_DEVAD_NONE,
d397f7c4	306	MII_KSZ9031_MMD_REG_DATA, val);
42a7cb50 SL	307	}
	308
	309	int ksz9031_phy_extended_read(struct phy_device *phydev, int devaddr,
	310	int regnum, u16 mode)
	311	{
	312	phy_write(phydev, MDIO_DEVAD_NONE,
	313	MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
	314	phy_write(phydev, MDIO_DEVAD_NONE,
	315	MII_KSZ9031_MMD_REG_DATA, regnum);
	316	phy_write(phydev, MDIO_DEVAD_NONE,
	317	MII_KSZ9031_MMD_ACCES_CTRL, (devaddr \| mode));
	318	return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9031_MMD_REG_DATA);
	319	}
	320
9ced16fe SB	321	static int ksz9031_phy_extread(struct phy_device *phydev, int addr, int devaddr,
	322	int regnum)
	323	{
	324	return ksz9031_phy_extended_read(phydev, devaddr, regnum,
	325	MII_KSZ9031_MOD_DATA_NO_POST_INC);
d397f7c4	326	}
9ced16fe SB	327
	328	static int ksz9031_phy_extwrite(struct phy_device *phydev, int addr,
	329	int devaddr, int regnum, u16 val)
	330	{
	331	return ksz9031_phy_extended_write(phydev, devaddr, regnum,
d397f7c4 AG	332	MII_KSZ9031_MOD_DATA_POST_INC_RW, val);
d397f7c4 AG	333	}
9ced16fe	334
22854bda MV	335	static int ksz9031_config(struct phy_device *phydev)
	336	{
	337	int ret;
ef1f61aa	338
22854bda	339	ret = ksz9031_of_config(phydev);
f018545e AC	340	if (ret)
	341	return ret;
	342	ret = ksz9031_center_flp_timing(phydev);
22854bda MV	343	if (ret)
22854bda MV	344	return ret;
ef1f61aa SB	345
ef1f61aa SB	346	/* add an option to disable the gigabit feature of this PHY */
00caae6d	347	if (env_get("disable_giga")) {
ef1f61aa SB	348	unsigned features;
	349	unsigned bmcr;
	350
	351	/* disable speed 1000 in features supported by the PHY */
	352	features = phydev->drv->features;
	353	features &= ~(SUPPORTED_1000baseT_Half \|
	354	SUPPORTED_1000baseT_Full);
	355	phydev->advertising = phydev->supported = features;
	356
	357	/* disable speed 1000 in Basic Control Register */
	358	bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
	359	bmcr &= ~(1 << 6);
	360	phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr);
	361
	362	/* disable speed 1000 in 1000Base-T Control Register */
	363	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
	364
	365	/* start autoneg */
	366	genphy_config_aneg(phydev);
	367	genphy_restart_aneg(phydev);
	368
	369	return 0;
	370	}
	371
22854bda MV	372	return genphy_config(phydev);
22854bda MV	373	}
9ced16fe	374
62d7dba7 DA	375	static struct phy_driver ksz9031_driver = {
	376	.name = "Micrel ksz9031",
	377	.uid = 0x221620,
e8194d58	378	.mask = 0xfffff0,
62d7dba7	379	.features = PHY_GBIT_FEATURES,
22854bda	380	.config = &ksz9031_config,
62d7dba7 DA	381	.startup = &ksz90xx_startup,
62d7dba7 DA	382	.shutdown = &genphy_shutdown,
9ced16fe SB	383	.writeext = &ksz9031_phy_extwrite,
9ced16fe SB	384	.readext = &ksz9031_phy_extread,
62d7dba7 DA	385	};
62d7dba7 DA	386
d397f7c4	387	int phy_micrel_ksz90x1_init(void)
9082eeac	388	{
8682aba7	389	phy_register(&ksz9021_driver);
62d7dba7	390	phy_register(&ksz9031_driver);
9082eeac AF	391	return 0;
9082eeac AF	392	}