[people/ms/u-boot.git] / drivers / net / xilinx_emaclite.c

/*
 * (C) Copyright 2007-2009 Michal Simek
 * (C) Copyright 2003 Xilinx Inc.
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <net.h>
#include <config.h>
#include <dm.h>
#include <console.h>
#include <malloc.h>
#include <asm/io.h>
#include <phy.h>
#include <miiphy.h>
#include <fdtdec.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

#define ENET_ADDR_LENGTH	6
#define ETH_FCS_LEN		4 /* Octets in the FCS */

/* Xmit complete */
#define XEL_TSR_XMIT_BUSY_MASK		0x00000001UL
/* Xmit interrupt enable bit */
#define XEL_TSR_XMIT_IE_MASK		0x00000008UL
/* Program the MAC address */
#define XEL_TSR_PROGRAM_MASK		0x00000002UL
/* define for programming the MAC address into the EMAC Lite */
#define XEL_TSR_PROG_MAC_ADDR	(XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)

/* Transmit packet length upper byte */
#define XEL_TPLR_LENGTH_MASK_HI		0x0000FF00UL
/* Transmit packet length lower byte */
#define XEL_TPLR_LENGTH_MASK_LO		0x000000FFUL

/* Recv complete */
#define XEL_RSR_RECV_DONE_MASK		0x00000001UL
/* Recv interrupt enable bit */
#define XEL_RSR_RECV_IE_MASK		0x00000008UL

/* MDIO Address Register Bit Masks */
#define XEL_MDIOADDR_REGADR_MASK  0x0000001F	/* Register Address */
#define XEL_MDIOADDR_PHYADR_MASK  0x000003E0	/* PHY Address */
#define XEL_MDIOADDR_PHYADR_SHIFT 5
#define XEL_MDIOADDR_OP_MASK	  0x00000400	/* RD/WR Operation */

/* MDIO Write Data Register Bit Masks */
#define XEL_MDIOWR_WRDATA_MASK	  0x0000FFFF	/* Data to be Written */

/* MDIO Read Data Register Bit Masks */
#define XEL_MDIORD_RDDATA_MASK	  0x0000FFFF	/* Data to be Read */

/* MDIO Control Register Bit Masks */
#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001	/* MDIO Status Mask */
#define XEL_MDIOCTRL_MDIOEN_MASK  0x00000008	/* MDIO Enable */

struct emaclite_regs {
	u32 tx_ping; /* 0x0 - TX Ping buffer */
	u32 reserved1[504];
	u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
	u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
	u32 mdiord;/* 0x7ec - MDIO Read Data Register */
	u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
	u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
	u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
	u32 tx_ping_tsr; /* 0x7fc - Tx status */
	u32 tx_pong; /* 0x800 - TX Pong buffer */
	u32 reserved2[508];
	u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
	u32 reserved3; /* 0xff8 */
	u32 tx_pong_tsr; /* 0xffc - Tx status */
	u32 rx_ping; /* 0x1000 - Receive Buffer */
	u32 reserved4[510];
	u32 rx_ping_rsr; /* 0x17fc - Rx status */
	u32 rx_pong; /* 0x1800 - Receive Buffer */
	u32 reserved5[510];
	u32 rx_pong_rsr; /* 0x1ffc - Rx status */
};

struct xemaclite {
	bool use_rx_pong_buffer_next;	/* Next RX buffer to read from */
	u32 txpp;		/* TX ping pong buffer */
	u32 rxpp;		/* RX ping pong buffer */
	int phyaddr;
	struct emaclite_regs *regs;
	struct phy_device *phydev;
	struct mii_dev *bus;
};

static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */

static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;

	/* Word aligned buffer, no correction needed. */
	to32ptr = (u32 *) destptr;
	while (bytecount > 3) {
		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}
	to8ptr = (u8 *) to32ptr;

	alignbuffer = *from32ptr++;
	from8ptr = (u8 *) &alignbuffer;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;
}

static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
{
	u32 i;
	u32 alignbuffer;
	u32 *to32ptr = (u32 *) destptr;
	u32 *from32ptr;
	u8 *to8ptr;
	u8 *from8ptr;

	from32ptr = (u32 *) srcptr;
	while (bytecount > 3) {

		*to32ptr++ = *from32ptr++;
		bytecount -= 4;
	}

	alignbuffer = 0;
	to8ptr = (u8 *) &alignbuffer;
	from8ptr = (u8 *) from32ptr;

	for (i = 0; i < bytecount; i++)
		*to8ptr++ = *from8ptr++;

	*to32ptr++ = alignbuffer;
}

static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
			bool set, unsigned int timeout)
{
	u32 val;
	unsigned long start = get_timer(0);

	while (1) {
		val = __raw_readl(reg);

		if (!set)
			val = ~val;

		if ((val & mask) == mask)
			return 0;

		if (get_timer(start) > timeout)
			break;

		if (ctrlc()) {
			puts("Abort\n");
			return -EINTR;
		}

		udelay(1);
	}

	debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
	      func, reg, mask, set);

	return -ETIMEDOUT;
}

static int mdio_wait(struct emaclite_regs *regs)
{
	return wait_for_bit(__func__, &regs->mdioctrl,
			    XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
}

static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
		   u16 *data)
{
	struct emaclite_regs *regs = emaclite->regs;

	if (mdio_wait(regs))
		return 1;

	u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
	__raw_writel(XEL_MDIOADDR_OP_MASK
		| ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
		| registernum), &regs->mdioaddr);
	__raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);

	if (mdio_wait(regs))
		return 1;

	/* Read data */
	*data = __raw_readl(&regs->mdiord);
	return 0;
}

static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
		    u16 data)
{
	struct emaclite_regs *regs = emaclite->regs;

	if (mdio_wait(regs))
		return 1;

	/*
	 * Write the PHY address, register number and clear the OP bit in the
	 * MDIO Address register and then write the value into the MDIO Write
	 * Data register. Finally, set the Status bit in the MDIO Control
	 * register to start a MDIO write transaction.
	 */
	u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
	__raw_writel(~XEL_MDIOADDR_OP_MASK
		& ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
		| registernum), &regs->mdioaddr);
	__raw_writel(data, &regs->mdiowr);
	__raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);

	if (mdio_wait(regs))
		return 1;

	return 0;
}

static void emaclite_stop(struct udevice *dev)
{
	debug("eth_stop\n");
}

/* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG  1

/* Mask used to verify certain PHY features (or register contents)
 * in the register above:
 *  0x1000: 10Mbps full duplex support
 *  0x0800: 10Mbps half duplex support
 *  0x0008: Auto-negotiation support
 */
#define PHY_DETECT_MASK 0x1808

static int setup_phy(struct udevice *dev)
{
	int i, ret;
	u16 phyreg;
	struct xemaclite *emaclite = dev_get_priv(dev);
	struct phy_device *phydev;

	u32 supported = SUPPORTED_10baseT_Half |
			SUPPORTED_10baseT_Full |
			SUPPORTED_100baseT_Half |
			SUPPORTED_100baseT_Full;

	if (emaclite->phyaddr != -1) {
		phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
		if ((phyreg != 0xFFFF) &&
		    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
			/* Found a valid PHY address */
			debug("Default phy address %d is valid\n",
			      emaclite->phyaddr);
		} else {
			debug("PHY address is not setup correctly %d\n",
			      emaclite->phyaddr);
			emaclite->phyaddr = -1;
		}
	}

	if (emaclite->phyaddr == -1) {
		/* detect the PHY address */
		for (i = 31; i >= 0; i--) {
			phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
			if ((phyreg != 0xFFFF) &&
			    ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
				/* Found a valid PHY address */
				emaclite->phyaddr = i;
				debug("emaclite: Found valid phy address, %d\n",
				      i);
				break;
			}
		}
	}

	/* interface - look at tsec */
	phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
			     PHY_INTERFACE_MODE_MII);
	/*
	 * Phy can support 1000baseT but device NOT that's why phydev->supported
	 * must be setup for 1000baseT. phydev->advertising setups what speeds
	 * will be used for autonegotiation where 1000baseT must be disabled.
	 */
	phydev->supported = supported | SUPPORTED_1000baseT_Half |
						SUPPORTED_1000baseT_Full;
	phydev->advertising = supported;
	emaclite->phydev = phydev;
	phy_config(phydev);
	ret = phy_startup(phydev);
	if (ret)
		return ret;

	if (!phydev->link) {
		printf("%s: No link.\n", phydev->dev->name);
		return 0;
	}

	/* Do not setup anything */
	return 1;
}

static int emaclite_start(struct udevice *dev)
{
	struct xemaclite *emaclite = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct emaclite_regs *regs = emaclite->regs;

	debug("EmacLite Initialization Started\n");

/*
 * TX - TX_PING & TX_PONG initialization
 */
	/* Restart PING TX */
	__raw_writel(0, &regs->tx_ping_tsr);
	/* Copy MAC address */
	xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
			       ENET_ADDR_LENGTH);
	/* Set the length */
	__raw_writel(ENET_ADDR_LENGTH, &regs->tx_ping_tplr);
	/* Update the MAC address in the EMAC Lite */
	__raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_ping_tsr);
	/* Wait for EMAC Lite to finish with the MAC address update */
	while ((__raw_readl(&regs->tx_ping_tsr) &
		XEL_TSR_PROG_MAC_ADDR) != 0)
		;

	if (emaclite->txpp) {
		/* The same operation with PONG TX */
		__raw_writel(0, &regs->tx_pong_tsr);
		xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
				       ENET_ADDR_LENGTH);
		__raw_writel(ENET_ADDR_LENGTH, &regs->tx_pong_tplr);
		__raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_pong_tsr);
		while ((__raw_readl(&regs->tx_pong_tsr) &
		       XEL_TSR_PROG_MAC_ADDR) != 0)
			;
	}

/*
 * RX - RX_PING & RX_PONG initialization
 */
	/* Write out the value to flush the RX buffer */
	__raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_ping_rsr);

	if (emaclite->rxpp)
		__raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_pong_rsr);

	__raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, &regs->mdioctrl);
	if (__raw_readl(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
		if (!setup_phy(dev))
			return -1;

	debug("EmacLite Initialization complete\n");
	return 0;
}

static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
{
	u32 tmp;
	struct emaclite_regs *regs = emaclite->regs;

	/*
	 * Read the other buffer register
	 * and determine if the other buffer is available
	 */
	tmp = ~__raw_readl(&regs->tx_ping_tsr);
	if (emaclite->txpp)
		tmp |= ~__raw_readl(&regs->tx_pong_tsr);

	return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
}

static int emaclite_send(struct udevice *dev, void *ptr, int len)
{
	u32 reg;
	struct xemaclite *emaclite = dev_get_priv(dev);
	struct emaclite_regs *regs = emaclite->regs;

	u32 maxtry = 1000;

	if (len > PKTSIZE)
		len = PKTSIZE;

	while (xemaclite_txbufferavailable(emaclite) && maxtry) {
		udelay(10);
		maxtry--;
	}

	if (!maxtry) {
		printf("Error: Timeout waiting for ethernet TX buffer\n");
		/* Restart PING TX */
		__raw_writel(0, &regs->tx_ping_tsr);
		if (emaclite->txpp) {
			__raw_writel(0, &regs->tx_pong_tsr);
		}
		return -1;
	}

	/* Determine if the expected buffer address is empty */
	reg = __raw_readl(&regs->tx_ping_tsr);
	if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
		debug("Send packet from tx_ping buffer\n");
		/* Write the frame to the buffer */
		xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
		__raw_writel(len
			& (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
		       &regs->tx_ping_tplr);
		reg = __raw_readl(&regs->tx_ping_tsr);
		reg |= XEL_TSR_XMIT_BUSY_MASK;
		__raw_writel(reg, &regs->tx_ping_tsr);
		return 0;
	}

	if (emaclite->txpp) {
		/* Determine if the expected buffer address is empty */
		reg = __raw_readl(&regs->tx_pong_tsr);
		if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
			debug("Send packet from tx_pong buffer\n");
			/* Write the frame to the buffer */
			xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
			__raw_writel(len &
				 (XEL_TPLR_LENGTH_MASK_HI |
				  XEL_TPLR_LENGTH_MASK_LO),
				  &regs->tx_pong_tplr);
			reg = __raw_readl(&regs->tx_pong_tsr);
			reg |= XEL_TSR_XMIT_BUSY_MASK;
			__raw_writel(reg, &regs->tx_pong_tsr);
			return 0;
		}
	}

	puts("Error while sending frame\n");
	return -1;
}

static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
{
	u32 length, first_read, reg, attempt = 0;
	void *addr, *ack;
	struct xemaclite *emaclite = dev->priv;
	struct emaclite_regs *regs = emaclite->regs;
	struct ethernet_hdr *eth;
	struct ip_udp_hdr *ip;

try_again:
	if (!emaclite->use_rx_pong_buffer_next) {
		reg = __raw_readl(&regs->rx_ping_rsr);
		debug("Testing data at rx_ping\n");
		if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
			debug("Data found in rx_ping buffer\n");
			addr = &regs->rx_ping;
			ack = &regs->rx_ping_rsr;
		} else {
			debug("Data not found in rx_ping buffer\n");
			/* Pong buffer is not available - return immediately */
			if (!emaclite->rxpp)
				return -1;

			/* Try pong buffer if this is first attempt */
			if (attempt++)
				return -1;
			emaclite->use_rx_pong_buffer_next =
					!emaclite->use_rx_pong_buffer_next;
			goto try_again;
		}
	} else {
		reg = __raw_readl(&regs->rx_pong_rsr);
		debug("Testing data at rx_pong\n");
		if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
			debug("Data found in rx_pong buffer\n");
			addr = &regs->rx_pong;
			ack = &regs->rx_pong_rsr;
		} else {
			debug("Data not found in rx_pong buffer\n");
			/* Try ping buffer if this is first attempt */
			if (attempt++)
				return -1;
			emaclite->use_rx_pong_buffer_next =
					!emaclite->use_rx_pong_buffer_next;
			goto try_again;
		}
	}

	/* Read all bytes for ARP packet with 32bit alignment - 48bytes  */
	first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
	xemaclite_alignedread(addr, etherrxbuff, first_read);

	/* Detect real packet size */
	eth = (struct ethernet_hdr *)etherrxbuff;
	switch (ntohs(eth->et_protlen)) {
	case PROT_ARP:
		length = first_read;
		debug("ARP Packet %x\n", length);
		break;
	case PROT_IP:
		ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
		length = ntohs(ip->ip_len);
		length += ETHER_HDR_SIZE + ETH_FCS_LEN;
		debug("IP Packet %x\n", length);
		break;
	default:
		debug("Other Packet\n");
		length = PKTSIZE;
		break;
	}

	/* Read the rest of the packet which is longer then first read */
	if (length != first_read)
		xemaclite_alignedread(addr + first_read,
				      etherrxbuff + first_read,
				      length - first_read);

	/* Acknowledge the frame */
	reg = __raw_readl(ack);
	reg &= ~XEL_RSR_RECV_DONE_MASK;
	__raw_writel(reg, ack);

	debug("Packet receive from 0x%p, length %dB\n", addr, length);
	*packetp = etherrxbuff;
	return length;
}

static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
				int devad, int reg)
{
	u32 ret;
	u16 val = 0;

	ret = phyread(bus->priv, addr, reg, &val);
	debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
	return val;
}

static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
				 int reg, u16 value)
{
	debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
	return phywrite(bus->priv, addr, reg, value);
}

static int emaclite_probe(struct udevice *dev)
{
	struct xemaclite *emaclite = dev_get_priv(dev);
	int ret;

	emaclite->bus = mdio_alloc();
	emaclite->bus->read = emaclite_miiphy_read;
	emaclite->bus->write = emaclite_miiphy_write;
	emaclite->bus->priv = emaclite;
	strcpy(emaclite->bus->name, "emaclite");

	ret = mdio_register(emaclite->bus);
	if (ret)
		return ret;

	return 0;
}

static int emaclite_remove(struct udevice *dev)
{
	struct xemaclite *emaclite = dev_get_priv(dev);

	free(emaclite->phydev);
	mdio_unregister(emaclite->bus);
	mdio_free(emaclite->bus);

	return 0;
}

static const struct eth_ops emaclite_ops = {
	.start = emaclite_start,
	.send = emaclite_send,
	.recv = emaclite_recv,
	.stop = emaclite_stop,
};

static int emaclite_ofdata_to_platdata(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct xemaclite *emaclite = dev_get_priv(dev);
	int offset = 0;

	pdata->iobase = (phys_addr_t)dev_get_addr(dev);
	emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
								 0x10000);

	emaclite->phyaddr = -1;

	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
				      "phy-handle");
	if (offset > 0)
		emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
						   "reg", -1);

	emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
					"xlnx,tx-ping-pong", 0);
	emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
					"xlnx,rx-ping-pong", 0);

	printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
	       emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);

	return 0;
}

static const struct udevice_id emaclite_ids[] = {
	{ .compatible = "xlnx,xps-ethernetlite-1.00.a" },
	{ }
};

U_BOOT_DRIVER(emaclite) = {
	.name   = "emaclite",
	.id     = UCLASS_ETH,
	.of_match = emaclite_ids,
	.ofdata_to_platdata = emaclite_ofdata_to_platdata,
	.probe  = emaclite_probe,
	.remove = emaclite_remove,
	.ops    = &emaclite_ops,
	.priv_auto_alloc_size = sizeof(struct xemaclite),
	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};
Commit	Line	Data
78d19a39 MS	1	/*
	2	* (C) Copyright 2007-2009 Michal Simek
	3	* (C) Copyright 2003 Xilinx Inc.
89c53891	4	*
89c53891 MS	5	* Michal SIMEK <monstr@monstr.eu>
89c53891 MS	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
78d19a39	8	*/
89c53891 MS	9
	10	#include <common.h>
	11	#include <net.h>
	12	#include <config.h>
d538ee1b	13	#include <dm.h>
d722e864	14	#include <console.h>
042272a6	15	#include <malloc.h>
89c53891	16	#include <asm/io.h>
d722e864 MS	17	#include <phy.h>
d722e864 MS	18	#include <miiphy.h>
7fd70820	19	#include <fdtdec.h>
5d97dff0	20	#include <linux/errno.h>
4d2749be	21	#include <linux/kernel.h>
39e020ef	22	#include <asm/io.h>
7fd70820	23
d538ee1b	24	DECLARE_GLOBAL_DATA_PTR;
89c53891	25
89c53891	26	#define ENET_ADDR_LENGTH 6
4d2749be	27	#define ETH_FCS_LEN 4 /* Octets in the FCS */
89c53891 MS	28
	29	/* Xmit complete */
	30	#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
	31	/* Xmit interrupt enable bit */
	32	#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
89c53891 MS	33	/* Program the MAC address */
	34	#define XEL_TSR_PROGRAM_MASK 0x00000002UL
	35	/* define for programming the MAC address into the EMAC Lite */
	36	#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK \| XEL_TSR_PROGRAM_MASK)
	37
	38	/* Transmit packet length upper byte */
	39	#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
	40	/* Transmit packet length lower byte */
	41	#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
	42
	43	/* Recv complete */
	44	#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
	45	/* Recv interrupt enable bit */
	46	#define XEL_RSR_RECV_IE_MASK 0x00000008UL
	47
d722e864 MS	48	/* MDIO Address Register Bit Masks */
	49	#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
	50	#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
	51	#define XEL_MDIOADDR_PHYADR_SHIFT 5
	52	#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
	53
	54	/* MDIO Write Data Register Bit Masks */
	55	#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
	56
	57	/* MDIO Read Data Register Bit Masks */
	58	#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
	59
	60	/* MDIO Control Register Bit Masks */
	61	#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
	62	#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
	63
9a23c496 MS	64	struct emaclite_regs {
	65	u32 tx_ping; /* 0x0 - TX Ping buffer */
	66	u32 reserved1[504];
	67	u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
	68	u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
	69	u32 mdiord;/* 0x7ec - MDIO Read Data Register */
	70	u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
	71	u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
	72	u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
	73	u32 tx_ping_tsr; /* 0x7fc - Tx status */
	74	u32 tx_pong; /* 0x800 - TX Pong buffer */
	75	u32 reserved2[508];
	76	u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
	77	u32 reserved3; /* 0xff8 */
	78	u32 tx_pong_tsr; /* 0xffc - Tx status */
	79	u32 rx_ping; /* 0x1000 - Receive Buffer */
	80	u32 reserved4[510];
	81	u32 rx_ping_rsr; /* 0x17fc - Rx status */
	82	u32 rx_pong; /* 0x1800 - Receive Buffer */
	83	u32 reserved5[510];
	84	u32 rx_pong_rsr; /* 0x1ffc - Rx status */
	85	};
	86
773cfa8d	87	struct xemaclite {
4d2749be	88	bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
947324b9 MS	89	u32 txpp; /* TX ping pong buffer */
947324b9 MS	90	u32 rxpp; /* RX ping pong buffer */
d722e864	91	int phyaddr;
9a23c496	92	struct emaclite_regs *regs;
d722e864 MS	93	struct phy_device *phydev;
d722e864 MS	94	struct mii_dev *bus;
773cfa8d	95	};
89c53891	96
f412b6ab	97	static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
89c53891	98
5ac83801	99	static void xemaclite_alignedread(u32 srcptr, void destptr, u32 bytecount)
89c53891	100	{
042272a6	101	u32 i;
89c53891 MS	102	u32 alignbuffer;
	103	u32 *to32ptr;
	104	u32 *from32ptr;
	105	u8 *to8ptr;
	106	u8 *from8ptr;
	107
	108	from32ptr = (u32 *) srcptr;
	109
	110	/* Word aligned buffer, no correction needed. */
	111	to32ptr = (u32 *) destptr;
	112	while (bytecount > 3) {
	113	to32ptr++ = from32ptr++;
	114	bytecount -= 4;
	115	}
	116	to8ptr = (u8 *) to32ptr;
	117
	118	alignbuffer = *from32ptr++;
5ac83801	119	from8ptr = (u8 *) &alignbuffer;
89c53891	120
5ac83801	121	for (i = 0; i < bytecount; i++)
89c53891	122	to8ptr++ = from8ptr++;
89c53891 MS	123	}
89c53891 MS	124
00702518	125	static void xemaclite_alignedwrite(void srcptr, u32 destptr, u32 bytecount)
89c53891	126	{
042272a6	127	u32 i;
89c53891 MS	128	u32 alignbuffer;
	129	u32 to32ptr = (u32 ) destptr;
	130	u32 *from32ptr;
	131	u8 *to8ptr;
	132	u8 *from8ptr;
	133
	134	from32ptr = (u32 *) srcptr;
	135	while (bytecount > 3) {
	136
	137	to32ptr++ = from32ptr++;
	138	bytecount -= 4;
	139	}
	140
	141	alignbuffer = 0;
5ac83801	142	to8ptr = (u8 *) &alignbuffer;
89c53891 MS	143	from8ptr = (u8 *) from32ptr;
89c53891 MS	144
5ac83801	145	for (i = 0; i < bytecount; i++)
89c53891	146	to8ptr++ = from8ptr++;
89c53891 MS	147
	148	*to32ptr++ = alignbuffer;
	149	}
	150
d722e864 MS	151	static int wait_for_bit(const char func, u32 reg, const u32 mask,
	152	bool set, unsigned int timeout)
	153	{
	154	u32 val;
	155	unsigned long start = get_timer(0);
	156
	157	while (1) {
611fe0bd	158	val = __raw_readl(reg);
d722e864 MS	159
	160	if (!set)
	161	val = ~val;
	162
	163	if ((val & mask) == mask)
	164	return 0;
	165
	166	if (get_timer(start) > timeout)
	167	break;
	168
	169	if (ctrlc()) {
	170	puts("Abort\n");
	171	return -EINTR;
	172	}
	173
	174	udelay(1);
	175	}
	176
	177	debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
	178	func, reg, mask, set);
	179
	180	return -ETIMEDOUT;
	181	}
	182
9a23c496	183	static int mdio_wait(struct emaclite_regs *regs)
d722e864	184	{
9a23c496	185	return wait_for_bit(__func__, &regs->mdioctrl,
d722e864 MS	186	XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
	187	}
	188
9a23c496	189	static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
d722e864 MS	190	u16 *data)
d722e864 MS	191	{
9a23c496 MS	192	struct emaclite_regs *regs = emaclite->regs;
	193
	194	if (mdio_wait(regs))
d722e864 MS	195	return 1;
d722e864 MS	196
611fe0bd ZLK	197	u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
	198	__raw_writel(XEL_MDIOADDR_OP_MASK
	199	\| ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
	200	\| registernum), &regs->mdioaddr);
	201	__raw_writel(ctrl_reg \| XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
d722e864	202
9a23c496	203	if (mdio_wait(regs))
d722e864 MS	204	return 1;
	205
	206	/* Read data */
611fe0bd	207	*data = __raw_readl(&regs->mdiord);
d722e864 MS	208	return 0;
	209	}
	210
9a23c496	211	static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
d722e864 MS	212	u16 data)
d722e864 MS	213	{
9a23c496 MS	214	struct emaclite_regs *regs = emaclite->regs;
	215
	216	if (mdio_wait(regs))
d722e864 MS	217	return 1;
	218
	219	/*
	220	* Write the PHY address, register number and clear the OP bit in the
	221	* MDIO Address register and then write the value into the MDIO Write
	222	* Data register. Finally, set the Status bit in the MDIO Control
	223	* register to start a MDIO write transaction.
	224	*/
611fe0bd ZLK	225	u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
	226	__raw_writel(~XEL_MDIOADDR_OP_MASK
	227	& ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
	228	\| registernum), &regs->mdioaddr);
	229	__raw_writel(data, &regs->mdiowr);
	230	__raw_writel(ctrl_reg \| XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
d722e864	231
9a23c496	232	if (mdio_wait(regs))
d722e864 MS	233	return 1;
	234
	235	return 0;
	236	}
d722e864	237
f03ec010	238	static void emaclite_stop(struct udevice *dev)
89c53891	239	{
f03ec010	240	debug("eth_stop\n");
89c53891 MS	241	}
89c53891 MS	242
d722e864 MS	243	/* Use MII register 1 (MII status register) to detect PHY */
	244	#define PHY_DETECT_REG 1
	245
	246	/* Mask used to verify certain PHY features (or register contents)
	247	* in the register above:
	248	* 0x1000: 10Mbps full duplex support
	249	* 0x0800: 10Mbps half duplex support
	250	* 0x0008: Auto-negotiation support
	251	*/
	252	#define PHY_DETECT_MASK 0x1808
	253
d538ee1b	254	static int setup_phy(struct udevice *dev)
d722e864	255	{
55259e7c	256	int i, ret;
d722e864	257	u16 phyreg;
d538ee1b	258	struct xemaclite *emaclite = dev_get_priv(dev);
d722e864 MS	259	struct phy_device *phydev;
	260
	261	u32 supported = SUPPORTED_10baseT_Half \|
	262	SUPPORTED_10baseT_Full \|
	263	SUPPORTED_100baseT_Half \|
	264	SUPPORTED_100baseT_Full;
	265
	266	if (emaclite->phyaddr != -1) {
9a23c496	267	phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
d722e864 MS	268	if ((phyreg != 0xFFFF) &&
	269	((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
	270	/* Found a valid PHY address */
	271	debug("Default phy address %d is valid\n",
	272	emaclite->phyaddr);
	273	} else {
	274	debug("PHY address is not setup correctly %d\n",
	275	emaclite->phyaddr);
	276	emaclite->phyaddr = -1;
	277	}
	278	}
	279
	280	if (emaclite->phyaddr == -1) {
	281	/* detect the PHY address */
	282	for (i = 31; i >= 0; i--) {
9a23c496	283	phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
d722e864 MS	284	if ((phyreg != 0xFFFF) &&
	285	((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
	286	/* Found a valid PHY address */
	287	emaclite->phyaddr = i;
	288	debug("emaclite: Found valid phy address, %d\n",
	289	i);
	290	break;
	291	}
	292	}
	293	}
	294
	295	/* interface - look at tsec */
	296	phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
	297	PHY_INTERFACE_MODE_MII);
	298	/*
	299	* Phy can support 1000baseT but device NOT that's why phydev->supported
	300	* must be setup for 1000baseT. phydev->advertising setups what speeds
	301	* will be used for autonegotiation where 1000baseT must be disabled.
	302	*/
	303	phydev->supported = supported \| SUPPORTED_1000baseT_Half \|
	304	SUPPORTED_1000baseT_Full;
	305	phydev->advertising = supported;
	306	emaclite->phydev = phydev;
	307	phy_config(phydev);
55259e7c MS	308	ret = phy_startup(phydev);
	309	if (ret)
	310	return ret;
d722e864 MS	311
	312	if (!phydev->link) {
	313	printf("%s: No link.\n", phydev->dev->name);
	314	return 0;
	315	}
	316
	317	/* Do not setup anything */
	318	return 1;
	319	}
d722e864	320
f03ec010	321	static int emaclite_start(struct udevice *dev)
89c53891	322	{
d538ee1b MS	323	struct xemaclite *emaclite = dev_get_priv(dev);
d538ee1b MS	324	struct eth_pdata *pdata = dev_get_platdata(dev);
9a23c496 MS	325	struct emaclite_regs *regs = emaclite->regs;
9a23c496 MS	326
5ac83801	327	debug("EmacLite Initialization Started\n");
89c53891 MS	328
	329	/*
	330	* TX - TX_PING & TX_PONG initialization
	331	*/
	332	/* Restart PING TX */
611fe0bd	333	__raw_writel(0, &regs->tx_ping_tsr);
89c53891	334	/* Copy MAC address */
d538ee1b	335	xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
a0b2bfb0	336	ENET_ADDR_LENGTH);
89c53891	337	/* Set the length */
611fe0bd	338	__raw_writel(ENET_ADDR_LENGTH, &regs->tx_ping_tplr);
89c53891	339	/* Update the MAC address in the EMAC Lite */
611fe0bd	340	__raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_ping_tsr);
89c53891	341	/* Wait for EMAC Lite to finish with the MAC address update */
611fe0bd	342	while ((__raw_readl(&regs->tx_ping_tsr) &
8d95ddbb MS	343	XEL_TSR_PROG_MAC_ADDR) != 0)
8d95ddbb MS	344	;
89c53891	345
947324b9 MS	346	if (emaclite->txpp) {
947324b9 MS	347	/* The same operation with PONG TX */
611fe0bd	348	__raw_writel(0, &regs->tx_pong_tsr);
d538ee1b	349	xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
a0b2bfb0	350	ENET_ADDR_LENGTH);
611fe0bd ZLK	351	__raw_writel(ENET_ADDR_LENGTH, &regs->tx_pong_tplr);
	352	__raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_pong_tsr);
	353	while ((__raw_readl(&regs->tx_pong_tsr) &
a0b2bfb0	354	XEL_TSR_PROG_MAC_ADDR) != 0)
947324b9 MS	355	;
947324b9 MS	356	}
89c53891 MS	357
	358	/*
	359	* RX - RX_PING & RX_PONG initialization
	360	*/
	361	/* Write out the value to flush the RX buffer */
611fe0bd	362	__raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_ping_rsr);
947324b9 MS	363
947324b9 MS	364	if (emaclite->rxpp)
611fe0bd	365	__raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_pong_rsr);
89c53891	366
611fe0bd ZLK	367	__raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, &regs->mdioctrl);
611fe0bd ZLK	368	if (__raw_readl(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
d722e864 MS	369	if (!setup_phy(dev))
d722e864 MS	370	return -1;
d538ee1b	371
5ac83801	372	debug("EmacLite Initialization complete\n");
89c53891 MS	373	return 0;
	374	}
	375
26c7945a	376	static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
89c53891	377	{
26c7945a MS	378	u32 tmp;
26c7945a MS	379	struct emaclite_regs *regs = emaclite->regs;
773cfa8d	380
89c53891 MS	381	/*
	382	* Read the other buffer register
	383	* and determine if the other buffer is available
	384	*/
611fe0bd	385	tmp = ~__raw_readl(&regs->tx_ping_tsr);
26c7945a	386	if (emaclite->txpp)
611fe0bd	387	tmp \|= ~__raw_readl(&regs->tx_pong_tsr);
89c53891	388
26c7945a	389	return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
89c53891 MS	390	}
89c53891 MS	391
d538ee1b	392	static int emaclite_send(struct udevice dev, void ptr, int len)
042272a6 MS	393	{
042272a6 MS	394	u32 reg;
d538ee1b	395	struct xemaclite *emaclite = dev_get_priv(dev);
5a4baa33	396	struct emaclite_regs *regs = emaclite->regs;
89c53891	397
042272a6	398	u32 maxtry = 1000;
89c53891	399
80439252 MS	400	if (len > PKTSIZE)
80439252 MS	401	len = PKTSIZE;
89c53891	402
26c7945a	403	while (xemaclite_txbufferavailable(emaclite) && maxtry) {
5ac83801	404	udelay(10);
89c53891 MS	405	maxtry--;
	406	}
	407
	408	if (!maxtry) {
5ac83801	409	printf("Error: Timeout waiting for ethernet TX buffer\n");
89c53891	410	/* Restart PING TX */
611fe0bd	411	__raw_writel(0, &regs->tx_ping_tsr);
947324b9	412	if (emaclite->txpp) {
611fe0bd	413	__raw_writel(0, &regs->tx_pong_tsr);
947324b9	414	}
95efa79d	415	return -1;
89c53891 MS	416	}
89c53891 MS	417
89c53891	418	/* Determine if the expected buffer address is empty */
611fe0bd	419	reg = __raw_readl(&regs->tx_ping_tsr);
15c239c8	420	if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
00702518	421	debug("Send packet from tx_ping buffer\n");
89c53891	422	/* Write the frame to the buffer */
00702518	423	xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
611fe0bd ZLK	424	__raw_writel(len
	425	& (XEL_TPLR_LENGTH_MASK_HI \| XEL_TPLR_LENGTH_MASK_LO),
	426	&regs->tx_ping_tplr);
	427	reg = __raw_readl(&regs->tx_ping_tsr);
89c53891	428	reg \|= XEL_TSR_XMIT_BUSY_MASK;
611fe0bd	429	__raw_writel(reg, &regs->tx_ping_tsr);
95efa79d	430	return 0;
89c53891	431	}
947324b9 MS	432
947324b9 MS	433	if (emaclite->txpp) {
947324b9	434	/* Determine if the expected buffer address is empty */
611fe0bd	435	reg = __raw_readl(&regs->tx_pong_tsr);
15c239c8	436	if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
00702518	437	debug("Send packet from tx_pong buffer\n");
947324b9	438	/* Write the frame to the buffer */
00702518	439	xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
611fe0bd	440	__raw_writel(len &
00702518	441	(XEL_TPLR_LENGTH_MASK_HI \|
611fe0bd ZLK	442	XEL_TPLR_LENGTH_MASK_LO),
	443	&regs->tx_pong_tplr);
	444	reg = __raw_readl(&regs->tx_pong_tsr);
947324b9	445	reg \|= XEL_TSR_XMIT_BUSY_MASK;
611fe0bd	446	__raw_writel(reg, &regs->tx_pong_tsr);
947324b9	447	return 0;
89c53891	448	}
89c53891	449	}
947324b9	450
5ac83801	451	puts("Error while sending frame\n");
95efa79d	452	return -1;
89c53891 MS	453	}
89c53891 MS	454
d538ee1b	455	static int emaclite_recv(struct udevice dev, int flags, uchar *packetp)
89c53891	456	{
4d2749be MS	457	u32 length, first_read, reg, attempt = 0;
4d2749be MS	458	void addr, ack;
773cfa8d	459	struct xemaclite *emaclite = dev->priv;
4d2749be MS	460	struct emaclite_regs *regs = emaclite->regs;
	461	struct ethernet_hdr *eth;
	462	struct ip_udp_hdr *ip;
	463
	464	try_again:
	465	if (!emaclite->use_rx_pong_buffer_next) {
611fe0bd	466	reg = __raw_readl(&regs->rx_ping_rsr);
4d2749be MS	467	debug("Testing data at rx_ping\n");
	468	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
	469	debug("Data found in rx_ping buffer\n");
	470	addr = &regs->rx_ping;
	471	ack = &regs->rx_ping_rsr;
	472	} else {
	473	debug("Data not found in rx_ping buffer\n");
	474	/* Pong buffer is not available - return immediately */
	475	if (!emaclite->rxpp)
	476	return -1;
	477
	478	/* Try pong buffer if this is first attempt */
	479	if (attempt++)
	480	return -1;
	481	emaclite->use_rx_pong_buffer_next =
	482	!emaclite->use_rx_pong_buffer_next;
	483	goto try_again;
	484	}
89c53891	485	} else {
611fe0bd	486	reg = __raw_readl(&regs->rx_pong_rsr);
4d2749be MS	487	debug("Testing data at rx_pong\n");
	488	if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
	489	debug("Data found in rx_pong buffer\n");
	490	addr = &regs->rx_pong;
	491	ack = &regs->rx_pong_rsr;
947324b9	492	} else {
4d2749be MS	493	debug("Data not found in rx_pong buffer\n");
	494	/* Try ping buffer if this is first attempt */
	495	if (attempt++)
	496	return -1;
	497	emaclite->use_rx_pong_buffer_next =
	498	!emaclite->use_rx_pong_buffer_next;
	499	goto try_again;
89c53891	500	}
89c53891	501	}
4d2749be MS	502
	503	/* Read all bytes for ARP packet with 32bit alignment - 48bytes */
	504	first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
	505	xemaclite_alignedread(addr, etherrxbuff, first_read);
	506
	507	/* Detect real packet size */
	508	eth = (struct ethernet_hdr *)etherrxbuff;
	509	switch (ntohs(eth->et_protlen)) {
	510	case PROT_ARP:
	511	length = first_read;
	512	debug("ARP Packet %x\n", length);
	513	break;
	514	case PROT_IP:
	515	ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
	516	length = ntohs(ip->ip_len);
	517	length += ETHER_HDR_SIZE + ETH_FCS_LEN;
	518	debug("IP Packet %x\n", length);
	519	break;
	520	default:
	521	debug("Other Packet\n");
	522	length = PKTSIZE;
	523	break;
89c53891 MS	524	}
89c53891 MS	525
4d2749be MS	526	/* Read the rest of the packet which is longer then first read */
	527	if (length != first_read)
	528	xemaclite_alignedread(addr + first_read,
	529	etherrxbuff + first_read,
	530	length - first_read);
89c53891 MS	531
89c53891 MS	532	/* Acknowledge the frame */
611fe0bd	533	reg = __raw_readl(ack);
89c53891	534	reg &= ~XEL_RSR_RECV_DONE_MASK;
611fe0bd	535	__raw_writel(reg, ack);
89c53891	536
4d2749be	537	debug("Packet receive from 0x%p, length %dB\n", addr, length);
f412b6ab MS	538	*packetp = etherrxbuff;
f412b6ab MS	539	return length;
89c53891	540	}
042272a6	541
d538ee1b MS	542	static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
d538ee1b MS	543	int devad, int reg)
d722e864 MS	544	{
d722e864 MS	545	u32 ret;
d538ee1b	546	u16 val = 0;
d722e864	547
d538ee1b MS	548	ret = phyread(bus->priv, addr, reg, &val);
	549	debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
	550	return val;
d722e864 MS	551	}
d722e864 MS	552
d538ee1b MS	553	static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
d538ee1b MS	554	int reg, u16 value)
d722e864	555	{
d538ee1b MS	556	debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
d538ee1b MS	557	return phywrite(bus->priv, addr, reg, value);
d722e864	558	}
d722e864	559
d538ee1b	560	static int emaclite_probe(struct udevice *dev)
042272a6	561	{
d538ee1b MS	562	struct xemaclite *emaclite = dev_get_priv(dev);
d538ee1b MS	563	int ret;
042272a6	564
d538ee1b MS	565	emaclite->bus = mdio_alloc();
	566	emaclite->bus->read = emaclite_miiphy_read;
	567	emaclite->bus->write = emaclite_miiphy_write;
	568	emaclite->bus->priv = emaclite;
361a8799	569	strcpy(emaclite->bus->name, "emaclite");
042272a6	570
361a8799	571	ret = mdio_register(emaclite->bus);
d538ee1b MS	572	if (ret)
	573	return ret;
	574
	575	return 0;
	576	}
773cfa8d	577
d538ee1b MS	578	static int emaclite_remove(struct udevice *dev)
	579	{
	580	struct xemaclite *emaclite = dev_get_priv(dev);
	581
	582	free(emaclite->phydev);
	583	mdio_unregister(emaclite->bus);
	584	mdio_free(emaclite->bus);
773cfa8d	585
d538ee1b MS	586	return 0;
d538ee1b MS	587	}
947324b9	588
d538ee1b	589	static const struct eth_ops emaclite_ops = {
f03ec010	590	.start = emaclite_start,
d538ee1b MS	591	.send = emaclite_send,
d538ee1b MS	592	.recv = emaclite_recv,
f03ec010	593	.stop = emaclite_stop,
d538ee1b MS	594	};
	595
	596	static int emaclite_ofdata_to_platdata(struct udevice *dev)
	597	{
	598	struct eth_pdata *pdata = dev_get_platdata(dev);
	599	struct xemaclite *emaclite = dev_get_priv(dev);
	600	int offset = 0;
042272a6	601
d538ee1b	602	pdata->iobase = (phys_addr_t)dev_get_addr(dev);
39e020ef ZLK	603	emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
39e020ef ZLK	604	0x10000);
042272a6	605
d722e864	606	emaclite->phyaddr = -1;
d722e864	607
d538ee1b MS	608	offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
	609	"phy-handle");
	610	if (offset > 0)
	611	emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
	612	"reg", -1);
042272a6	613
d538ee1b MS	614	emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
	615	"xlnx,tx-ping-pong", 0);
	616	emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
	617	"xlnx,rx-ping-pong", 0);
d722e864	618
d538ee1b MS	619	printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
d538ee1b MS	620	emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
d722e864	621
d538ee1b	622	return 0;
042272a6	623	}
d538ee1b MS	624
	625	static const struct udevice_id emaclite_ids[] = {
	626	{ .compatible = "xlnx,xps-ethernetlite-1.00.a" },
	627	{ }
	628	};
	629
	630	U_BOOT_DRIVER(emaclite) = {
	631	.name = "emaclite",
	632	.id = UCLASS_ETH,
	633	.of_match = emaclite_ids,
	634	.ofdata_to_platdata = emaclite_ofdata_to_platdata,
	635	.probe = emaclite_probe,
	636	.remove = emaclite_remove,
	637	.ops = &emaclite_ops,
	638	.priv_auto_alloc_size = sizeof(struct xemaclite),
	639	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	640	};