[people/ms/u-boot.git] / drivers / pci / pci_auto.c

/*
 * arch/ppc/kernel/pci_auto.c
 *
 * PCI autoconfiguration library
 *
 * Author: Matt Porter <mporter@mvista.com>
 *
 * Copyright 2000 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <common.h>

#include <pci.h>

#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */

#define	PCIAUTO_IDE_MODE_MASK		0x05

/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	8
#endif

/*
 *
 */

void pciauto_region_init(struct pci_region* res)
{
	/*
	 * Avoid allocating PCI resources from address 0 -- this is illegal
	 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
	 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
	 */
	res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
}

void pciauto_region_align(struct pci_region *res, unsigned long size)
{
	res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
}

int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
{
	unsigned long addr;

	if (!res) {
		DEBUGF("No resource");
		goto error;
	}

	addr = ((res->bus_lower - 1) | (size - 1)) + 1;

	if (addr - res->bus_start + size > res->size) {
		DEBUGF("No room in resource");
		goto error;
	}

	res->bus_lower = addr + size;

	DEBUGF("address=0x%lx bus_lower=%x", addr, res->bus_lower);

	*bar = addr;
	return 0;

 error:
	*bar = 0xffffffff;
	return -1;
}

/*
 *
 */

void pciauto_setup_device(struct pci_controller *hose,
			  pci_dev_t dev, int bars_num,
			  struct pci_region *mem,
			  struct pci_region *prefetch,
			  struct pci_region *io)
{
	unsigned int bar_value, bar_response, bar_size;
	unsigned int cmdstat = 0;
	struct pci_region *bar_res;
	int bar, bar_nr = 0;
	int found_mem64 = 0;

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;

	for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
		/* Tickle the BAR and get the response */
		pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
		pci_hose_read_config_dword(hose, dev, bar, &bar_response);

		/* If BAR is not implemented go to the next BAR */
		if (!bar_response)
			continue;

		found_mem64 = 0;

		/* Check the BAR type and set our address mask */
		if (bar_response & PCI_BASE_ADDRESS_SPACE) {
			bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
				   & 0xffff) + 1;
			bar_res = io;

			DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
		} else {
			if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
			     PCI_BASE_ADDRESS_MEM_TYPE_64)
				found_mem64 = 1;

			bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
			if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
				bar_res = prefetch;
			else
				bar_res = mem;

			DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
		}

		if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
			/* Write it out and update our limit */
			pci_hose_write_config_dword(hose, dev, bar, bar_value);

			/*
			 * If we are a 64-bit decoder then increment to the
			 * upper 32 bits of the bar and force it to locate
			 * in the lower 4GB of memory.
			 */
			if (found_mem64) {
				bar += 4;
				pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
			}

			cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
				PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
		}

		DEBUGF("\n");

		bar_nr++;
	}

	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
		CONFIG_SYS_PCI_CACHE_LINE_SIZE);
	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}

void pciauto_prescan_setup_bridge(struct pci_controller *hose,
					 pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem = hose->pci_mem;
	struct pci_region *pci_prefetch = hose->pci_prefetch;
	struct pci_region *pci_io = hose->pci_io;
	unsigned int cmdstat;

	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
				   PCI_BUS(dev) - hose->first_busno);
	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
				   sub_bus - hose->first_busno);
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);

	if (pci_mem) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
		pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
					(pci_mem->bus_lower & 0xfff00000) >> 16);

		cmdstat |= PCI_COMMAND_MEMORY;
	}

	if (pci_prefetch) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_prefetch, 0x100000);

		/* Set up memory and I/O filter limits, assume 32-bit I/O space */
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
					(pci_prefetch->bus_lower & 0xfff00000) >> 16);

		cmdstat |= PCI_COMMAND_MEMORY;
	} else {
		/* We don't support prefetchable memory for now, so disable */
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
	}

	if (pci_io) {
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
					(pci_io->bus_lower & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
					(pci_io->bus_lower & 0xffff0000) >> 16);

		cmdstat |= PCI_COMMAND_IO;
	}

	/* Enable memory and I/O accesses, enable bus master */
	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
}

void pciauto_postscan_setup_bridge(struct pci_controller *hose,
					  pci_dev_t dev, int sub_bus)
{
	struct pci_region *pci_mem = hose->pci_mem;
	struct pci_region *pci_prefetch = hose->pci_prefetch;
	struct pci_region *pci_io = hose->pci_io;

	/* Configure bus number registers */
	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
				   sub_bus - hose->first_busno);

	if (pci_mem) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_mem, 0x100000);

		pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
					(pci_mem->bus_lower-1) >> 16);
	}

	if (pci_prefetch) {
		/* Round memory allocator to 1MB boundary */
		pciauto_region_align(pci_prefetch, 0x100000);

		pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
					(pci_prefetch->bus_lower-1) >> 16);
	}

	if (pci_io) {
		/* Round I/O allocator to 4KB boundary */
		pciauto_region_align(pci_io, 0x1000);

		pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
					((pci_io->bus_lower-1) & 0x0000f000) >> 8);
		pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
					((pci_io->bus_lower-1) & 0xffff0000) >> 16);
	}
}

/*
 *
 */

void pciauto_config_init(struct pci_controller *hose)
{
	int i;

	hose->pci_io = hose->pci_mem = NULL;

	for (i=0; i<hose->region_count; i++) {
		switch(hose->regions[i].flags) {
		case PCI_REGION_IO:
			if (!hose->pci_io ||
			    hose->pci_io->size < hose->regions[i].size)
				hose->pci_io = hose->regions + i;
			break;
		case PCI_REGION_MEM:
			if (!hose->pci_mem ||
			    hose->pci_mem->size < hose->regions[i].size)
				hose->pci_mem = hose->regions + i;
			break;
		case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
			if (!hose->pci_prefetch ||
			    hose->pci_prefetch->size < hose->regions[i].size)
				hose->pci_prefetch = hose->regions + i;
			break;
		}
	}


	if (hose->pci_mem) {
		pciauto_region_init(hose->pci_mem);

		DEBUGF("PCI Autoconfig: Bus Memory region: [%lx-%lx],\n"
		       "\t\tPhysical Memory [%x-%x]\n",
		    hose->pci_mem->bus_start,
		    hose->pci_mem->bus_start + hose->pci_mem->size - 1,
		    hose->pci_mem->phys_start,
		    hose->pci_mem->phys_start + hose->pci_mem->size - 1);
	}

	if (hose->pci_prefetch) {
		pciauto_region_init(hose->pci_prefetch);

		DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [%lx-%lx],\n"
		       "\t\tPhysical Memory [%x-%x]\n",
		    hose->pci_prefetch->bus_start,
		    hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1,
		    hose->pci_prefetch->phys_start,
		    hose->pci_prefetch->phys_start +
				hose->pci_prefetch->size - 1);
	}

	if (hose->pci_io) {
		pciauto_region_init(hose->pci_io);

		DEBUGF("PCI Autoconfig: Bus I/O region: [%lx-%lx],\n"
		       "\t\tPhysical Memory: [%x-%x]\n",
		    hose->pci_io->bus_start,
		    hose->pci_io->bus_start + hose->pci_io->size - 1,
		    hose->pci_io->phys_start,
		    hose->pci_io->phys_start + hose->pci_io->size - 1);

	}
}

/* HJF: Changed this to return int. I think this is required
 * to get the correct result when scanning bridges
 */
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
{
	unsigned int sub_bus = PCI_BUS(dev);
	unsigned short class;
	unsigned char prg_iface;
	int n;

	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);

	switch(class) {
	case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
		DEBUGF("PCI AutoConfig: Found PowerPC device\n");
		pciauto_setup_device(hose, dev, 6, hose->pci_mem,
				     hose->pci_prefetch, hose->pci_io);
		break;

	case PCI_CLASS_BRIDGE_PCI:
		hose->current_busno++;
		pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);

		DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));

		/* Passing in current_busno allows for sibling P2P bridges */
		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
		/*
		 * need to figure out if this is a subordinate bridge on the bus
		 * to be able to properly set the pri/sec/sub bridge registers.
		 */
		n = pci_hose_scan_bus(hose, hose->current_busno);

		/* figure out the deepest we've gone for this leg */
		sub_bus = max(n, sub_bus);
		pciauto_postscan_setup_bridge(hose, dev, sub_bus);

		sub_bus = hose->current_busno;
		break;

	case PCI_CLASS_STORAGE_IDE:
		pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
		if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
			DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
			return sub_bus;
		}

		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
		break;

	case PCI_CLASS_BRIDGE_CARDBUS:
		/* just do a minimal setup of the bridge, let the OS take care of the rest */
		pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);

		DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));

		hose->current_busno++;
		break;

#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
	case PCI_CLASS_BRIDGE_OTHER:
		DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
		       PCI_DEV(dev));
		break;
#endif
#ifdef CONFIG_MPC834X
	case PCI_CLASS_BRIDGE_OTHER:
		/*
		 * The host/PCI bridge 1 seems broken in 8349 - it presents
		 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
		 * device claiming resources io/mem/irq.. we only allow for
		 * the PIMMR window to be allocated (BAR0 - 1MB size)
		 */
		DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
		pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
		break;
#endif
	default:
		pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
		break;
	}

	return sub_bus;
}
Commit	Line	Data
c609719b WD	1	/*
	2	* arch/ppc/kernel/pci_auto.c
	3	*
	4	* PCI autoconfiguration library
	5	*
	6	* Author: Matt Porter <mporter@mvista.com>
	7	*
	8	* Copyright 2000 MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <common.h>
	17
c609719b WD	18	#include <pci.h>
	19
	20	#undef DEBUG
	21	#ifdef DEBUG
	22	#define DEBUGF(x...) printf(x)
	23	#else
	24	#define DEBUGF(x...)
	25	#endif /* DEBUG */
	26
	27	#define PCIAUTO_IDE_MODE_MASK 0x05
	28
6d0f6bcf JCPV	29	/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
	30	#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
	31	#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
81b73dec GJ	32	#endif
81b73dec GJ	33
c609719b WD	34	/*
	35	*
	36	*/
	37
	38	void pciauto_region_init(struct pci_region* res)
	39	{
b7598a43 SS	40	/*
	41	* Avoid allocating PCI resources from address 0 -- this is illegal
	42	* according to PCI 2.1 and moreover, this is known to cause Linux IDE
	43	* drivers to fail. Use a reasonable starting value of 0x1000 instead.
	44	*/
	45	res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
c609719b WD	46	}
	47
	48	void pciauto_region_align(struct pci_region *res, unsigned long size)
	49	{
	50	res->bus_lower = ((res->bus_lower - 1) \| (size - 1)) + 1;
	51	}
	52
	53	int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
	54	{
	55	unsigned long addr;
	56
3c74e32a	57	if (!res) {
c609719b WD	58	DEBUGF("No resource");
	59	goto error;
	60	}
	61
	62	addr = ((res->bus_lower - 1) \| (size - 1)) + 1;
	63
3c74e32a	64	if (addr - res->bus_start + size > res->size) {
c609719b WD	65	DEBUGF("No room in resource");
	66	goto error;
	67	}
	68
	69	res->bus_lower = addr + size;
	70
ba5feb12	71	DEBUGF("address=0x%lx bus_lower=%x", addr, res->bus_lower);
c609719b WD	72
	73	*bar = addr;
	74	return 0;
	75
	76	error:
	77	*bar = 0xffffffff;
	78	return -1;
	79	}
	80
	81	/*
	82	*
	83	*/
	84
	85	void pciauto_setup_device(struct pci_controller *hose,
	86	pci_dev_t dev, int bars_num,
	87	struct pci_region *mem,
a179012e	88	struct pci_region *prefetch,
c609719b WD	89	struct pci_region *io)
	90	{
	91	unsigned int bar_value, bar_response, bar_size;
	92	unsigned int cmdstat = 0;
	93	struct pci_region *bar_res;
	94	int bar, bar_nr = 0;
	95	int found_mem64 = 0;
	96
	97	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	98	cmdstat = (cmdstat & ~(PCI_COMMAND_IO \| PCI_COMMAND_MEMORY)) \| PCI_COMMAND_MASTER;
	99
936b3e69	100	for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
c609719b WD	101	/* Tickle the BAR and get the response */
	102	pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
	103	pci_hose_read_config_dword(hose, dev, bar, &bar_response);
	104
	105	/* If BAR is not implemented go to the next BAR */
	106	if (!bar_response)
	107	continue;
	108
	109	found_mem64 = 0;
	110
	111	/* Check the BAR type and set our address mask */
3c74e32a	112	if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bd22c2b9 JZR	113	bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
bd22c2b9 JZR	114	& 0xffff) + 1;
c609719b WD	115	bar_res = io;
	116
	117	DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
3c74e32a	118	} else {
c609719b WD	119	if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
	120	PCI_BASE_ADDRESS_MEM_TYPE_64)
	121	found_mem64 = 1;
	122
	123	bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
a179012e KG	124	if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
	125	bar_res = prefetch;
	126	else
	127	bar_res = mem;
c609719b WD	128
	129	DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
	130	}
	131
3c74e32a	132	if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
c609719b WD	133	/* Write it out and update our limit */
	134	pci_hose_write_config_dword(hose, dev, bar, bar_value);
	135
	136	/*
	137	* If we are a 64-bit decoder then increment to the
	138	* upper 32 bits of the bar and force it to locate
	139	* in the lower 4GB of memory.
	140	*/
3c74e32a	141	if (found_mem64) {
c609719b WD	142	bar += 4;
	143	pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
	144	}
	145
	146	cmdstat \|= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
	147	PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
	148	}
	149
	150	DEBUGF("\n");
	151
	152	bar_nr++;
	153	}
	154
	155	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
81b73dec	156	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
6d0f6bcf	157	CONFIG_SYS_PCI_CACHE_LINE_SIZE);
c609719b WD	158	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
	159	}
	160
ba5feb12	161	void pciauto_prescan_setup_bridge(struct pci_controller *hose,
c609719b WD	162	pci_dev_t dev, int sub_bus)
	163	{
	164	struct pci_region *pci_mem = hose->pci_mem;
a179012e	165	struct pci_region *pci_prefetch = hose->pci_prefetch;
c609719b WD	166	struct pci_region *pci_io = hose->pci_io;
	167	unsigned int cmdstat;
	168
	169	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	170
	171	/* Configure bus number registers */
e8b85f3b ES	172	pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
	173	PCI_BUS(dev) - hose->first_busno);
	174	pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
	175	sub_bus - hose->first_busno);
c609719b WD	176	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
c609719b WD	177
3c74e32a	178	if (pci_mem) {
c609719b WD	179	/* Round memory allocator to 1MB boundary */
	180	pciauto_region_align(pci_mem, 0x100000);
	181
	182	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	183	pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
	184	(pci_mem->bus_lower & 0xfff00000) >> 16);
	185
	186	cmdstat \|= PCI_COMMAND_MEMORY;
	187	}
	188
a179012e KG	189	if (pci_prefetch) {
	190	/* Round memory allocator to 1MB boundary */
	191	pciauto_region_align(pci_prefetch, 0x100000);
	192
	193	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	194	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
	195	(pci_prefetch->bus_lower & 0xfff00000) >> 16);
	196
	197	cmdstat \|= PCI_COMMAND_MEMORY;
	198	} else {
	199	/* We don't support prefetchable memory for now, so disable */
	200	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
a4e11558	201	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
a179012e KG	202	}
a179012e KG	203
3c74e32a	204	if (pci_io) {
c609719b WD	205	/* Round I/O allocator to 4KB boundary */
	206	pciauto_region_align(pci_io, 0x1000);
	207
	208	pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
	209	(pci_io->bus_lower & 0x0000f000) >> 8);
	210	pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
	211	(pci_io->bus_lower & 0xffff0000) >> 16);
	212
	213	cmdstat \|= PCI_COMMAND_IO;
	214	}
	215
c609719b WD	216	/* Enable memory and I/O accesses, enable bus master */
	217	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat \| PCI_COMMAND_MASTER);
	218	}
	219
ba5feb12	220	void pciauto_postscan_setup_bridge(struct pci_controller *hose,
c609719b WD	221	pci_dev_t dev, int sub_bus)
	222	{
	223	struct pci_region *pci_mem = hose->pci_mem;
a179012e	224	struct pci_region *pci_prefetch = hose->pci_prefetch;
c609719b WD	225	struct pci_region *pci_io = hose->pci_io;
	226
	227	/* Configure bus number registers */
e8b85f3b ES	228	pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
e8b85f3b ES	229	sub_bus - hose->first_busno);
c609719b	230
3c74e32a	231	if (pci_mem) {
c609719b WD	232	/* Round memory allocator to 1MB boundary */
	233	pciauto_region_align(pci_mem, 0x100000);
	234
	235	pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
	236	(pci_mem->bus_lower-1) >> 16);
	237	}
	238
a179012e KG	239	if (pci_prefetch) {
	240	/* Round memory allocator to 1MB boundary */
	241	pciauto_region_align(pci_prefetch, 0x100000);
	242
	243	pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
	244	(pci_prefetch->bus_lower-1) >> 16);
	245	}
	246
3c74e32a	247	if (pci_io) {
c609719b WD	248	/* Round I/O allocator to 4KB boundary */
	249	pciauto_region_align(pci_io, 0x1000);
	250
	251	pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
	252	((pci_io->bus_lower-1) & 0x0000f000) >> 8);
	253	pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
	254	((pci_io->bus_lower-1) & 0xffff0000) >> 16);
	255	}
	256	}
	257
	258	/*
	259	*
	260	*/
	261
	262	void pciauto_config_init(struct pci_controller *hose)
	263	{
	264	int i;
	265
	266	hose->pci_io = hose->pci_mem = NULL;
	267
3c74e32a WD	268	for (i=0; i<hose->region_count; i++) {
3c74e32a WD	269	switch(hose->regions[i].flags) {
c609719b WD	270	case PCI_REGION_IO:
	271	if (!hose->pci_io \|\|
	272	hose->pci_io->size < hose->regions[i].size)
	273	hose->pci_io = hose->regions + i;
	274	break;
	275	case PCI_REGION_MEM:
	276	if (!hose->pci_mem \|\|
	277	hose->pci_mem->size < hose->regions[i].size)
	278	hose->pci_mem = hose->regions + i;
	279	break;
a179012e KG	280	case (PCI_REGION_MEM \| PCI_REGION_PREFETCH):
	281	if (!hose->pci_prefetch \|\|
	282	hose->pci_prefetch->size < hose->regions[i].size)
	283	hose->pci_prefetch = hose->regions + i;
	284	break;
c609719b WD	285	}
	286	}
	287
	288
3c74e32a	289	if (hose->pci_mem) {
c609719b WD	290	pciauto_region_init(hose->pci_mem);
c609719b WD	291
ba5feb12 ES	292	DEBUGF("PCI Autoconfig: Bus Memory region: [%lx-%lx],\n"
ba5feb12 ES	293	"\t\tPhysical Memory [%x-%x]\n",
c609719b	294	hose->pci_mem->bus_start,
ba5feb12 ES	295	hose->pci_mem->bus_start + hose->pci_mem->size - 1,
	296	hose->pci_mem->phys_start,
	297	hose->pci_mem->phys_start + hose->pci_mem->size - 1);
c609719b WD	298	}
c609719b WD	299
a179012e KG	300	if (hose->pci_prefetch) {
	301	pciauto_region_init(hose->pci_prefetch);
	302
ba5feb12 ES	303	DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [%lx-%lx],\n"
ba5feb12 ES	304	"\t\tPhysical Memory [%x-%x]\n",
a179012e	305	hose->pci_prefetch->bus_start,
ba5feb12 ES	306	hose->pci_prefetch->bus_start + hose->pci_prefetch->size - 1,
	307	hose->pci_prefetch->phys_start,
	308	hose->pci_prefetch->phys_start +
	309	hose->pci_prefetch->size - 1);
a179012e KG	310	}
a179012e KG	311
3c74e32a	312	if (hose->pci_io) {
c609719b WD	313	pciauto_region_init(hose->pci_io);
c609719b WD	314
ba5feb12 ES	315	DEBUGF("PCI Autoconfig: Bus I/O region: [%lx-%lx],\n"
ba5feb12 ES	316	"\t\tPhysical Memory: [%x-%x]\n",
c609719b	317	hose->pci_io->bus_start,
ba5feb12 ES	318	hose->pci_io->bus_start + hose->pci_io->size - 1,
	319	hose->pci_io->phys_start,
	320	hose->pci_io->phys_start + hose->pci_io->size - 1);
	321
c609719b WD	322	}
	323	}
	324
c7de829c WD	325	/* HJF: Changed this to return int. I think this is required
	326	* to get the correct result when scanning bridges
	327	*/
	328	int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
c609719b	329	{
c7de829c	330	unsigned int sub_bus = PCI_BUS(dev);
c609719b WD	331	unsigned short class;
c609719b WD	332	unsigned char prg_iface;
5653fc33	333	int n;
c609719b WD	334
	335	pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
	336
3c74e32a	337	switch(class) {
5dc210de ES	338	case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
	339	DEBUGF("PCI AutoConfig: Found PowerPC device\n");
	340	pciauto_setup_device(hose, dev, 6, hose->pci_mem,
	341	hose->pci_prefetch, hose->pci_io);
	342	break;
	343
c609719b	344	case PCI_CLASS_BRIDGE_PCI:
db2f721f	345	hose->current_busno++;
a179012e	346	pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b	347
db2f721f	348	DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
cd37d9e6	349
3c74e32a	350	/* Passing in current_busno allows for sibling P2P bridges */
5653fc33	351	pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
cd37d9e6	352	/*
3c74e32a	353	* need to figure out if this is a subordinate bridge on the bus
5653fc33 WD	354	* to be able to properly set the pri/sec/sub bridge registers.
	355	*/
	356	n = pci_hose_scan_bus(hose, hose->current_busno);
	357
3c74e32a	358	/* figure out the deepest we've gone for this leg */
5653fc33	359	sub_bus = max(n, sub_bus);
db2f721f	360	pciauto_postscan_setup_bridge(hose, dev, sub_bus);
5653fc33	361
db2f721f	362	sub_bus = hose->current_busno;
c609719b WD	363	break;
	364
	365	case PCI_CLASS_STORAGE_IDE:
	366	pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
3c74e32a WD	367	if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
	368	DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
	369	return sub_bus;
	370	}
c609719b	371
a179012e	372	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b WD	373	break;
c609719b WD	374
1cb8e980 WD	375	case PCI_CLASS_BRIDGE_CARDBUS:
1cb8e980 WD	376	/* just do a minimal setup of the bridge, let the OS take care of the rest */
a179012e	377	pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
1cb8e980	378
3c74e32a	379	DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
1cb8e980 WD	380
	381	hose->current_busno++;
	382	break;
	383
f33fca22	384	#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
e0ac62d7 WD	385	case PCI_CLASS_BRIDGE_OTHER:
	386	DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
	387	PCI_DEV(dev));
	388	break;
	389	#endif
6902df56 RJ	390	#ifdef CONFIG_MPC834X
	391	case PCI_CLASS_BRIDGE_OTHER:
	392	/*
	393	* The host/PCI bridge 1 seems broken in 8349 - it presents
	394	* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
	395	* device claiming resources io/mem/irq.. we only allow for
	396	* the PIMMR window to be allocated (BAR0 - 1MB size)
	397	*/
	398	DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
a179012e	399	pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
6902df56 RJ	400	break;
6902df56 RJ	401	#endif
c609719b	402	default:
a179012e	403	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b WD	404	break;
c609719b WD	405	}
c7de829c WD	406
c7de829c WD	407	return sub_bus;
c609719b	408	}