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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / drivers / qe / uec.c
CommitLineData
7737d5c6
DL		 1/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include "common.h"
23#include "net.h"
24#include "malloc.h"
25#include "asm/errno.h"
26#include "asm/io.h"
27#include "asm/immap_qe.h"
28#include "qe.h"
29#include "uccf.h"
30#include "uec.h"
31#include "uec_phy.h"
d5d28fe4 32#include "miiphy.h"
7737d5c6 33
7737d5c6
DL		 34#ifdef CONFIG_UEC_ETH1
35static uec_info_t eth1_uec_info = {
36 .uf_info = {
6d0f6bcf
JCPV		 37 .ucc_num = CONFIG_SYS_UEC1_UCC_NUM,
38 .rx_clock = CONFIG_SYS_UEC1_RX_CLK,
39 .tx_clock = CONFIG_SYS_UEC1_TX_CLK,
40 .eth_type = CONFIG_SYS_UEC1_ETH_TYPE,
7737d5c6 41 },
6d0f6bcf 42#if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH)
2465665b
DS		 43 .num_threads_tx = UEC_NUM_OF_THREADS_1,
44 .num_threads_rx = UEC_NUM_OF_THREADS_1,
45#else
7737d5c6
DL		 46 .num_threads_tx = UEC_NUM_OF_THREADS_4,
47 .num_threads_rx = UEC_NUM_OF_THREADS_4,
2465665b 48#endif
7737d5c6
DL		 49 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
50 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
51 .tx_bd_ring_len = 16,
52 .rx_bd_ring_len = 16,
6d0f6bcf
JCPV		 53 .phy_address = CONFIG_SYS_UEC1_PHY_ADDR,
54 .enet_interface = CONFIG_SYS_UEC1_INTERFACE_MODE,
7737d5c6
DL		 55};
56#endif
57#ifdef CONFIG_UEC_ETH2
58static uec_info_t eth2_uec_info = {
59 .uf_info = {
6d0f6bcf
JCPV		 60 .ucc_num = CONFIG_SYS_UEC2_UCC_NUM,
61 .rx_clock = CONFIG_SYS_UEC2_RX_CLK,
62 .tx_clock = CONFIG_SYS_UEC2_TX_CLK,
63 .eth_type = CONFIG_SYS_UEC2_ETH_TYPE,
7737d5c6 64 },
6d0f6bcf 65#if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH)
2465665b
DS		 66 .num_threads_tx = UEC_NUM_OF_THREADS_1,
67 .num_threads_rx = UEC_NUM_OF_THREADS_1,
68#else
7737d5c6
DL		 69 .num_threads_tx = UEC_NUM_OF_THREADS_4,
70 .num_threads_rx = UEC_NUM_OF_THREADS_4,
2465665b 71#endif
7737d5c6
DL		 72 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
73 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
74 .tx_bd_ring_len = 16,
75 .rx_bd_ring_len = 16,
6d0f6bcf
JCPV		 76 .phy_address = CONFIG_SYS_UEC2_PHY_ADDR,
77 .enet_interface = CONFIG_SYS_UEC2_INTERFACE_MODE,
7737d5c6
DL		 78};
79#endif
ccf21c31
JT		 80#ifdef CONFIG_UEC_ETH3
81static uec_info_t eth3_uec_info = {
82 .uf_info = {
6d0f6bcf
JCPV		 83 .ucc_num = CONFIG_SYS_UEC3_UCC_NUM,
84 .rx_clock = CONFIG_SYS_UEC3_RX_CLK,
85 .tx_clock = CONFIG_SYS_UEC3_TX_CLK,
86 .eth_type = CONFIG_SYS_UEC3_ETH_TYPE,
ccf21c31 87 },
6d0f6bcf 88#if (CONFIG_SYS_UEC3_ETH_TYPE == FAST_ETH)
2465665b
DS		 89 .num_threads_tx = UEC_NUM_OF_THREADS_1,
90 .num_threads_rx = UEC_NUM_OF_THREADS_1,
91#else
ccf21c31
JT		 92 .num_threads_tx = UEC_NUM_OF_THREADS_4,
93 .num_threads_rx = UEC_NUM_OF_THREADS_4,
2465665b 94#endif
ccf21c31
JT		 95 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
96 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
97 .tx_bd_ring_len = 16,
98 .rx_bd_ring_len = 16,
6d0f6bcf
JCPV		 99 .phy_address = CONFIG_SYS_UEC3_PHY_ADDR,
100 .enet_interface = CONFIG_SYS_UEC3_INTERFACE_MODE,
ccf21c31
JT		 101};
102#endif
2465665b
DS		 103#ifdef CONFIG_UEC_ETH4
104static uec_info_t eth4_uec_info = {
105 .uf_info = {
6d0f6bcf
JCPV		 106 .ucc_num = CONFIG_SYS_UEC4_UCC_NUM,
107 .rx_clock = CONFIG_SYS_UEC4_RX_CLK,
108 .tx_clock = CONFIG_SYS_UEC4_TX_CLK,
109 .eth_type = CONFIG_SYS_UEC4_ETH_TYPE,
2465665b 110 },
6d0f6bcf 111#if (CONFIG_SYS_UEC4_ETH_TYPE == FAST_ETH)
2465665b
DS		 112 .num_threads_tx = UEC_NUM_OF_THREADS_1,
113 .num_threads_rx = UEC_NUM_OF_THREADS_1,
114#else
115 .num_threads_tx = UEC_NUM_OF_THREADS_4,
116 .num_threads_rx = UEC_NUM_OF_THREADS_4,
117#endif
118 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
119 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
120 .tx_bd_ring_len = 16,
121 .rx_bd_ring_len = 16,
6d0f6bcf
JCPV		 122 .phy_address = CONFIG_SYS_UEC4_PHY_ADDR,
123 .enet_interface = CONFIG_SYS_UEC4_INTERFACE_MODE,
2465665b
DS		 124};
125#endif
c68a05fe 126#ifdef CONFIG_UEC_ETH5
127static uec_info_t eth5_uec_info = {
128 .uf_info = {
6d0f6bcf
JCPV		 129 .ucc_num = CONFIG_SYS_UEC5_UCC_NUM,
130 .rx_clock = CONFIG_SYS_UEC5_RX_CLK,
131 .tx_clock = CONFIG_SYS_UEC5_TX_CLK,
132 .eth_type = CONFIG_SYS_UEC5_ETH_TYPE,
c68a05fe 133 },
6d0f6bcf 134#if (CONFIG_SYS_UEC5_ETH_TYPE == FAST_ETH)
c68a05fe 135 .num_threads_tx = UEC_NUM_OF_THREADS_1,
136 .num_threads_rx = UEC_NUM_OF_THREADS_1,
137#else
138 .num_threads_tx = UEC_NUM_OF_THREADS_4,
139 .num_threads_rx = UEC_NUM_OF_THREADS_4,
140#endif
141 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
142 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
143 .tx_bd_ring_len = 16,
144 .rx_bd_ring_len = 16,
6d0f6bcf
JCPV		 145 .phy_address = CONFIG_SYS_UEC5_PHY_ADDR,
146 .enet_interface = CONFIG_SYS_UEC5_INTERFACE_MODE,
c68a05fe 147};
148#endif
149#ifdef CONFIG_UEC_ETH6
150static uec_info_t eth6_uec_info = {
151 .uf_info = {
6d0f6bcf
JCPV		 152 .ucc_num = CONFIG_SYS_UEC6_UCC_NUM,
153 .rx_clock = CONFIG_SYS_UEC6_RX_CLK,
154 .tx_clock = CONFIG_SYS_UEC6_TX_CLK,
155 .eth_type = CONFIG_SYS_UEC6_ETH_TYPE,
c68a05fe 156 },
6d0f6bcf 157#if (CONFIG_SYS_UEC6_ETH_TYPE == FAST_ETH)
c68a05fe 158 .num_threads_tx = UEC_NUM_OF_THREADS_1,
159 .num_threads_rx = UEC_NUM_OF_THREADS_1,
160#else
161 .num_threads_tx = UEC_NUM_OF_THREADS_4,
162 .num_threads_rx = UEC_NUM_OF_THREADS_4,
163#endif
164 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
165 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
166 .tx_bd_ring_len = 16,
167 .rx_bd_ring_len = 16,
6d0f6bcf
JCPV		 168 .phy_address = CONFIG_SYS_UEC6_PHY_ADDR,
169 .enet_interface = CONFIG_SYS_UEC6_INTERFACE_MODE,
c68a05fe 170};
171#endif
ccf21c31 172
c68a05fe 173#define MAXCONTROLLERS (6)
d5d28fe4
DS		 174
175static struct eth_device *devlist[MAXCONTROLLERS];
176
d5d28fe4
DS		 177u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
178void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
179
7737d5c6
DL		 180static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
181{
182 uec_t *uec_regs;
183 u32 maccfg1;
184
185 if (!uec) {
186 printf("%s: uec not initial\n", __FUNCTION__);
187 return -EINVAL;
188 }
189 uec_regs = uec->uec_regs;
190
191 maccfg1 = in_be32(&uec_regs->maccfg1);
192
193 if (mode & COMM_DIR_TX) {
194 maccfg1 |= MACCFG1_ENABLE_TX;
195 out_be32(&uec_regs->maccfg1, maccfg1);
196 uec->mac_tx_enabled = 1;
197 }
198
199 if (mode & COMM_DIR_RX) {
200 maccfg1 |= MACCFG1_ENABLE_RX;
201 out_be32(&uec_regs->maccfg1, maccfg1);
202 uec->mac_rx_enabled = 1;
203 }
204
205 return 0;
206}
207
208static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
209{
210 uec_t *uec_regs;
211 u32 maccfg1;
212
213 if (!uec) {
214 printf("%s: uec not initial\n", __FUNCTION__);
215 return -EINVAL;
216 }
217 uec_regs = uec->uec_regs;
218
219 maccfg1 = in_be32(&uec_regs->maccfg1);
220
221 if (mode & COMM_DIR_TX) {
222 maccfg1 &= ~MACCFG1_ENABLE_TX;
223 out_be32(&uec_regs->maccfg1, maccfg1);
224 uec->mac_tx_enabled = 0;
225 }
226
227 if (mode & COMM_DIR_RX) {
228 maccfg1 &= ~MACCFG1_ENABLE_RX;
229 out_be32(&uec_regs->maccfg1, maccfg1);
230 uec->mac_rx_enabled = 0;
231 }
232
233 return 0;
234}
235
236static int uec_graceful_stop_tx(uec_private_t *uec)
237{
238 ucc_fast_t *uf_regs;
239 u32 cecr_subblock;
240 u32 ucce;
241
242 if (!uec || !uec->uccf) {
243 printf("%s: No handle passed.\n", __FUNCTION__);
244 return -EINVAL;
245 }
246
247 uf_regs = uec->uccf->uf_regs;
248
249 /* Clear the grace stop event */
250 out_be32(&uf_regs->ucce, UCCE_GRA);
251
252 /* Issue host command */
253 cecr_subblock =
254 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
255 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
256 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
257
258 /* Wait for command to complete */
259 do {
260 ucce = in_be32(&uf_regs->ucce);
261 } while (! (ucce & UCCE_GRA));
262
263 uec->grace_stopped_tx = 1;
264
265 return 0;
266}
267
268static int uec_graceful_stop_rx(uec_private_t *uec)
269{
270 u32 cecr_subblock;
271 u8 ack;
272
273 if (!uec) {
274 printf("%s: No handle passed.\n", __FUNCTION__);
275 return -EINVAL;
276 }
277
278 if (!uec->p_rx_glbl_pram) {
279 printf("%s: No init rx global parameter\n", __FUNCTION__);
280 return -EINVAL;
281 }
282
283 /* Clear acknowledge bit */
284 ack = uec->p_rx_glbl_pram->rxgstpack;
285 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
286 uec->p_rx_glbl_pram->rxgstpack = ack;
287
288 /* Keep issuing cmd and checking ack bit until it is asserted */
289 do {
290 /* Issue host command */
291 cecr_subblock =
292 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
293 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
294 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
295 ack = uec->p_rx_glbl_pram->rxgstpack;
296 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
297
298 uec->grace_stopped_rx = 1;
299
300 return 0;
301}
302
303static int uec_restart_tx(uec_private_t *uec)
304{
305 u32 cecr_subblock;
306
307 if (!uec || !uec->uec_info) {
308 printf("%s: No handle passed.\n", __FUNCTION__);
309 return -EINVAL;
310 }
311
312 cecr_subblock =
313 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
314 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
315 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
316
317 uec->grace_stopped_tx = 0;
318
319 return 0;
320}
321
322static int uec_restart_rx(uec_private_t *uec)
323{
324 u32 cecr_subblock;
325
326 if (!uec || !uec->uec_info) {
327 printf("%s: No handle passed.\n", __FUNCTION__);
328 return -EINVAL;
329 }
330
331 cecr_subblock =
332 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
333 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
334 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
335
336 uec->grace_stopped_rx = 0;
337
338 return 0;
339}
340
341static int uec_open(uec_private_t *uec, comm_dir_e mode)
342{
343 ucc_fast_private_t *uccf;
344
345 if (!uec || !uec->uccf) {
346 printf("%s: No handle passed.\n", __FUNCTION__);
347 return -EINVAL;
348 }
349 uccf = uec->uccf;
350
351 /* check if the UCC number is in range. */
352 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
353 printf("%s: ucc_num out of range.\n", __FUNCTION__);
354 return -EINVAL;
355 }
356
357 /* Enable MAC */
358 uec_mac_enable(uec, mode);
359
360 /* Enable UCC fast */
361 ucc_fast_enable(uccf, mode);
362
363 /* RISC microcode start */
364 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
365 uec_restart_tx(uec);
366 }
367 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
368 uec_restart_rx(uec);
369 }
370
371 return 0;
372}
373
374static int uec_stop(uec_private_t *uec, comm_dir_e mode)
375{
376 ucc_fast_private_t *uccf;
377
378 if (!uec || !uec->uccf) {
379 printf("%s: No handle passed.\n", __FUNCTION__);
380 return -EINVAL;
381 }
382 uccf = uec->uccf;
383
384 /* check if the UCC number is in range. */
385 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
386 printf("%s: ucc_num out of range.\n", __FUNCTION__);
387 return -EINVAL;
388 }
389 /* Stop any transmissions */
390 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
391 uec_graceful_stop_tx(uec);
392 }
393 /* Stop any receptions */
394 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
395 uec_graceful_stop_rx(uec);
396 }
397
398 /* Disable the UCC fast */
399 ucc_fast_disable(uec->uccf, mode);
400
401 /* Disable the MAC */
402 uec_mac_disable(uec, mode);
403
404 return 0;
405}
406
407static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
408{
409 uec_t *uec_regs;
410 u32 maccfg2;
411
412 if (!uec) {
413 printf("%s: uec not initial\n", __FUNCTION__);
414 return -EINVAL;
415 }
416 uec_regs = uec->uec_regs;
417
418 if (duplex == DUPLEX_HALF) {
419 maccfg2 = in_be32(&uec_regs->maccfg2);
420 maccfg2 &= ~MACCFG2_FDX;
421 out_be32(&uec_regs->maccfg2, maccfg2);
422 }
423
424 if (duplex == DUPLEX_FULL) {
425 maccfg2 = in_be32(&uec_regs->maccfg2);
426 maccfg2 |= MACCFG2_FDX;
427 out_be32(&uec_regs->maccfg2, maccfg2);
428 }
429
430 return 0;
431}
432
433static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
434{
435 enet_interface_e enet_if_mode;
53677ef1 436 uec_info_t *uec_info;
7737d5c6
DL		 437 uec_t *uec_regs;
438 u32 upsmr;
439 u32 maccfg2;
440
441 if (!uec) {
442 printf("%s: uec not initial\n", __FUNCTION__);
443 return -EINVAL;
444 }
445
446 uec_info = uec->uec_info;
447 uec_regs = uec->uec_regs;
448 enet_if_mode = if_mode;
449
450 maccfg2 = in_be32(&uec_regs->maccfg2);
451 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
452
453 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
454 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
455
456 switch (enet_if_mode) {
457 case ENET_100_MII:
458 case ENET_10_MII:
459 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
460 break;
461 case ENET_1000_GMII:
462 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
463 break;
464 case ENET_1000_TBI:
465 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
466 upsmr |= UPSMR_TBIM;
467 break;
468 case ENET_1000_RTBI:
469 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
470 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
471 break;
6a600c3a 472 case ENET_1000_RGMII_RXID:
41410eee 473 case ENET_1000_RGMII_ID:
7737d5c6
DL		 474 case ENET_1000_RGMII:
475 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
476 upsmr |= UPSMR_RPM;
477 break;
478 case ENET_100_RGMII:
479 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
480 upsmr |= UPSMR_RPM;
481 break;
482 case ENET_10_RGMII:
483 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
484 upsmr |= (UPSMR_RPM | UPSMR_R10M);
485 break;
486 case ENET_100_RMII:
487 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
488 upsmr |= UPSMR_RMM;
489 break;
490 case ENET_10_RMII:
491 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
492 upsmr |= (UPSMR_R10M | UPSMR_RMM);
493 break;
494 default:
495 return -EINVAL;
496 break;
497 }
498 out_be32(&uec_regs->maccfg2, maccfg2);
499 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
500
501 return 0;
502}
503
da9d4610 504static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
7737d5c6
DL		 505{
506 uint timeout = 0x1000;
507 u32 miimcfg = 0;
508
da9d4610 509 miimcfg = in_be32(&uec_mii_regs->miimcfg);
7737d5c6 510 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
da9d4610 511 out_be32(&uec_mii_regs->miimcfg, miimcfg);
7737d5c6
DL		 512
513 /* Wait until the bus is free */
da9d4610 514 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
7737d5c6
DL		 515 if (timeout <= 0) {
516 printf("%s: The MII Bus is stuck!", __FUNCTION__);
517 return -ETIMEDOUT;
518 }
519
520 return 0;
521}
522
523static int init_phy(struct eth_device *dev)
524{
525 uec_private_t *uec;
da9d4610 526 uec_mii_t *umii_regs;
7737d5c6
DL		 527 struct uec_mii_info *mii_info;
528 struct phy_info *curphy;
529 int err;
530
531 uec = (uec_private_t *)dev->priv;
da9d4610 532 umii_regs = uec->uec_mii_regs;
7737d5c6
DL		 533
534 uec->oldlink = 0;
535 uec->oldspeed = 0;
536 uec->oldduplex = -1;
537
538 mii_info = malloc(sizeof(*mii_info));
539 if (!mii_info) {
540 printf("%s: Could not allocate mii_info", dev->name);
541 return -ENOMEM;
542 }
543 memset(mii_info, 0, sizeof(*mii_info));
544
24c3aca3
DL		 545 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
546 mii_info->speed = SPEED_1000;
547 } else {
548 mii_info->speed = SPEED_100;
549 }
550
7737d5c6
DL		 551 mii_info->duplex = DUPLEX_FULL;
552 mii_info->pause = 0;
553 mii_info->link = 1;
554
555 mii_info->advertising = (ADVERTISED_10baseT_Half |
556 ADVERTISED_10baseT_Full |
557 ADVERTISED_100baseT_Half |
558 ADVERTISED_100baseT_Full |
559 ADVERTISED_1000baseT_Full);
560 mii_info->autoneg = 1;
561 mii_info->mii_id = uec->uec_info->phy_address;
562 mii_info->dev = dev;
563
da9d4610
AF		 564 mii_info->mdio_read = &uec_read_phy_reg;
565 mii_info->mdio_write = &uec_write_phy_reg;
7737d5c6
DL		 566
567 uec->mii_info = mii_info;
568
ee62ed32
KP		 569 qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
570
da9d4610 571 if (init_mii_management_configuration(umii_regs)) {
7737d5c6
DL		 572 printf("%s: The MII Bus is stuck!", dev->name);
573 err = -1;
574 goto bus_fail;
575 }
576
577 /* get info for this PHY */
da9d4610 578 curphy = uec_get_phy_info(uec->mii_info);
7737d5c6
DL		 579 if (!curphy) {
580 printf("%s: No PHY found", dev->name);
581 err = -1;
582 goto no_phy;
583 }
584
585 mii_info->phyinfo = curphy;
586
587 /* Run the commands which initialize the PHY */
588 if (curphy->init) {
589 err = curphy->init(uec->mii_info);
590 if (err)
591 goto phy_init_fail;
592 }
593
594 return 0;
595
596phy_init_fail:
597no_phy:
598bus_fail:
599 free(mii_info);
600 return err;
601}
602
603static void adjust_link(struct eth_device *dev)
604{
605 uec_private_t *uec = (uec_private_t *)dev->priv;
606 uec_t *uec_regs;
607 struct uec_mii_info *mii_info = uec->mii_info;
608
609 extern void change_phy_interface_mode(struct eth_device *dev,
610 enet_interface_e mode);
611 uec_regs = uec->uec_regs;
612
613 if (mii_info->link) {
614 /* Now we make sure that we can be in full duplex mode.
615 * If not, we operate in half-duplex mode. */
616 if (mii_info->duplex != uec->oldduplex) {
617 if (!(mii_info->duplex)) {
618 uec_set_mac_duplex(uec, DUPLEX_HALF);
619 printf("%s: Half Duplex\n", dev->name);
620 } else {
621 uec_set_mac_duplex(uec, DUPLEX_FULL);
622 printf("%s: Full Duplex\n", dev->name);
623 }
624 uec->oldduplex = mii_info->duplex;
625 }
626
627 if (mii_info->speed != uec->oldspeed) {
24c3aca3
DL		 628 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
629 switch (mii_info->speed) {
7737d5c6
DL		 630 case 1000:
631 break;
632 case 100:
633 printf ("switching to rgmii 100\n");
634 /* change phy to rgmii 100 */
635 change_phy_interface_mode(dev,
636 ENET_100_RGMII);
637 /* change the MAC interface mode */
638 uec_set_mac_if_mode(uec,ENET_100_RGMII);
639 break;
640 case 10:
641 printf ("switching to rgmii 10\n");
642 /* change phy to rgmii 10 */
643 change_phy_interface_mode(dev,
644 ENET_10_RGMII);
645 /* change the MAC interface mode */
646 uec_set_mac_if_mode(uec,ENET_10_RGMII);
647 break;
648 default:
649 printf("%s: Ack,Speed(%d)is illegal\n",
650 dev->name, mii_info->speed);
651 break;
24c3aca3 652 }
7737d5c6
DL		 653 }
654
655 printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
656 uec->oldspeed = mii_info->speed;
657 }
658
659 if (!uec->oldlink) {
660 printf("%s: Link is up\n", dev->name);
661 uec->oldlink = 1;
662 }
663
664 } else { /* if (mii_info->link) */
665 if (uec->oldlink) {
666 printf("%s: Link is down\n", dev->name);
667 uec->oldlink = 0;
668 uec->oldspeed = 0;
669 uec->oldduplex = -1;
670 }
671 }
672}
673
674static void phy_change(struct eth_device *dev)
675{
676 uec_private_t *uec = (uec_private_t *)dev->priv;
7737d5c6
DL		 677
678 /* Update the link, speed, duplex */
ee62ed32 679 uec->mii_info->phyinfo->read_status(uec->mii_info);
7737d5c6
DL		 680
681 /* Adjust the interface according to speed */
ee62ed32 682 adjust_link(dev);
7737d5c6
DL		 683}
684
d9d78ee4
BW		 685#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
686 && !defined(BITBANGMII)
687
688/*
689 * Read a MII PHY register.
690 *
691 * Returns:
692 * 0 on success
693 */
694static int uec_miiphy_read(char *devname, unsigned char addr,
695 unsigned char reg, unsigned short *value)
696{
697 *value = uec_read_phy_reg(devlist[0], addr, reg);
698
699 return 0;
700}
701
702/*
703 * Write a MII PHY register.
704 *
705 * Returns:
706 * 0 on success
707 */
708static int uec_miiphy_write(char *devname, unsigned char addr,
709 unsigned char reg, unsigned short value)
710{
711 uec_write_phy_reg(devlist[0], addr, reg, value);
712
713 return 0;
714}
715
716#endif
717
7737d5c6
DL		 718static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
719{
720 uec_t *uec_regs;
721 u32 mac_addr1;
722 u32 mac_addr2;
723
724 if (!uec) {
725 printf("%s: uec not initial\n", __FUNCTION__);
726 return -EINVAL;
727 }
728
729 uec_regs = uec->uec_regs;
730
731 /* if a station address of 0x12345678ABCD, perform a write to
732 MACSTNADDR1 of 0xCDAB7856,
733 MACSTNADDR2 of 0x34120000 */
734
735 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
736 (mac_addr[3] << 8) | (mac_addr[2]);
737 out_be32(&uec_regs->macstnaddr1, mac_addr1);
738
739 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
740 out_be32(&uec_regs->macstnaddr2, mac_addr2);
741
742 return 0;
743}
744
745static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
746 int *threads_num_ret)
747{
748 int num_threads_numerica;
749
750 switch (threads_num) {
751 case UEC_NUM_OF_THREADS_1:
752 num_threads_numerica = 1;
753 break;
754 case UEC_NUM_OF_THREADS_2:
755 num_threads_numerica = 2;
756 break;
757 case UEC_NUM_OF_THREADS_4:
758 num_threads_numerica = 4;
759 break;
760 case UEC_NUM_OF_THREADS_6:
761 num_threads_numerica = 6;
762 break;
763 case UEC_NUM_OF_THREADS_8:
764 num_threads_numerica = 8;
765 break;
766 default:
767 printf("%s: Bad number of threads value.",
768 __FUNCTION__);
769 return -EINVAL;
770 }
771
772 *threads_num_ret = num_threads_numerica;
773
774 return 0;
775}
776
777static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
778{
779 uec_info_t *uec_info;
780 u32 end_bd;
781 u8 bmrx = 0;
782 int i;
783
784 uec_info = uec->uec_info;
785
786 /* Alloc global Tx parameter RAM page */
787 uec->tx_glbl_pram_offset = qe_muram_alloc(
788 sizeof(uec_tx_global_pram_t),
789 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
790 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
791 qe_muram_addr(uec->tx_glbl_pram_offset);
792
793 /* Zero the global Tx prameter RAM */
794 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
795
796 /* Init global Tx parameter RAM */
797
798 /* TEMODER, RMON statistics disable, one Tx queue */
799 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
800
801 /* SQPTR */
802 uec->send_q_mem_reg_offset = qe_muram_alloc(
803 sizeof(uec_send_queue_qd_t),
804 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
805 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
806 qe_muram_addr(uec->send_q_mem_reg_offset);
807 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
808
809 /* Setup the table with TxBDs ring */
810 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
811 * SIZEOFBD;
812 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
813 (u32)(uec->p_tx_bd_ring));
814 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
815 end_bd);
816
817 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
818 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
819
820 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
821 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
822
823 /* TSTATE, global snooping, big endian, the CSB bus selected */
824 bmrx = BMR_INIT_VALUE;
825 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
826
827 /* IPH_Offset */
828 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
829 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
830 }
831
832 /* VTAG table */
833 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
834 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
835 }
836
837 /* TQPTR */
838 uec->thread_dat_tx_offset = qe_muram_alloc(
839 num_threads_tx * sizeof(uec_thread_data_tx_t) +
840 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
841
842 uec->p_thread_data_tx = (uec_thread_data_tx_t *)
843 qe_muram_addr(uec->thread_dat_tx_offset);
844 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
845}
846
847static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
848{
849 u8 bmrx = 0;
850 int i;
851 uec_82xx_address_filtering_pram_t *p_af_pram;
852
853 /* Allocate global Rx parameter RAM page */
854 uec->rx_glbl_pram_offset = qe_muram_alloc(
855 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
856 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
857 qe_muram_addr(uec->rx_glbl_pram_offset);
858
859 /* Zero Global Rx parameter RAM */
860 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
861
862 /* Init global Rx parameter RAM */
863 /* REMODER, Extended feature mode disable, VLAN disable,
864 LossLess flow control disable, Receive firmware statisic disable,
865 Extended address parsing mode disable, One Rx queues,
866 Dynamic maximum/minimum frame length disable, IP checksum check
867 disable, IP address alignment disable
868 */
869 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
870
871 /* RQPTR */
872 uec->thread_dat_rx_offset = qe_muram_alloc(
873 num_threads_rx * sizeof(uec_thread_data_rx_t),
874 UEC_THREAD_DATA_ALIGNMENT);
875 uec->p_thread_data_rx = (uec_thread_data_rx_t *)
876 qe_muram_addr(uec->thread_dat_rx_offset);
877 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
878
879 /* Type_or_Len */
880 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
881
882 /* RxRMON base pointer, we don't need it */
883 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
884
885 /* IntCoalescingPTR, we don't need it, no interrupt */
886 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
887
888 /* RSTATE, global snooping, big endian, the CSB bus selected */
889 bmrx = BMR_INIT_VALUE;
890 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
891
892 /* MRBLR */
893 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
894
895 /* RBDQPTR */
896 uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
897 sizeof(uec_rx_bd_queues_entry_t) + \
898 sizeof(uec_rx_prefetched_bds_t),
899 UEC_RX_BD_QUEUES_ALIGNMENT);
900 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
901 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
902
903 /* Zero it */
904 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
905 sizeof(uec_rx_prefetched_bds_t));
906 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
907 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
908 (u32)uec->p_rx_bd_ring);
909
910 /* MFLR */
911 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
912 /* MINFLR */
913 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
914 /* MAXD1 */
915 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
916 /* MAXD2 */
917 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
918 /* ECAM_PTR */
919 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
920 /* L2QT */
921 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
922 /* L3QT */
923 for (i = 0; i < 8; i++) {
924 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
925 }
926
927 /* VLAN_TYPE */
928 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
929 /* TCI */
930 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
931
932 /* Clear PQ2 style address filtering hash table */
933 p_af_pram = (uec_82xx_address_filtering_pram_t *) \
934 uec->p_rx_glbl_pram->addressfiltering;
935
936 p_af_pram->iaddr_h = 0;
937 p_af_pram->iaddr_l = 0;
938 p_af_pram->gaddr_h = 0;
939 p_af_pram->gaddr_l = 0;
940}
941
942static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
943 int thread_tx, int thread_rx)
944{
945 uec_init_cmd_pram_t *p_init_enet_param;
946 u32 init_enet_param_offset;
947 uec_info_t *uec_info;
948 int i;
949 int snum;
950 u32 init_enet_offset;
951 u32 entry_val;
952 u32 command;
953 u32 cecr_subblock;
954
955 uec_info = uec->uec_info;
956
957 /* Allocate init enet command parameter */
958 uec->init_enet_param_offset = qe_muram_alloc(
959 sizeof(uec_init_cmd_pram_t), 4);
960 init_enet_param_offset = uec->init_enet_param_offset;
961 uec->p_init_enet_param = (uec_init_cmd_pram_t *)
962 qe_muram_addr(uec->init_enet_param_offset);
963
964 /* Zero init enet command struct */
965 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
966
967 /* Init the command struct */
968 p_init_enet_param = uec->p_init_enet_param;
969 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
970 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
971 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
972 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
973 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
974 p_init_enet_param->largestexternallookupkeysize = 0;
975
976 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
977 << ENET_INIT_PARAM_RGF_SHIFT;
978 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
979 << ENET_INIT_PARAM_TGF_SHIFT;
980
981 /* Init Rx global parameter pointer */
982 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
983 (u32)uec_info->riscRx;
984
985 /* Init Rx threads */
986 for (i = 0; i < (thread_rx + 1); i++) {
987 if ((snum = qe_get_snum()) < 0) {
988 printf("%s can not get snum\n", __FUNCTION__);
989 return -ENOMEM;
990 }
991
992 if (i==0) {
993 init_enet_offset = 0;
994 } else {
995 init_enet_offset = qe_muram_alloc(
996 sizeof(uec_thread_rx_pram_t),
997 UEC_THREAD_RX_PRAM_ALIGNMENT);
998 }
999
1000 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
1001 init_enet_offset | (u32)uec_info->riscRx;
1002 p_init_enet_param->rxthread[i] = entry_val;
1003 }
1004
1005 /* Init Tx global parameter pointer */
1006 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
1007 (u32)uec_info->riscTx;
1008
1009 /* Init Tx threads */
1010 for (i = 0; i < thread_tx; i++) {
1011 if ((snum = qe_get_snum()) < 0) {
1012 printf("%s can not get snum\n", __FUNCTION__);
1013 return -ENOMEM;
1014 }
1015
1016 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
1017 UEC_THREAD_TX_PRAM_ALIGNMENT);
1018
1019 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
1020 init_enet_offset | (u32)uec_info->riscTx;
1021 p_init_enet_param->txthread[i] = entry_val;
1022 }
1023
1024 __asm__ __volatile__("sync");
1025
1026 /* Issue QE command */
1027 command = QE_INIT_TX_RX;
1028 cecr_subblock = ucc_fast_get_qe_cr_subblock(
1029 uec->uec_info->uf_info.ucc_num);
1030 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
1031 init_enet_param_offset);
1032
1033 return 0;
1034}
1035
1036static int uec_startup(uec_private_t *uec)
1037{
1038 uec_info_t *uec_info;
1039 ucc_fast_info_t *uf_info;
1040 ucc_fast_private_t *uccf;
1041 ucc_fast_t *uf_regs;
1042 uec_t *uec_regs;
1043 int num_threads_tx;
1044 int num_threads_rx;
1045 u32 utbipar;
1046 enet_interface_e enet_interface;
1047 u32 length;
1048 u32 align;
1049 qe_bd_t *bd;
1050 u8 *buf;
1051 int i;
1052
1053 if (!uec || !uec->uec_info) {
1054 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
1055 return -EINVAL;
1056 }
1057
1058 uec_info = uec->uec_info;
1059 uf_info = &(uec_info->uf_info);
1060
1061 /* Check if Rx BD ring len is illegal */
1062 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
1063 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
1064 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1065 __FUNCTION__);
1066 return -EINVAL;
1067 }
1068
1069 /* Check if Tx BD ring len is illegal */
1070 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
1071 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1072 __FUNCTION__);
1073 return -EINVAL;
1074 }
1075
1076 /* Check if MRBLR is illegal */
1077 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
1078 printf("%s: max rx buffer length must be mutliple of 128.\n",
1079 __FUNCTION__);
1080 return -EINVAL;
1081 }
1082
1083 /* Both Rx and Tx are stopped */
1084 uec->grace_stopped_rx = 1;
1085 uec->grace_stopped_tx = 1;
1086
1087 /* Init UCC fast */
1088 if (ucc_fast_init(uf_info, &uccf)) {
1089 printf("%s: failed to init ucc fast\n", __FUNCTION__);
1090 return -ENOMEM;
1091 }
1092
1093 /* Save uccf */
1094 uec->uccf = uccf;
1095
1096 /* Convert the Tx threads number */
1097 if (uec_convert_threads_num(uec_info->num_threads_tx,
1098 &num_threads_tx)) {
1099 return -EINVAL;
1100 }
1101
1102 /* Convert the Rx threads number */
1103 if (uec_convert_threads_num(uec_info->num_threads_rx,
1104 &num_threads_rx)) {
1105 return -EINVAL;
1106 }
1107
1108 uf_regs = uccf->uf_regs;
1109
1110 /* UEC register is following UCC fast registers */
1111 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
1112
1113 /* Save the UEC register pointer to UEC private struct */
1114 uec->uec_regs = uec_regs;
1115
1116 /* Init UPSMR, enable hardware statistics (UCC) */
1117 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1118
1119 /* Init MACCFG1, flow control disable, disable Tx and Rx */
1120 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1121
1122 /* Init MACCFG2, length check, MAC PAD and CRC enable */
1123 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1124
1125 /* Setup MAC interface mode */
1126 uec_set_mac_if_mode(uec, uec_info->enet_interface);
1127
da9d4610
AF		 1128 /* Setup MII management base */
1129#ifndef CONFIG_eTSEC_MDIO_BUS
1130 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1131#else
1132 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1133#endif
1134
7737d5c6
DL		 1135 /* Setup MII master clock source */
1136 qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1137
1138 /* Setup UTBIPAR */
1139 utbipar = in_be32(&uec_regs->utbipar);
1140 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1141 enet_interface = uec->uec_info->enet_interface;
1142 if (enet_interface == ENET_1000_TBI ||
1143 enet_interface == ENET_1000_RTBI) {
1144 utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num)
1145 << UTBIPAR_PHY_ADDRESS_SHIFT;
1146 } else {
1147 utbipar |= (0x10 + uec_info->uf_info.ucc_num)
1148 << UTBIPAR_PHY_ADDRESS_SHIFT;
1149 }
1150
1151 out_be32(&uec_regs->utbipar, utbipar);
1152
1153 /* Allocate Tx BDs */
1154 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1155 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1156 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1157 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1158 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1159 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1160 }
1161
1162 align = UEC_TX_BD_RING_ALIGNMENT;
1163 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1164 if (uec->tx_bd_ring_offset != 0) {
1165 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1166 & ~(align - 1));
1167 }
1168
1169 /* Zero all of Tx BDs */
1170 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1171
1172 /* Allocate Rx BDs */
1173 length = uec_info->rx_bd_ring_len * SIZEOFBD;
1174 align = UEC_RX_BD_RING_ALIGNMENT;
1175 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1176 if (uec->rx_bd_ring_offset != 0) {
1177 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1178 & ~(align - 1));
1179 }
1180
1181 /* Zero all of Rx BDs */
1182 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1183
1184 /* Allocate Rx buffer */
1185 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1186 align = UEC_RX_DATA_BUF_ALIGNMENT;
1187 uec->rx_buf_offset = (u32)malloc(length + align);
1188 if (uec->rx_buf_offset != 0) {
1189 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1190 & ~(align - 1));
1191 }
1192
1193 /* Zero all of the Rx buffer */
1194 memset((void *)(uec->rx_buf_offset), 0, length + align);
1195
1196 /* Init TxBD ring */
1197 bd = (qe_bd_t *)uec->p_tx_bd_ring;
1198 uec->txBd = bd;
1199
1200 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1201 BD_DATA_CLEAR(bd);
1202 BD_STATUS_SET(bd, 0);
1203 BD_LENGTH_SET(bd, 0);
1204 bd ++;
1205 }
1206 BD_STATUS_SET((--bd), TxBD_WRAP);
1207
1208 /* Init RxBD ring */
1209 bd = (qe_bd_t *)uec->p_rx_bd_ring;
1210 uec->rxBd = bd;
1211 buf = uec->p_rx_buf;
1212 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1213 BD_DATA_SET(bd, buf);
1214 BD_LENGTH_SET(bd, 0);
1215 BD_STATUS_SET(bd, RxBD_EMPTY);
1216 buf += MAX_RXBUF_LEN;
1217 bd ++;
1218 }
1219 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1220
1221 /* Init global Tx parameter RAM */
1222 uec_init_tx_parameter(uec, num_threads_tx);
1223
1224 /* Init global Rx parameter RAM */
1225 uec_init_rx_parameter(uec, num_threads_rx);
1226
1227 /* Init ethernet Tx and Rx parameter command */
1228 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1229 num_threads_rx)) {
1230 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1231 return -ENOMEM;
1232 }
1233
1234 return 0;
1235}
1236
1237static int uec_init(struct eth_device* dev, bd_t *bd)
1238{
1239 uec_private_t *uec;
ee62ed32
KP		 1240 int err, i;
1241 struct phy_info *curphy;
7737d5c6
DL		 1242
1243 uec = (uec_private_t *)dev->priv;
1244
1245 if (uec->the_first_run == 0) {
ee62ed32
KP		 1246 err = init_phy(dev);
1247 if (err) {
1248 printf("%s: Cannot initialize PHY, aborting.\n",
1249 dev->name);
1250 return err;
7737d5c6 1251 }
ee62ed32
KP		 1252
1253 curphy = uec->mii_info->phyinfo;
1254
1255 if (curphy->config_aneg) {
1256 err = curphy->config_aneg(uec->mii_info);
1257 if (err) {
1258 printf("%s: Can't negotiate PHY\n", dev->name);
1259 return err;
1260 }
1261 }
1262
1263 /* Give PHYs up to 5 sec to report a link */
1264 i = 50;
1265 do {
1266 err = curphy->read_status(uec->mii_info);
1267 udelay(100000);
1268 } while (((i-- > 0) && !uec->mii_info->link) || err);
1269
1270 if (err || i <= 0)
1271 printf("warning: %s: timeout on PHY link\n", dev->name);
1272
7737d5c6
DL		 1273 uec->the_first_run = 1;
1274 }
1275
ee62ed32
KP		 1276 /* Set up the MAC address */
1277 if (dev->enetaddr[0] & 0x01) {
1278 printf("%s: MacAddress is multcast address\n",
1279 __FUNCTION__);
1280 return -1;
1281 }
1282 uec_set_mac_address(uec, dev->enetaddr);
1283
1284
7737d5c6
DL		 1285 err = uec_open(uec, COMM_DIR_RX_AND_TX);
1286 if (err) {
1287 printf("%s: cannot enable UEC device\n", dev->name);
422b1a01 1288 return -1;
7737d5c6
DL		 1289 }
1290
ee62ed32
KP		 1291 phy_change(dev);
1292
422b1a01 1293 return (uec->mii_info->link ? 0 : -1);
7737d5c6
DL		 1294}
1295
1296static void uec_halt(struct eth_device* dev)
1297{
1298 uec_private_t *uec = (uec_private_t *)dev->priv;
1299 uec_stop(uec, COMM_DIR_RX_AND_TX);
1300}
1301
1302static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1303{
1304 uec_private_t *uec;
1305 ucc_fast_private_t *uccf;
1306 volatile qe_bd_t *bd;
ddd02492 1307 u16 status;
7737d5c6
DL		 1308 int i;
1309 int result = 0;
1310
1311 uec = (uec_private_t *)dev->priv;
1312 uccf = uec->uccf;
1313 bd = uec->txBd;
1314
1315 /* Find an empty TxBD */
ddd02492 1316 for (i = 0; bd->status & TxBD_READY; i++) {
7737d5c6
DL		 1317 if (i > 0x100000) {
1318 printf("%s: tx buffer not ready\n", dev->name);
1319 return result;
1320 }
1321 }
1322
1323 /* Init TxBD */
1324 BD_DATA_SET(bd, buf);
1325 BD_LENGTH_SET(bd, len);
a28899c9 1326 status = bd->status;
7737d5c6
DL		 1327 status &= BD_WRAP;
1328 status |= (TxBD_READY | TxBD_LAST);
1329 BD_STATUS_SET(bd, status);
1330
1331 /* Tell UCC to transmit the buffer */
1332 ucc_fast_transmit_on_demand(uccf);
1333
1334 /* Wait for buffer to be transmitted */
ddd02492 1335 for (i = 0; bd->status & TxBD_READY; i++) {
7737d5c6
DL		 1336 if (i > 0x100000) {
1337 printf("%s: tx error\n", dev->name);
1338 return result;
1339 }
7737d5c6
DL		 1340 }
1341
1342 /* Ok, the buffer be transimitted */
1343 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1344 uec->txBd = bd;
1345 result = 1;
1346
1347 return result;
1348}
1349
1350static int uec_recv(struct eth_device* dev)
1351{
1352 uec_private_t *uec = dev->priv;
1353 volatile qe_bd_t *bd;
ddd02492 1354 u16 status;
7737d5c6
DL		 1355 u16 len;
1356 u8 *data;
1357
1358 bd = uec->rxBd;
ddd02492 1359 status = bd->status;
7737d5c6
DL		 1360
1361 while (!(status & RxBD_EMPTY)) {
1362 if (!(status & RxBD_ERROR)) {
1363 data = BD_DATA(bd);
1364 len = BD_LENGTH(bd);
1365 NetReceive(data, len);
1366 } else {
1367 printf("%s: Rx error\n", dev->name);
1368 }
1369 status &= BD_CLEAN;
1370 BD_LENGTH_SET(bd, 0);
1371 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1372 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
ddd02492 1373 status = bd->status;
7737d5c6
DL		 1374 }
1375 uec->rxBd = bd;
1376
1377 return 1;
1378}
1379
1380int uec_initialize(int index)
1381{
1382 struct eth_device *dev;
1383 int i;
1384 uec_private_t *uec;
1385 uec_info_t *uec_info;
1386 int err;
1387
1388 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1389 if (!dev)
1390 return 0;
1391 memset(dev, 0, sizeof(struct eth_device));
1392
1393 /* Allocate the UEC private struct */
1394 uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1395 if (!uec) {
1396 return -ENOMEM;
1397 }
1398 memset(uec, 0, sizeof(uec_private_t));
1399
1400 /* Init UEC private struct, they come from board.h */
06c428bc 1401 uec_info = NULL;
7737d5c6
DL		 1402 if (index == 0) {
1403#ifdef CONFIG_UEC_ETH1
1404 uec_info = &eth1_uec_info;
1405#endif
1406 } else if (index == 1) {
1407#ifdef CONFIG_UEC_ETH2
1408 uec_info = &eth2_uec_info;
ccf21c31
JT		 1409#endif
1410 } else if (index == 2) {
1411#ifdef CONFIG_UEC_ETH3
1412 uec_info = &eth3_uec_info;
2465665b
DS		 1413#endif
1414 } else if (index == 3) {
1415#ifdef CONFIG_UEC_ETH4
1416 uec_info = &eth4_uec_info;
7737d5c6
DL		 1417#endif
1418 } else {
1419 printf("%s: index is illegal.\n", __FUNCTION__);
1420 return -EINVAL;
1421 }
1422
d5d28fe4
DS		 1423 devlist[index] = dev;
1424
7737d5c6
DL		 1425 uec->uec_info = uec_info;
1426
1427 sprintf(dev->name, "FSL UEC%d", index);
1428 dev->iobase = 0;
1429 dev->priv = (void *)uec;
1430 dev->init = uec_init;
1431 dev->halt = uec_halt;
1432 dev->send = uec_send;
1433 dev->recv = uec_recv;
1434
1435 /* Clear the ethnet address */
1436 for (i = 0; i < 6; i++)
1437 dev->enetaddr[i] = 0;
1438
1439 eth_register(dev);
1440
1441 err = uec_startup(uec);
1442 if (err) {
1443 printf("%s: Cannot configure net device, aborting.",dev->name);
1444 return err;
1445 }
1446
d5d28fe4
DS		 1447#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1448 && !defined(BITBANGMII)
1449 miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
1450#endif
1451
7737d5c6
DL		 1452 return 1;
1453}
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