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6e9e0626 OT |
1 | /* |
2 | * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org> | |
3 | * Copyright (C) 2014 Marek Vasut <marex@denx.de> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
f58a41e0 | 9 | #include <dm.h> |
6e9e0626 OT |
10 | #include <errno.h> |
11 | #include <usb.h> | |
12 | #include <malloc.h> | |
cf92e05c | 13 | #include <memalign.h> |
5c0beb5c | 14 | #include <phys2bus.h> |
6e9e0626 | 15 | #include <usbroothubdes.h> |
fd2cd662 | 16 | #include <wait_bit.h> |
6e9e0626 OT |
17 | #include <asm/io.h> |
18 | ||
19 | #include "dwc2.h" | |
20 | ||
b4fbd089 MV |
21 | DECLARE_GLOBAL_DATA_PTR; |
22 | ||
6e9e0626 OT |
23 | /* Use only HC channel 0. */ |
24 | #define DWC2_HC_CHANNEL 0 | |
25 | ||
26 | #define DWC2_STATUS_BUF_SIZE 64 | |
27 | #define DWC2_DATA_BUF_SIZE (64 * 1024) | |
28 | ||
6e9e0626 OT |
29 | #define MAX_DEVICE 16 |
30 | #define MAX_ENDPOINT 16 | |
6e9e0626 | 31 | |
cc3e3a9e | 32 | struct dwc2_priv { |
f58a41e0 | 33 | #ifdef CONFIG_DM_USB |
db402e00 AS |
34 | uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); |
35 | uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); | |
f58a41e0 | 36 | #else |
cc3e3a9e SG |
37 | uint8_t *aligned_buffer; |
38 | uint8_t *status_buffer; | |
f58a41e0 | 39 | #endif |
25612f23 SB |
40 | u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; |
41 | u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT]; | |
cc3e3a9e SG |
42 | struct dwc2_core_regs *regs; |
43 | int root_hub_devnum; | |
618da563 | 44 | bool ext_vbus; |
b4fbd089 | 45 | bool oc_disable; |
cc3e3a9e | 46 | }; |
6e9e0626 | 47 | |
f58a41e0 | 48 | #ifndef CONFIG_DM_USB |
db402e00 AS |
49 | /* We need cacheline-aligned buffers for DMA transfers and dcache support */ |
50 | DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE, | |
51 | ARCH_DMA_MINALIGN); | |
52 | DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE, | |
53 | ARCH_DMA_MINALIGN); | |
cc3e3a9e SG |
54 | |
55 | static struct dwc2_priv local; | |
f58a41e0 | 56 | #endif |
6e9e0626 OT |
57 | |
58 | /* | |
59 | * DWC2 IP interface | |
60 | */ | |
6e9e0626 OT |
61 | |
62 | /* | |
63 | * Initializes the FSLSPClkSel field of the HCFG register | |
64 | * depending on the PHY type. | |
65 | */ | |
66 | static void init_fslspclksel(struct dwc2_core_regs *regs) | |
67 | { | |
68 | uint32_t phyclk; | |
69 | ||
70 | #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) | |
71 | phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ | |
72 | #else | |
73 | /* High speed PHY running at full speed or high speed */ | |
74 | phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; | |
75 | #endif | |
76 | ||
77 | #ifdef CONFIG_DWC2_ULPI_FS_LS | |
78 | uint32_t hwcfg2 = readl(®s->ghwcfg2); | |
79 | uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> | |
80 | DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; | |
81 | uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> | |
82 | DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; | |
83 | ||
84 | if (hval == 2 && fval == 1) | |
85 | phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ | |
86 | #endif | |
87 | ||
88 | clrsetbits_le32(®s->host_regs.hcfg, | |
89 | DWC2_HCFG_FSLSPCLKSEL_MASK, | |
90 | phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET); | |
91 | } | |
92 | ||
93 | /* | |
94 | * Flush a Tx FIFO. | |
95 | * | |
96 | * @param regs Programming view of DWC_otg controller. | |
97 | * @param num Tx FIFO to flush. | |
98 | */ | |
99 | static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num) | |
100 | { | |
101 | int ret; | |
102 | ||
103 | writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET), | |
104 | ®s->grstctl); | |
fd2cd662 MK |
105 | ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_TXFFLSH, |
106 | false, 1000, false); | |
6e9e0626 OT |
107 | if (ret) |
108 | printf("%s: Timeout!\n", __func__); | |
109 | ||
110 | /* Wait for 3 PHY Clocks */ | |
111 | udelay(1); | |
112 | } | |
113 | ||
114 | /* | |
115 | * Flush Rx FIFO. | |
116 | * | |
117 | * @param regs Programming view of DWC_otg controller. | |
118 | */ | |
119 | static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs) | |
120 | { | |
121 | int ret; | |
122 | ||
123 | writel(DWC2_GRSTCTL_RXFFLSH, ®s->grstctl); | |
fd2cd662 MK |
124 | ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_RXFFLSH, |
125 | false, 1000, false); | |
6e9e0626 OT |
126 | if (ret) |
127 | printf("%s: Timeout!\n", __func__); | |
128 | ||
129 | /* Wait for 3 PHY Clocks */ | |
130 | udelay(1); | |
131 | } | |
132 | ||
133 | /* | |
134 | * Do core a soft reset of the core. Be careful with this because it | |
135 | * resets all the internal state machines of the core. | |
136 | */ | |
137 | static void dwc_otg_core_reset(struct dwc2_core_regs *regs) | |
138 | { | |
139 | int ret; | |
140 | ||
141 | /* Wait for AHB master IDLE state. */ | |
fd2cd662 MK |
142 | ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_AHBIDLE, |
143 | true, 1000, false); | |
6e9e0626 OT |
144 | if (ret) |
145 | printf("%s: Timeout!\n", __func__); | |
146 | ||
147 | /* Core Soft Reset */ | |
148 | writel(DWC2_GRSTCTL_CSFTRST, ®s->grstctl); | |
fd2cd662 MK |
149 | ret = wait_for_bit(__func__, ®s->grstctl, DWC2_GRSTCTL_CSFTRST, |
150 | false, 1000, false); | |
6e9e0626 OT |
151 | if (ret) |
152 | printf("%s: Timeout!\n", __func__); | |
153 | ||
154 | /* | |
155 | * Wait for core to come out of reset. | |
156 | * NOTE: This long sleep is _very_ important, otherwise the core will | |
157 | * not stay in host mode after a connector ID change! | |
158 | */ | |
159 | mdelay(100); | |
160 | } | |
161 | ||
162 | /* | |
163 | * This function initializes the DWC_otg controller registers for | |
164 | * host mode. | |
165 | * | |
166 | * This function flushes the Tx and Rx FIFOs and it flushes any entries in the | |
167 | * request queues. Host channels are reset to ensure that they are ready for | |
168 | * performing transfers. | |
169 | * | |
170 | * @param regs Programming view of DWC_otg controller | |
171 | * | |
172 | */ | |
173 | static void dwc_otg_core_host_init(struct dwc2_core_regs *regs) | |
174 | { | |
175 | uint32_t nptxfifosize = 0; | |
176 | uint32_t ptxfifosize = 0; | |
177 | uint32_t hprt0 = 0; | |
178 | int i, ret, num_channels; | |
179 | ||
180 | /* Restart the Phy Clock */ | |
181 | writel(0, ®s->pcgcctl); | |
182 | ||
183 | /* Initialize Host Configuration Register */ | |
184 | init_fslspclksel(regs); | |
185 | #ifdef CONFIG_DWC2_DFLT_SPEED_FULL | |
186 | setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); | |
187 | #endif | |
188 | ||
189 | /* Configure data FIFO sizes */ | |
190 | #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO | |
191 | if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { | |
192 | /* Rx FIFO */ | |
193 | writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); | |
194 | ||
195 | /* Non-periodic Tx FIFO */ | |
196 | nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << | |
197 | DWC2_FIFOSIZE_DEPTH_OFFSET; | |
198 | nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << | |
199 | DWC2_FIFOSIZE_STARTADDR_OFFSET; | |
200 | writel(nptxfifosize, ®s->gnptxfsiz); | |
201 | ||
202 | /* Periodic Tx FIFO */ | |
203 | ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << | |
204 | DWC2_FIFOSIZE_DEPTH_OFFSET; | |
205 | ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + | |
206 | CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << | |
207 | DWC2_FIFOSIZE_STARTADDR_OFFSET; | |
208 | writel(ptxfifosize, ®s->hptxfsiz); | |
209 | } | |
210 | #endif | |
211 | ||
212 | /* Clear Host Set HNP Enable in the OTG Control Register */ | |
213 | clrbits_le32(®s->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN); | |
214 | ||
215 | /* Make sure the FIFOs are flushed. */ | |
216 | dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */ | |
217 | dwc_otg_flush_rx_fifo(regs); | |
218 | ||
219 | /* Flush out any leftover queued requests. */ | |
220 | num_channels = readl(®s->ghwcfg2); | |
221 | num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK; | |
222 | num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET; | |
223 | num_channels += 1; | |
224 | ||
225 | for (i = 0; i < num_channels; i++) | |
226 | clrsetbits_le32(®s->hc_regs[i].hcchar, | |
227 | DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR, | |
228 | DWC2_HCCHAR_CHDIS); | |
229 | ||
230 | /* Halt all channels to put them into a known state. */ | |
231 | for (i = 0; i < num_channels; i++) { | |
232 | clrsetbits_le32(®s->hc_regs[i].hcchar, | |
233 | DWC2_HCCHAR_EPDIR, | |
234 | DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS); | |
fd2cd662 MK |
235 | ret = wait_for_bit(__func__, ®s->hc_regs[i].hcchar, |
236 | DWC2_HCCHAR_CHEN, false, 1000, false); | |
6e9e0626 OT |
237 | if (ret) |
238 | printf("%s: Timeout!\n", __func__); | |
239 | } | |
240 | ||
241 | /* Turn on the vbus power. */ | |
242 | if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) { | |
243 | hprt0 = readl(®s->hprt0); | |
244 | hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET); | |
245 | hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG); | |
246 | if (!(hprt0 & DWC2_HPRT0_PRTPWR)) { | |
247 | hprt0 |= DWC2_HPRT0_PRTPWR; | |
248 | writel(hprt0, ®s->hprt0); | |
249 | } | |
250 | } | |
251 | } | |
252 | ||
253 | /* | |
254 | * This function initializes the DWC_otg controller registers and | |
255 | * prepares the core for device mode or host mode operation. | |
256 | * | |
257 | * @param regs Programming view of the DWC_otg controller | |
258 | */ | |
55901989 | 259 | static void dwc_otg_core_init(struct dwc2_priv *priv) |
6e9e0626 | 260 | { |
55901989 | 261 | struct dwc2_core_regs *regs = priv->regs; |
6e9e0626 OT |
262 | uint32_t ahbcfg = 0; |
263 | uint32_t usbcfg = 0; | |
264 | uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; | |
265 | ||
266 | /* Common Initialization */ | |
267 | usbcfg = readl(®s->gusbcfg); | |
268 | ||
269 | /* Program the ULPI External VBUS bit if needed */ | |
618da563 | 270 | if (priv->ext_vbus) { |
b4fbd089 MV |
271 | usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; |
272 | if (!priv->oc_disable) { | |
273 | usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR | | |
274 | DWC2_GUSBCFG_INDICATOR_PASSTHROUGH; | |
275 | } | |
618da563 MV |
276 | } else { |
277 | usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV; | |
278 | } | |
6e9e0626 OT |
279 | |
280 | /* Set external TS Dline pulsing */ | |
281 | #ifdef CONFIG_DWC2_TS_DLINE | |
282 | usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; | |
283 | #else | |
284 | usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; | |
285 | #endif | |
286 | writel(usbcfg, ®s->gusbcfg); | |
287 | ||
288 | /* Reset the Controller */ | |
289 | dwc_otg_core_reset(regs); | |
290 | ||
291 | /* | |
292 | * This programming sequence needs to happen in FS mode before | |
293 | * any other programming occurs | |
294 | */ | |
295 | #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ | |
296 | (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) | |
297 | /* If FS mode with FS PHY */ | |
298 | setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); | |
299 | ||
300 | /* Reset after a PHY select */ | |
301 | dwc_otg_core_reset(regs); | |
302 | ||
303 | /* | |
304 | * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. | |
305 | * Also do this on HNP Dev/Host mode switches (done in dev_init | |
306 | * and host_init). | |
307 | */ | |
308 | if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) | |
309 | init_fslspclksel(regs); | |
310 | ||
311 | #ifdef CONFIG_DWC2_I2C_ENABLE | |
312 | /* Program GUSBCFG.OtgUtmifsSel to I2C */ | |
313 | setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); | |
314 | ||
315 | /* Program GI2CCTL.I2CEn */ | |
316 | clrsetbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN | | |
317 | DWC2_GI2CCTL_I2CDEVADDR_MASK, | |
318 | 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET); | |
319 | setbits_le32(®s->gi2cctl, DWC2_GI2CCTL_I2CEN); | |
320 | #endif | |
321 | ||
322 | #else | |
323 | /* High speed PHY. */ | |
324 | ||
325 | /* | |
326 | * HS PHY parameters. These parameters are preserved during | |
327 | * soft reset so only program the first time. Do a soft reset | |
328 | * immediately after setting phyif. | |
329 | */ | |
330 | usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); | |
331 | usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; | |
332 | ||
333 | if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ | |
334 | #ifdef CONFIG_DWC2_PHY_ULPI_DDR | |
335 | usbcfg |= DWC2_GUSBCFG_DDRSEL; | |
336 | #else | |
337 | usbcfg &= ~DWC2_GUSBCFG_DDRSEL; | |
338 | #endif | |
339 | } else { /* UTMI+ interface */ | |
340 | #if (CONFIG_DWC2_UTMI_PHY_WIDTH == 16) | |
341 | usbcfg |= DWC2_GUSBCFG_PHYIF; | |
342 | #endif | |
343 | } | |
344 | ||
345 | writel(usbcfg, ®s->gusbcfg); | |
346 | ||
347 | /* Reset after setting the PHY parameters */ | |
348 | dwc_otg_core_reset(regs); | |
349 | #endif | |
350 | ||
351 | usbcfg = readl(®s->gusbcfg); | |
352 | usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); | |
353 | #ifdef CONFIG_DWC2_ULPI_FS_LS | |
354 | uint32_t hwcfg2 = readl(®s->ghwcfg2); | |
355 | uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> | |
356 | DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; | |
357 | uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >> | |
358 | DWC2_HWCFG2_FS_PHY_TYPE_OFFSET; | |
359 | if (hval == 2 && fval == 1) { | |
360 | usbcfg |= DWC2_GUSBCFG_ULPI_FSLS; | |
361 | usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M; | |
362 | } | |
363 | #endif | |
364 | writel(usbcfg, ®s->gusbcfg); | |
365 | ||
366 | /* Program the GAHBCFG Register. */ | |
367 | switch (readl(®s->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) { | |
368 | case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY: | |
369 | break; | |
370 | case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA: | |
371 | while (brst_sz > 1) { | |
372 | ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET); | |
373 | ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK; | |
374 | brst_sz >>= 1; | |
375 | } | |
376 | ||
377 | #ifdef CONFIG_DWC2_DMA_ENABLE | |
378 | ahbcfg |= DWC2_GAHBCFG_DMAENABLE; | |
379 | #endif | |
380 | break; | |
381 | ||
382 | case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: | |
383 | ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; | |
384 | #ifdef CONFIG_DWC2_DMA_ENABLE | |
385 | ahbcfg |= DWC2_GAHBCFG_DMAENABLE; | |
386 | #endif | |
387 | break; | |
388 | } | |
389 | ||
390 | writel(ahbcfg, ®s->gahbcfg); | |
391 | ||
392 | /* Program the GUSBCFG register for HNP/SRP. */ | |
393 | setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP); | |
394 | ||
395 | #ifdef CONFIG_DWC2_IC_USB_CAP | |
396 | setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_IC_USB_CAP); | |
397 | #endif | |
398 | } | |
399 | ||
400 | /* | |
401 | * Prepares a host channel for transferring packets to/from a specific | |
402 | * endpoint. The HCCHARn register is set up with the characteristics specified | |
403 | * in _hc. Host channel interrupts that may need to be serviced while this | |
404 | * transfer is in progress are enabled. | |
405 | * | |
406 | * @param regs Programming view of DWC_otg controller | |
407 | * @param hc Information needed to initialize the host channel | |
408 | */ | |
409 | static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num, | |
ed9bcbc7 SW |
410 | struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num, |
411 | uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet) | |
6e9e0626 OT |
412 | { |
413 | struct dwc2_hc_regs *hc_regs = ®s->hc_regs[hc_num]; | |
ed9bcbc7 SW |
414 | uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) | |
415 | (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) | | |
416 | (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) | | |
417 | (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) | | |
418 | (max_packet << DWC2_HCCHAR_MPS_OFFSET); | |
419 | ||
420 | if (dev->speed == USB_SPEED_LOW) | |
421 | hcchar |= DWC2_HCCHAR_LSPDDEV; | |
6e9e0626 | 422 | |
6e9e0626 OT |
423 | /* |
424 | * Program the HCCHARn register with the endpoint characteristics | |
425 | * for the current transfer. | |
426 | */ | |
427 | writel(hcchar, &hc_regs->hcchar); | |
428 | ||
890f0ee4 | 429 | /* Program the HCSPLIT register, default to no SPLIT */ |
6e9e0626 OT |
430 | writel(0, &hc_regs->hcsplt); |
431 | } | |
432 | ||
890f0ee4 SB |
433 | static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs, |
434 | uint8_t hub_devnum, uint8_t hub_port) | |
435 | { | |
436 | uint32_t hcsplt = 0; | |
437 | ||
438 | hcsplt = DWC2_HCSPLT_SPLTENA; | |
439 | hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET; | |
440 | hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET; | |
441 | ||
442 | /* Program the HCSPLIT register for SPLITs */ | |
443 | writel(hcsplt, &hc_regs->hcsplt); | |
444 | } | |
445 | ||
6e9e0626 OT |
446 | /* |
447 | * DWC2 to USB API interface | |
448 | */ | |
449 | /* Direction: In ; Request: Status */ | |
cc3e3a9e SG |
450 | static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs, |
451 | struct usb_device *dev, void *buffer, | |
6e9e0626 OT |
452 | int txlen, struct devrequest *cmd) |
453 | { | |
454 | uint32_t hprt0 = 0; | |
455 | uint32_t port_status = 0; | |
456 | uint32_t port_change = 0; | |
457 | int len = 0; | |
458 | int stat = 0; | |
459 | ||
460 | switch (cmd->requesttype & ~USB_DIR_IN) { | |
461 | case 0: | |
462 | *(uint16_t *)buffer = cpu_to_le16(1); | |
463 | len = 2; | |
464 | break; | |
465 | case USB_RECIP_INTERFACE: | |
466 | case USB_RECIP_ENDPOINT: | |
467 | *(uint16_t *)buffer = cpu_to_le16(0); | |
468 | len = 2; | |
469 | break; | |
470 | case USB_TYPE_CLASS: | |
471 | *(uint32_t *)buffer = cpu_to_le32(0); | |
472 | len = 4; | |
473 | break; | |
474 | case USB_RECIP_OTHER | USB_TYPE_CLASS: | |
475 | hprt0 = readl(®s->hprt0); | |
476 | if (hprt0 & DWC2_HPRT0_PRTCONNSTS) | |
477 | port_status |= USB_PORT_STAT_CONNECTION; | |
478 | if (hprt0 & DWC2_HPRT0_PRTENA) | |
479 | port_status |= USB_PORT_STAT_ENABLE; | |
480 | if (hprt0 & DWC2_HPRT0_PRTSUSP) | |
481 | port_status |= USB_PORT_STAT_SUSPEND; | |
482 | if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT) | |
483 | port_status |= USB_PORT_STAT_OVERCURRENT; | |
484 | if (hprt0 & DWC2_HPRT0_PRTRST) | |
485 | port_status |= USB_PORT_STAT_RESET; | |
486 | if (hprt0 & DWC2_HPRT0_PRTPWR) | |
487 | port_status |= USB_PORT_STAT_POWER; | |
488 | ||
4748cce5 SW |
489 | if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW) |
490 | port_status |= USB_PORT_STAT_LOW_SPEED; | |
491 | else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == | |
492 | DWC2_HPRT0_PRTSPD_HIGH) | |
493 | port_status |= USB_PORT_STAT_HIGH_SPEED; | |
6e9e0626 OT |
494 | |
495 | if (hprt0 & DWC2_HPRT0_PRTENCHNG) | |
496 | port_change |= USB_PORT_STAT_C_ENABLE; | |
497 | if (hprt0 & DWC2_HPRT0_PRTCONNDET) | |
498 | port_change |= USB_PORT_STAT_C_CONNECTION; | |
499 | if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG) | |
500 | port_change |= USB_PORT_STAT_C_OVERCURRENT; | |
501 | ||
502 | *(uint32_t *)buffer = cpu_to_le32(port_status | | |
503 | (port_change << 16)); | |
504 | len = 4; | |
505 | break; | |
506 | default: | |
507 | puts("unsupported root hub command\n"); | |
508 | stat = USB_ST_STALLED; | |
509 | } | |
510 | ||
511 | dev->act_len = min(len, txlen); | |
512 | dev->status = stat; | |
513 | ||
514 | return stat; | |
515 | } | |
516 | ||
517 | /* Direction: In ; Request: Descriptor */ | |
518 | static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev, | |
519 | void *buffer, int txlen, | |
520 | struct devrequest *cmd) | |
521 | { | |
522 | unsigned char data[32]; | |
523 | uint32_t dsc; | |
524 | int len = 0; | |
525 | int stat = 0; | |
526 | uint16_t wValue = cpu_to_le16(cmd->value); | |
527 | uint16_t wLength = cpu_to_le16(cmd->length); | |
528 | ||
529 | switch (cmd->requesttype & ~USB_DIR_IN) { | |
530 | case 0: | |
531 | switch (wValue & 0xff00) { | |
532 | case 0x0100: /* device descriptor */ | |
b4141195 | 533 | len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength); |
6e9e0626 OT |
534 | memcpy(buffer, root_hub_dev_des, len); |
535 | break; | |
536 | case 0x0200: /* configuration descriptor */ | |
b4141195 | 537 | len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength); |
6e9e0626 OT |
538 | memcpy(buffer, root_hub_config_des, len); |
539 | break; | |
540 | case 0x0300: /* string descriptors */ | |
541 | switch (wValue & 0xff) { | |
542 | case 0x00: | |
b4141195 MY |
543 | len = min3(txlen, (int)sizeof(root_hub_str_index0), |
544 | (int)wLength); | |
6e9e0626 OT |
545 | memcpy(buffer, root_hub_str_index0, len); |
546 | break; | |
547 | case 0x01: | |
b4141195 MY |
548 | len = min3(txlen, (int)sizeof(root_hub_str_index1), |
549 | (int)wLength); | |
6e9e0626 OT |
550 | memcpy(buffer, root_hub_str_index1, len); |
551 | break; | |
552 | } | |
553 | break; | |
554 | default: | |
555 | stat = USB_ST_STALLED; | |
556 | } | |
557 | break; | |
558 | ||
559 | case USB_TYPE_CLASS: | |
560 | /* Root port config, set 1 port and nothing else. */ | |
561 | dsc = 0x00000001; | |
562 | ||
563 | data[0] = 9; /* min length; */ | |
564 | data[1] = 0x29; | |
565 | data[2] = dsc & RH_A_NDP; | |
566 | data[3] = 0; | |
567 | if (dsc & RH_A_PSM) | |
568 | data[3] |= 0x1; | |
569 | if (dsc & RH_A_NOCP) | |
570 | data[3] |= 0x10; | |
571 | else if (dsc & RH_A_OCPM) | |
572 | data[3] |= 0x8; | |
573 | ||
574 | /* corresponds to data[4-7] */ | |
575 | data[5] = (dsc & RH_A_POTPGT) >> 24; | |
576 | data[7] = dsc & RH_B_DR; | |
577 | if (data[2] < 7) { | |
578 | data[8] = 0xff; | |
579 | } else { | |
580 | data[0] += 2; | |
581 | data[8] = (dsc & RH_B_DR) >> 8; | |
582 | data[9] = 0xff; | |
583 | data[10] = data[9]; | |
584 | } | |
585 | ||
b4141195 | 586 | len = min3(txlen, (int)data[0], (int)wLength); |
6e9e0626 OT |
587 | memcpy(buffer, data, len); |
588 | break; | |
589 | default: | |
590 | puts("unsupported root hub command\n"); | |
591 | stat = USB_ST_STALLED; | |
592 | } | |
593 | ||
594 | dev->act_len = min(len, txlen); | |
595 | dev->status = stat; | |
596 | ||
597 | return stat; | |
598 | } | |
599 | ||
600 | /* Direction: In ; Request: Configuration */ | |
601 | static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev, | |
602 | void *buffer, int txlen, | |
603 | struct devrequest *cmd) | |
604 | { | |
605 | int len = 0; | |
606 | int stat = 0; | |
607 | ||
608 | switch (cmd->requesttype & ~USB_DIR_IN) { | |
609 | case 0: | |
610 | *(uint8_t *)buffer = 0x01; | |
611 | len = 1; | |
612 | break; | |
613 | default: | |
614 | puts("unsupported root hub command\n"); | |
615 | stat = USB_ST_STALLED; | |
616 | } | |
617 | ||
618 | dev->act_len = min(len, txlen); | |
619 | dev->status = stat; | |
620 | ||
621 | return stat; | |
622 | } | |
623 | ||
624 | /* Direction: In */ | |
cc3e3a9e SG |
625 | static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv, |
626 | struct usb_device *dev, void *buffer, | |
627 | int txlen, struct devrequest *cmd) | |
6e9e0626 OT |
628 | { |
629 | switch (cmd->request) { | |
630 | case USB_REQ_GET_STATUS: | |
cc3e3a9e | 631 | return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer, |
6e9e0626 OT |
632 | txlen, cmd); |
633 | case USB_REQ_GET_DESCRIPTOR: | |
634 | return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer, | |
635 | txlen, cmd); | |
636 | case USB_REQ_GET_CONFIGURATION: | |
637 | return dwc_otg_submit_rh_msg_in_configuration(dev, buffer, | |
638 | txlen, cmd); | |
639 | default: | |
640 | puts("unsupported root hub command\n"); | |
641 | return USB_ST_STALLED; | |
642 | } | |
643 | } | |
644 | ||
645 | /* Direction: Out */ | |
cc3e3a9e SG |
646 | static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv, |
647 | struct usb_device *dev, | |
648 | void *buffer, int txlen, | |
649 | struct devrequest *cmd) | |
6e9e0626 | 650 | { |
cc3e3a9e | 651 | struct dwc2_core_regs *regs = priv->regs; |
6e9e0626 OT |
652 | int len = 0; |
653 | int stat = 0; | |
654 | uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8); | |
655 | uint16_t wValue = cpu_to_le16(cmd->value); | |
656 | ||
657 | switch (bmrtype_breq & ~USB_DIR_IN) { | |
658 | case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT: | |
659 | case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS: | |
660 | break; | |
661 | ||
662 | case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: | |
663 | switch (wValue) { | |
664 | case USB_PORT_FEAT_C_CONNECTION: | |
665 | setbits_le32(®s->hprt0, DWC2_HPRT0_PRTCONNDET); | |
666 | break; | |
667 | } | |
668 | break; | |
669 | ||
670 | case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS: | |
671 | switch (wValue) { | |
672 | case USB_PORT_FEAT_SUSPEND: | |
673 | break; | |
674 | ||
675 | case USB_PORT_FEAT_RESET: | |
676 | clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | | |
677 | DWC2_HPRT0_PRTCONNDET | | |
678 | DWC2_HPRT0_PRTENCHNG | | |
679 | DWC2_HPRT0_PRTOVRCURRCHNG, | |
680 | DWC2_HPRT0_PRTRST); | |
681 | mdelay(50); | |
682 | clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTRST); | |
683 | break; | |
684 | ||
685 | case USB_PORT_FEAT_POWER: | |
686 | clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | | |
687 | DWC2_HPRT0_PRTCONNDET | | |
688 | DWC2_HPRT0_PRTENCHNG | | |
689 | DWC2_HPRT0_PRTOVRCURRCHNG, | |
690 | DWC2_HPRT0_PRTRST); | |
691 | break; | |
692 | ||
693 | case USB_PORT_FEAT_ENABLE: | |
694 | break; | |
695 | } | |
696 | break; | |
697 | case (USB_REQ_SET_ADDRESS << 8): | |
cc3e3a9e | 698 | priv->root_hub_devnum = wValue; |
6e9e0626 OT |
699 | break; |
700 | case (USB_REQ_SET_CONFIGURATION << 8): | |
701 | break; | |
702 | default: | |
703 | puts("unsupported root hub command\n"); | |
704 | stat = USB_ST_STALLED; | |
705 | } | |
706 | ||
707 | len = min(len, txlen); | |
708 | ||
709 | dev->act_len = len; | |
710 | dev->status = stat; | |
711 | ||
712 | return stat; | |
713 | } | |
714 | ||
cc3e3a9e SG |
715 | static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev, |
716 | unsigned long pipe, void *buffer, int txlen, | |
6e9e0626 OT |
717 | struct devrequest *cmd) |
718 | { | |
719 | int stat = 0; | |
720 | ||
721 | if (usb_pipeint(pipe)) { | |
722 | puts("Root-Hub submit IRQ: NOT implemented\n"); | |
723 | return 0; | |
724 | } | |
725 | ||
726 | if (cmd->requesttype & USB_DIR_IN) | |
cc3e3a9e | 727 | stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd); |
6e9e0626 | 728 | else |
cc3e3a9e | 729 | stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd); |
6e9e0626 OT |
730 | |
731 | mdelay(1); | |
732 | ||
733 | return stat; | |
734 | } | |
735 | ||
25612f23 | 736 | int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle) |
4a1d21fc | 737 | { |
4a1d21fc SW |
738 | int ret; |
739 | uint32_t hcint, hctsiz; | |
740 | ||
fd2cd662 MK |
741 | ret = wait_for_bit(__func__, &hc_regs->hcint, DWC2_HCINT_CHHLTD, true, |
742 | 1000, false); | |
4a1d21fc SW |
743 | if (ret) |
744 | return ret; | |
745 | ||
746 | hcint = readl(&hc_regs->hcint); | |
4a1d21fc SW |
747 | hctsiz = readl(&hc_regs->hctsiz); |
748 | *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >> | |
749 | DWC2_HCTSIZ_XFERSIZE_OFFSET; | |
66ffc875 | 750 | *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET; |
4a1d21fc | 751 | |
03460cdc SB |
752 | debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub, |
753 | *toggle); | |
4a1d21fc | 754 | |
03460cdc SB |
755 | if (hcint & DWC2_HCINT_XFERCOMP) |
756 | return 0; | |
757 | ||
758 | if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN)) | |
759 | return -EAGAIN; | |
760 | ||
761 | debug("%s: Error (HCINT=%08x)\n", __func__, hcint); | |
762 | return -EINVAL; | |
4a1d21fc SW |
763 | } |
764 | ||
7b5e504d SW |
765 | static int dwc2_eptype[] = { |
766 | DWC2_HCCHAR_EPTYPE_ISOC, | |
767 | DWC2_HCCHAR_EPTYPE_INTR, | |
768 | DWC2_HCCHAR_EPTYPE_CONTROL, | |
769 | DWC2_HCCHAR_EPTYPE_BULK, | |
770 | }; | |
771 | ||
daed3059 | 772 | static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer, |
25612f23 | 773 | u8 *pid, int in, void *buffer, int num_packets, |
d2ff51b3 | 774 | int xfer_len, int *actual_len, int odd_frame) |
daed3059 SB |
775 | { |
776 | int ret = 0; | |
777 | uint32_t sub; | |
778 | ||
779 | debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__, | |
780 | *pid, xfer_len, num_packets); | |
781 | ||
782 | writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) | | |
783 | (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) | | |
784 | (*pid << DWC2_HCTSIZ_PID_OFFSET), | |
785 | &hc_regs->hctsiz); | |
786 | ||
787 | if (!in && xfer_len) { | |
788 | memcpy(aligned_buffer, buffer, xfer_len); | |
789 | ||
790 | flush_dcache_range((unsigned long)aligned_buffer, | |
791 | (unsigned long)aligned_buffer + | |
792 | roundup(xfer_len, ARCH_DMA_MINALIGN)); | |
793 | } | |
794 | ||
795 | writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma); | |
796 | ||
797 | /* Clear old interrupt conditions for this host channel. */ | |
798 | writel(0x3fff, &hc_regs->hcint); | |
799 | ||
800 | /* Set host channel enable after all other setup is complete. */ | |
801 | clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK | | |
d2ff51b3 SB |
802 | DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS | |
803 | DWC2_HCCHAR_ODDFRM, | |
daed3059 | 804 | (1 << DWC2_HCCHAR_MULTICNT_OFFSET) | |
d2ff51b3 | 805 | (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) | |
daed3059 SB |
806 | DWC2_HCCHAR_CHEN); |
807 | ||
808 | ret = wait_for_chhltd(hc_regs, &sub, pid); | |
809 | if (ret < 0) | |
810 | return ret; | |
811 | ||
812 | if (in) { | |
813 | xfer_len -= sub; | |
814 | ||
815 | invalidate_dcache_range((unsigned long)aligned_buffer, | |
816 | (unsigned long)aligned_buffer + | |
817 | roundup(xfer_len, ARCH_DMA_MINALIGN)); | |
818 | ||
819 | memcpy(buffer, aligned_buffer, xfer_len); | |
820 | } | |
821 | *actual_len = xfer_len; | |
822 | ||
823 | return ret; | |
824 | } | |
825 | ||
cc3e3a9e | 826 | int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, |
25612f23 | 827 | unsigned long pipe, u8 *pid, int in, void *buffer, int len) |
6e9e0626 | 828 | { |
cc3e3a9e | 829 | struct dwc2_core_regs *regs = priv->regs; |
7b5e504d | 830 | struct dwc2_hc_regs *hc_regs = ®s->hc_regs[DWC2_HC_CHANNEL]; |
d2ff51b3 | 831 | struct dwc2_host_regs *host_regs = ®s->host_regs; |
6e9e0626 OT |
832 | int devnum = usb_pipedevice(pipe); |
833 | int ep = usb_pipeendpoint(pipe); | |
834 | int max = usb_maxpacket(dev, pipe); | |
7b5e504d | 835 | int eptype = dwc2_eptype[usb_pipetype(pipe)]; |
6e9e0626 | 836 | int done = 0; |
5877de91 | 837 | int ret = 0; |
b54e4470 SB |
838 | int do_split = 0; |
839 | int complete_split = 0; | |
6e9e0626 OT |
840 | uint32_t xfer_len; |
841 | uint32_t num_packets; | |
842 | int stop_transfer = 0; | |
56a7bbd7 | 843 | uint32_t max_xfer_len; |
d2ff51b3 | 844 | int ssplit_frame_num = 0; |
6e9e0626 | 845 | |
7b5e504d SW |
846 | debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, |
847 | in, len); | |
6e9e0626 | 848 | |
56a7bbd7 SB |
849 | max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; |
850 | if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) | |
851 | max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; | |
852 | if (max_xfer_len > DWC2_DATA_BUF_SIZE) | |
853 | max_xfer_len = DWC2_DATA_BUF_SIZE; | |
854 | ||
855 | /* Make sure that max_xfer_len is a multiple of max packet size. */ | |
856 | num_packets = max_xfer_len / max; | |
857 | max_xfer_len = num_packets * max; | |
858 | ||
daed3059 SB |
859 | /* Initialize channel */ |
860 | dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in, | |
861 | eptype, max); | |
6e9e0626 | 862 | |
b54e4470 SB |
863 | /* Check if the target is a FS/LS device behind a HS hub */ |
864 | if (dev->speed != USB_SPEED_HIGH) { | |
865 | uint8_t hub_addr; | |
866 | uint8_t hub_port; | |
867 | uint32_t hprt0 = readl(®s->hprt0); | |
868 | if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == | |
869 | DWC2_HPRT0_PRTSPD_HIGH) { | |
870 | usb_find_usb2_hub_address_port(dev, &hub_addr, | |
871 | &hub_port); | |
872 | dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port); | |
873 | ||
874 | do_split = 1; | |
875 | num_packets = 1; | |
876 | max_xfer_len = max; | |
877 | } | |
878 | } | |
6e9e0626 | 879 | |
daed3059 SB |
880 | do { |
881 | int actual_len = 0; | |
b54e4470 | 882 | uint32_t hcint; |
d2ff51b3 | 883 | int odd_frame = 0; |
6e9e0626 | 884 | xfer_len = len - done; |
6e9e0626 | 885 | |
56a7bbd7 SB |
886 | if (xfer_len > max_xfer_len) |
887 | xfer_len = max_xfer_len; | |
888 | else if (xfer_len > max) | |
6e9e0626 | 889 | num_packets = (xfer_len + max - 1) / max; |
56a7bbd7 | 890 | else |
6e9e0626 | 891 | num_packets = 1; |
6e9e0626 | 892 | |
b54e4470 SB |
893 | if (complete_split) |
894 | setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); | |
895 | else if (do_split) | |
896 | clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT); | |
db402e00 | 897 | |
d2ff51b3 SB |
898 | if (eptype == DWC2_HCCHAR_EPTYPE_INTR) { |
899 | int uframe_num = readl(&host_regs->hfnum); | |
900 | if (!(uframe_num & 0x1)) | |
901 | odd_frame = 1; | |
cc3e3a9e | 902 | } |
d1c880c6 | 903 | |
daed3059 SB |
904 | ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid, |
905 | in, (char *)buffer + done, num_packets, | |
d2ff51b3 | 906 | xfer_len, &actual_len, odd_frame); |
7b5e504d | 907 | |
b54e4470 SB |
908 | hcint = readl(&hc_regs->hcint); |
909 | if (complete_split) { | |
910 | stop_transfer = 0; | |
d2ff51b3 | 911 | if (hcint & DWC2_HCINT_NYET) { |
b54e4470 | 912 | ret = 0; |
d2ff51b3 SB |
913 | int frame_num = DWC2_HFNUM_MAX_FRNUM & |
914 | readl(&host_regs->hfnum); | |
915 | if (((frame_num - ssplit_frame_num) & | |
916 | DWC2_HFNUM_MAX_FRNUM) > 4) | |
917 | ret = -EAGAIN; | |
918 | } else | |
b54e4470 SB |
919 | complete_split = 0; |
920 | } else if (do_split) { | |
921 | if (hcint & DWC2_HCINT_ACK) { | |
d2ff51b3 SB |
922 | ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM & |
923 | readl(&host_regs->hfnum); | |
b54e4470 SB |
924 | ret = 0; |
925 | complete_split = 1; | |
926 | } | |
927 | } | |
6e9e0626 | 928 | |
5877de91 | 929 | if (ret) |
4a1d21fc | 930 | break; |
6e9e0626 | 931 | |
daed3059 SB |
932 | if (actual_len < xfer_len) |
933 | stop_transfer = 1; | |
6e9e0626 | 934 | |
daed3059 | 935 | done += actual_len; |
d1c880c6 | 936 | |
b54e4470 SB |
937 | /* Transactions are done when when either all data is transferred or |
938 | * there is a short transfer. In case of a SPLIT make sure the CSPLIT | |
939 | * is executed. | |
940 | */ | |
941 | } while (((done < len) && !stop_transfer) || complete_split); | |
6e9e0626 OT |
942 | |
943 | writel(0, &hc_regs->hcintmsk); | |
944 | writel(0xFFFFFFFF, &hc_regs->hcint); | |
945 | ||
946 | dev->status = 0; | |
947 | dev->act_len = done; | |
948 | ||
5877de91 | 949 | return ret; |
6e9e0626 OT |
950 | } |
951 | ||
7b5e504d | 952 | /* U-Boot USB transmission interface */ |
cc3e3a9e SG |
953 | int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev, |
954 | unsigned long pipe, void *buffer, int len) | |
7b5e504d SW |
955 | { |
956 | int devnum = usb_pipedevice(pipe); | |
957 | int ep = usb_pipeendpoint(pipe); | |
25612f23 | 958 | u8* pid; |
7b5e504d | 959 | |
25612f23 | 960 | if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) { |
7b5e504d SW |
961 | dev->status = 0; |
962 | return -EINVAL; | |
963 | } | |
964 | ||
25612f23 SB |
965 | if (usb_pipein(pipe)) |
966 | pid = &priv->in_data_toggle[devnum][ep]; | |
967 | else | |
968 | pid = &priv->out_data_toggle[devnum][ep]; | |
969 | ||
970 | return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len); | |
7b5e504d SW |
971 | } |
972 | ||
cc3e3a9e SG |
973 | static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev, |
974 | unsigned long pipe, void *buffer, int len, | |
975 | struct devrequest *setup) | |
6e9e0626 | 976 | { |
6e9e0626 | 977 | int devnum = usb_pipedevice(pipe); |
25612f23 SB |
978 | int ret, act_len; |
979 | u8 pid; | |
6e9e0626 OT |
980 | /* For CONTROL endpoint pid should start with DATA1 */ |
981 | int status_direction; | |
982 | ||
cc3e3a9e | 983 | if (devnum == priv->root_hub_devnum) { |
6e9e0626 OT |
984 | dev->status = 0; |
985 | dev->speed = USB_SPEED_HIGH; | |
cc3e3a9e SG |
986 | return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len, |
987 | setup); | |
6e9e0626 OT |
988 | } |
989 | ||
b54e4470 | 990 | /* SETUP stage */ |
ee837554 | 991 | pid = DWC2_HC_PID_SETUP; |
b54e4470 SB |
992 | do { |
993 | ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8); | |
994 | } while (ret == -EAGAIN); | |
ee837554 SW |
995 | if (ret) |
996 | return ret; | |
6e9e0626 | 997 | |
b54e4470 SB |
998 | /* DATA stage */ |
999 | act_len = 0; | |
6e9e0626 | 1000 | if (buffer) { |
282685e0 | 1001 | pid = DWC2_HC_PID_DATA1; |
b54e4470 SB |
1002 | do { |
1003 | ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe), | |
1004 | buffer, len); | |
1005 | act_len += dev->act_len; | |
1006 | buffer += dev->act_len; | |
1007 | len -= dev->act_len; | |
1008 | } while (ret == -EAGAIN); | |
ee837554 SW |
1009 | if (ret) |
1010 | return ret; | |
b54e4470 SB |
1011 | status_direction = usb_pipeout(pipe); |
1012 | } else { | |
1013 | /* No-data CONTROL always ends with an IN transaction */ | |
6e9e0626 | 1014 | status_direction = 1; |
b54e4470 | 1015 | } |
6e9e0626 | 1016 | |
b54e4470 | 1017 | /* STATUS stage */ |
ee837554 | 1018 | pid = DWC2_HC_PID_DATA1; |
b54e4470 SB |
1019 | do { |
1020 | ret = chunk_msg(priv, dev, pipe, &pid, status_direction, | |
1021 | priv->status_buffer, 0); | |
1022 | } while (ret == -EAGAIN); | |
ee837554 SW |
1023 | if (ret) |
1024 | return ret; | |
6e9e0626 | 1025 | |
ee837554 | 1026 | dev->act_len = act_len; |
6e9e0626 | 1027 | |
4a1d21fc | 1028 | return 0; |
6e9e0626 OT |
1029 | } |
1030 | ||
cc3e3a9e SG |
1031 | int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev, |
1032 | unsigned long pipe, void *buffer, int len, int interval) | |
6e9e0626 | 1033 | { |
5877de91 SW |
1034 | unsigned long timeout; |
1035 | int ret; | |
1036 | ||
e236519b | 1037 | /* FIXME: what is interval? */ |
5877de91 SW |
1038 | |
1039 | timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); | |
1040 | for (;;) { | |
1041 | if (get_timer(0) > timeout) { | |
1042 | printf("Timeout poll on interrupt endpoint\n"); | |
1043 | return -ETIMEDOUT; | |
1044 | } | |
cc3e3a9e | 1045 | ret = _submit_bulk_msg(priv, dev, pipe, buffer, len); |
5877de91 SW |
1046 | if (ret != -EAGAIN) |
1047 | return ret; | |
1048 | } | |
6e9e0626 OT |
1049 | } |
1050 | ||
cc3e3a9e | 1051 | static int dwc2_init_common(struct dwc2_priv *priv) |
6e9e0626 | 1052 | { |
cc3e3a9e | 1053 | struct dwc2_core_regs *regs = priv->regs; |
6e9e0626 OT |
1054 | uint32_t snpsid; |
1055 | int i, j; | |
1056 | ||
6e9e0626 OT |
1057 | snpsid = readl(®s->gsnpsid); |
1058 | printf("Core Release: %x.%03x\n", snpsid >> 12 & 0xf, snpsid & 0xfff); | |
1059 | ||
5cfd6c00 PG |
1060 | if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx && |
1061 | (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) { | |
6e9e0626 OT |
1062 | printf("SNPSID invalid (not DWC2 OTG device): %08x\n", snpsid); |
1063 | return -ENODEV; | |
1064 | } | |
1065 | ||
618da563 MV |
1066 | #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS |
1067 | priv->ext_vbus = 1; | |
1068 | #else | |
1069 | priv->ext_vbus = 0; | |
1070 | #endif | |
1071 | ||
55901989 | 1072 | dwc_otg_core_init(priv); |
6e9e0626 OT |
1073 | dwc_otg_core_host_init(regs); |
1074 | ||
1075 | clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | | |
1076 | DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | | |
1077 | DWC2_HPRT0_PRTOVRCURRCHNG, | |
1078 | DWC2_HPRT0_PRTRST); | |
1079 | mdelay(50); | |
1080 | clrbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET | | |
1081 | DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG | | |
1082 | DWC2_HPRT0_PRTRST); | |
1083 | ||
1084 | for (i = 0; i < MAX_DEVICE; i++) { | |
25612f23 SB |
1085 | for (j = 0; j < MAX_ENDPOINT; j++) { |
1086 | priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0; | |
1087 | priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0; | |
1088 | } | |
6e9e0626 OT |
1089 | } |
1090 | ||
2bf352f0 SR |
1091 | /* |
1092 | * Add a 1 second delay here. This gives the host controller | |
1093 | * a bit time before the comminucation with the USB devices | |
1094 | * is started (the bus is scanned) and fixes the USB detection | |
1095 | * problems with some problematic USB keys. | |
1096 | */ | |
1097 | if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) | |
1098 | mdelay(1000); | |
1099 | ||
6e9e0626 OT |
1100 | return 0; |
1101 | } | |
1102 | ||
cc3e3a9e | 1103 | static void dwc2_uninit_common(struct dwc2_core_regs *regs) |
6e9e0626 OT |
1104 | { |
1105 | /* Put everything in reset. */ | |
1106 | clrsetbits_le32(®s->hprt0, DWC2_HPRT0_PRTENA | | |
1107 | DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG | | |
1108 | DWC2_HPRT0_PRTOVRCURRCHNG, | |
1109 | DWC2_HPRT0_PRTRST); | |
cc3e3a9e SG |
1110 | } |
1111 | ||
f58a41e0 | 1112 | #ifndef CONFIG_DM_USB |
cc3e3a9e SG |
1113 | int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, |
1114 | int len, struct devrequest *setup) | |
1115 | { | |
1116 | return _submit_control_msg(&local, dev, pipe, buffer, len, setup); | |
1117 | } | |
1118 | ||
1119 | int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1120 | int len) | |
1121 | { | |
1122 | return _submit_bulk_msg(&local, dev, pipe, buffer, len); | |
1123 | } | |
1124 | ||
1125 | int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, | |
1126 | int len, int interval) | |
1127 | { | |
1128 | return _submit_int_msg(&local, dev, pipe, buffer, len, interval); | |
1129 | } | |
1130 | ||
1131 | /* U-Boot USB control interface */ | |
1132 | int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) | |
1133 | { | |
1134 | struct dwc2_priv *priv = &local; | |
1135 | ||
1136 | memset(priv, '\0', sizeof(*priv)); | |
1137 | priv->root_hub_devnum = 0; | |
1138 | priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR; | |
1139 | priv->aligned_buffer = aligned_buffer_addr; | |
1140 | priv->status_buffer = status_buffer_addr; | |
1141 | ||
1142 | /* board-dependant init */ | |
1143 | if (board_usb_init(index, USB_INIT_HOST)) | |
1144 | return -1; | |
1145 | ||
1146 | return dwc2_init_common(priv); | |
1147 | } | |
1148 | ||
1149 | int usb_lowlevel_stop(int index) | |
1150 | { | |
1151 | dwc2_uninit_common(local.regs); | |
1152 | ||
6e9e0626 OT |
1153 | return 0; |
1154 | } | |
f58a41e0 SG |
1155 | #endif |
1156 | ||
1157 | #ifdef CONFIG_DM_USB | |
1158 | static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev, | |
1159 | unsigned long pipe, void *buffer, int length, | |
1160 | struct devrequest *setup) | |
1161 | { | |
1162 | struct dwc2_priv *priv = dev_get_priv(dev); | |
1163 | ||
1164 | debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__, | |
1165 | dev->name, udev, udev->dev->name, udev->portnr); | |
1166 | ||
1167 | return _submit_control_msg(priv, udev, pipe, buffer, length, setup); | |
1168 | } | |
1169 | ||
1170 | static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev, | |
1171 | unsigned long pipe, void *buffer, int length) | |
1172 | { | |
1173 | struct dwc2_priv *priv = dev_get_priv(dev); | |
1174 | ||
1175 | debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); | |
1176 | ||
1177 | return _submit_bulk_msg(priv, udev, pipe, buffer, length); | |
1178 | } | |
1179 | ||
1180 | static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev, | |
1181 | unsigned long pipe, void *buffer, int length, | |
1182 | int interval) | |
1183 | { | |
1184 | struct dwc2_priv *priv = dev_get_priv(dev); | |
1185 | ||
1186 | debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev); | |
1187 | ||
1188 | return _submit_int_msg(priv, udev, pipe, buffer, length, interval); | |
1189 | } | |
1190 | ||
1191 | static int dwc2_usb_ofdata_to_platdata(struct udevice *dev) | |
1192 | { | |
1193 | struct dwc2_priv *priv = dev_get_priv(dev); | |
b4fbd089 | 1194 | const void *prop; |
f58a41e0 SG |
1195 | fdt_addr_t addr; |
1196 | ||
1197 | addr = dev_get_addr(dev); | |
1198 | if (addr == FDT_ADDR_T_NONE) | |
1199 | return -EINVAL; | |
1200 | priv->regs = (struct dwc2_core_regs *)addr; | |
1201 | ||
e160f7d4 SG |
1202 | prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), |
1203 | "disable-over-current", NULL); | |
b4fbd089 MV |
1204 | if (prop) |
1205 | priv->oc_disable = true; | |
1206 | ||
f58a41e0 SG |
1207 | return 0; |
1208 | } | |
1209 | ||
1210 | static int dwc2_usb_probe(struct udevice *dev) | |
1211 | { | |
1212 | struct dwc2_priv *priv = dev_get_priv(dev); | |
e96e064f MV |
1213 | struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev); |
1214 | ||
1215 | bus_priv->desc_before_addr = true; | |
f58a41e0 SG |
1216 | |
1217 | return dwc2_init_common(priv); | |
1218 | } | |
1219 | ||
1220 | static int dwc2_usb_remove(struct udevice *dev) | |
1221 | { | |
1222 | struct dwc2_priv *priv = dev_get_priv(dev); | |
1223 | ||
1224 | dwc2_uninit_common(priv->regs); | |
1225 | ||
1226 | return 0; | |
1227 | } | |
1228 | ||
1229 | struct dm_usb_ops dwc2_usb_ops = { | |
1230 | .control = dwc2_submit_control_msg, | |
1231 | .bulk = dwc2_submit_bulk_msg, | |
1232 | .interrupt = dwc2_submit_int_msg, | |
1233 | }; | |
1234 | ||
1235 | static const struct udevice_id dwc2_usb_ids[] = { | |
1236 | { .compatible = "brcm,bcm2835-usb" }, | |
f522f947 | 1237 | { .compatible = "snps,dwc2" }, |
f58a41e0 SG |
1238 | { } |
1239 | }; | |
1240 | ||
1241 | U_BOOT_DRIVER(usb_dwc2) = { | |
7a1386f9 | 1242 | .name = "dwc2_usb", |
f58a41e0 SG |
1243 | .id = UCLASS_USB, |
1244 | .of_match = dwc2_usb_ids, | |
1245 | .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata, | |
1246 | .probe = dwc2_usb_probe, | |
1247 | .remove = dwc2_usb_remove, | |
1248 | .ops = &dwc2_usb_ops, | |
1249 | .priv_auto_alloc_size = sizeof(struct dwc2_priv), | |
1250 | .flags = DM_FLAG_ALLOC_PRIV_DMA, | |
1251 | }; | |
1252 | #endif |