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1d8937a4 PW |
1 | /* |
2 | * (C) Copyright 2009 | |
3 | * Marvell Semiconductor <www.marvell.com> | |
4 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
1d8937a4 PW |
7 | */ |
8 | ||
9 | #include <common.h> | |
10 | #include <asm/io.h> | |
11 | #include <usb.h> | |
12 | #include "ehci.h" | |
fe11ae24 | 13 | #include <linux/mbus.h> |
a7efd719 | 14 | #include <asm/arch/cpu.h> |
cd48225b | 15 | #include <dm.h> |
805ad7ee AA |
16 | |
17 | #if defined(CONFIG_KIRKWOOD) | |
3dc23f78 | 18 | #include <asm/arch/soc.h> |
805ad7ee AA |
19 | #elif defined(CONFIG_ORION5X) |
20 | #include <asm/arch/orion5x.h> | |
21 | #endif | |
1d8937a4 | 22 | |
74d34421 AA |
23 | DECLARE_GLOBAL_DATA_PTR; |
24 | ||
1d8937a4 PW |
25 | #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4)) |
26 | #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4)) | |
27 | #define USB_TARGET_DRAM 0x0 | |
28 | ||
29 | /* | |
30 | * USB 2.0 Bridge Address Decoding registers setup | |
31 | */ | |
cd48225b | 32 | #ifdef CONFIG_DM_USB |
fe11ae24 | 33 | |
cd48225b SR |
34 | struct ehci_mvebu_priv { |
35 | struct ehci_ctrl ehci; | |
36 | fdt_addr_t hcd_base; | |
37 | }; | |
fe11ae24 SR |
38 | |
39 | /* | |
40 | * Once all the older Marvell SoC's (Orion, Kirkwood) are converted | |
41 | * to the common mvebu archticture including the mbus setup, this | |
42 | * will be the only function needed to configure the access windows | |
43 | */ | |
cd48225b | 44 | static void usb_brg_adrdec_setup(u32 base) |
fe11ae24 SR |
45 | { |
46 | const struct mbus_dram_target_info *dram; | |
47 | int i; | |
48 | ||
49 | dram = mvebu_mbus_dram_info(); | |
50 | ||
51 | for (i = 0; i < 4; i++) { | |
cd48225b SR |
52 | writel(0, base + USB_WINDOW_CTRL(i)); |
53 | writel(0, base + USB_WINDOW_BASE(i)); | |
fe11ae24 SR |
54 | } |
55 | ||
56 | for (i = 0; i < dram->num_cs; i++) { | |
57 | const struct mbus_dram_window *cs = dram->cs + i; | |
58 | ||
59 | /* Write size, attributes and target id to control register */ | |
82b9143b SR |
60 | writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | |
61 | (dram->mbus_dram_target_id << 4) | 1, | |
cd48225b | 62 | base + USB_WINDOW_CTRL(i)); |
fe11ae24 SR |
63 | |
64 | /* Write base address to base register */ | |
cd48225b | 65 | writel(cs->base, base + USB_WINDOW_BASE(i)); |
fe11ae24 SR |
66 | } |
67 | } | |
cd48225b SR |
68 | |
69 | static int ehci_mvebu_probe(struct udevice *dev) | |
70 | { | |
71 | struct ehci_mvebu_priv *priv = dev_get_priv(dev); | |
72 | struct ehci_hccr *hccr; | |
73 | struct ehci_hcor *hcor; | |
74 | ||
75 | /* | |
76 | * Get the base address for EHCI controller from the device node | |
77 | */ | |
78 | priv->hcd_base = dev_get_addr(dev); | |
79 | if (priv->hcd_base == FDT_ADDR_T_NONE) { | |
80 | debug("Can't get the EHCI register base address\n"); | |
81 | return -ENXIO; | |
82 | } | |
83 | ||
84 | usb_brg_adrdec_setup(priv->hcd_base); | |
85 | ||
86 | hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100); | |
87 | hcor = (struct ehci_hcor *) | |
88 | ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); | |
89 | ||
90 | debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n", | |
91 | (u32)hccr, (u32)hcor, | |
92 | (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); | |
93 | ||
94 | return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); | |
95 | } | |
96 | ||
cd48225b SR |
97 | static const struct udevice_id ehci_usb_ids[] = { |
98 | { .compatible = "marvell,orion-ehci", }, | |
99 | { } | |
100 | }; | |
101 | ||
102 | U_BOOT_DRIVER(ehci_mvebu) = { | |
103 | .name = "ehci_mvebu", | |
104 | .id = UCLASS_USB, | |
105 | .of_match = ehci_usb_ids, | |
106 | .probe = ehci_mvebu_probe, | |
40527342 | 107 | .remove = ehci_deregister, |
cd48225b SR |
108 | .ops = &ehci_usb_ops, |
109 | .platdata_auto_alloc_size = sizeof(struct usb_platdata), | |
110 | .priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv), | |
111 | .flags = DM_FLAG_ALLOC_PRIV_DMA, | |
112 | }; | |
113 | ||
fe11ae24 | 114 | #else |
8a333716 AS |
115 | #define MVUSB_BASE(port) MVUSB0_BASE |
116 | ||
117 | static void usb_brg_adrdec_setup(int index) | |
1d8937a4 PW |
118 | { |
119 | int i; | |
74d34421 | 120 | u32 size, base, attrib; |
1d8937a4 PW |
121 | |
122 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { | |
123 | ||
124 | /* Enable DRAM bank */ | |
125 | switch (i) { | |
126 | case 0: | |
74d34421 | 127 | attrib = MVUSB0_CPU_ATTR_DRAM_CS0; |
1d8937a4 PW |
128 | break; |
129 | case 1: | |
74d34421 | 130 | attrib = MVUSB0_CPU_ATTR_DRAM_CS1; |
1d8937a4 PW |
131 | break; |
132 | case 2: | |
74d34421 | 133 | attrib = MVUSB0_CPU_ATTR_DRAM_CS2; |
1d8937a4 PW |
134 | break; |
135 | case 3: | |
74d34421 | 136 | attrib = MVUSB0_CPU_ATTR_DRAM_CS3; |
1d8937a4 PW |
137 | break; |
138 | default: | |
139 | /* invalide bank, disable access */ | |
140 | attrib = 0; | |
141 | break; | |
142 | } | |
143 | ||
74d34421 AA |
144 | size = gd->bd->bi_dram[i].size; |
145 | base = gd->bd->bi_dram[i].start; | |
1d8937a4 | 146 | if ((size) && (attrib)) |
82b9143b SR |
147 | writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM, |
148 | attrib, MVCPU_WIN_ENABLE), | |
149 | MVUSB0_BASE + USB_WINDOW_CTRL(i)); | |
1d8937a4 | 150 | else |
82b9143b SR |
151 | writel(MVCPU_WIN_DISABLE, |
152 | MVUSB0_BASE + USB_WINDOW_CTRL(i)); | |
1d8937a4 | 153 | |
82b9143b | 154 | writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i)); |
1d8937a4 PW |
155 | } |
156 | } | |
157 | ||
158 | /* | |
159 | * Create the appropriate control structures to manage | |
160 | * a new EHCI host controller. | |
161 | */ | |
127efc4f TK |
162 | int ehci_hcd_init(int index, enum usb_init_type init, |
163 | struct ehci_hccr **hccr, struct ehci_hcor **hcor) | |
1d8937a4 | 164 | { |
8a333716 | 165 | usb_brg_adrdec_setup(index); |
1d8937a4 | 166 | |
8a333716 | 167 | *hccr = (struct ehci_hccr *)(MVUSB_BASE(index) + 0x100); |
676ae068 LS |
168 | *hcor = (struct ehci_hcor *)((uint32_t) *hccr |
169 | + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); | |
1d8937a4 | 170 | |
74d34421 | 171 | debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n", |
676ae068 LS |
172 | (uint32_t)*hccr, (uint32_t)*hcor, |
173 | (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); | |
1d8937a4 PW |
174 | |
175 | return 0; | |
176 | } | |
177 | ||
178 | /* | |
179 | * Destroy the appropriate control structures corresponding | |
180 | * the the EHCI host controller. | |
181 | */ | |
676ae068 | 182 | int ehci_hcd_stop(int index) |
1d8937a4 PW |
183 | { |
184 | return 0; | |
185 | } | |
cd48225b SR |
186 | |
187 | #endif /* CONFIG_DM_USB */ |