[people/ms/u-boot.git] / include / asm-m68k / immap.h

/*
 * ColdFire Internal Memory Map and Defines
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __IMMAP_H
#define __IMMAP_H

#ifdef CONFIG_M52277
#include <asm/immap_5227x.h>
#include <asm/m5227x.h>

#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))

#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)

#ifdef CONFIG_LCD
#define	CONFIG_SYS_LCD_BASE		(MMAP_LCD)
#endif

/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(6)
#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
#endif

#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE	(6)
#endif

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS		(128)
#endif				/* CONFIG_M52277 */

#ifdef CONFIG_M5235
#include <asm/immap_5235.h>
#include <asm/m5235.h>

#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))

/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
#endif

#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE	(6)
#endif

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS		(128)
#endif				/* CONFIG_M5235 */

#ifdef CONFIG_M5249
#include <asm/immap_5249.h>
#include <asm/m5249.h>

#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS		(64)

/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
#define CONFIG_SYS_TMRINTR_NO		(31)
#define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
#endif
#endif				/* CONFIG_M5249 */

#ifdef CONFIG_M5253
#include <asm/immap_5253.h>
#include <asm/m5249.h>
#include <asm/m5253.h>

#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS		(64)

/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
#define CONFIG_SYS_TMRINTR_NO		(27)
#define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
#endif
#endif				/* CONFIG_M5253 */

#ifdef CONFIG_M5271
#include <asm/immap_5271.h>
#include <asm/m5271.h>

#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))

/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(0)		/* Level must include inorder to work */
#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
#endif

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS		(128)
#endif				/* CONFIG_M5271 */

#ifdef CONFIG_M5272
#include <asm/immap_5272.h>
#include <asm/m5272.h>

#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
#define CONFIG_SYS_NUM_IRQS		(64)

/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_TMR0)
#define CONFIG_SYS_TMR_BASE		(MMAP_TMR3)
#define CONFIG_SYS_TMRPND_REG		(((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
#define CONFIG_SYS_TMRINTR_NO		(INT_TMR3)
#define CONFIG_SYS_TMRINTR_MASK	(INT_ISR_INT24)
#define CONFIG_SYS_TMRINTR_PEND	(0)
#define CONFIG_SYS_TMRINTR_PRI		(INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif				/* CONFIG_M5272 */

#ifdef CONFIG_M5275
#include <asm/immap_5275.h>
#include <asm/m5275.h>

#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS		(192)

/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif				/* CONFIG_M5275 */

#ifdef CONFIG_M5282
#include <asm/immap_5282.h>
#include <asm/m5282.h>

#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS		(128)

/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
#define CONFIG_SYS_TMRINTR_MASK	(1 << INT0_LO_DTMR3)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
#endif
#endif				/* CONFIG_M5282 */

#if defined(CONFIG_M5329) || defined(CONFIG_M5373)
#include <asm/immap_5329.h>
#include <asm/m5329.h>

#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC)
#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)

/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(6)
#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
#endif

#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE	(6)
#endif

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS		(128)
#endif				/* CONFIG_M5329 && CONFIG_M5373 */

#if defined(CONFIG_M54451) || defined(CONFIG_M54455)
#include <asm/immap_5445x.h>
#include <asm/m5445x.h>

#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
#if defined(CONFIG_M54455EVB)
#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
#endif

#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))

#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)

/* Timer */
#ifdef CONFIG_MCFTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(6)
#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
#endif

#ifdef CONFIG_MCFPIT
#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
#define CONFIG_SYS_PIT_PRESCALE	(6)
#endif

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS		(128)

#ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_BAR0		(CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_BAR5		(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_TBATR5		(CONFIG_SYS_SDRAM_BASE)
#endif
#endif				/* CONFIG_M54451 || CONFIG_M54455 */

#ifdef CONFIG_M547x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>

#ifdef CONFIG_FSLDMAFEC
#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)

#define FEC0_RX_TASK		0
#define FEC0_TX_TASK		1
#define FEC0_RX_PRIORITY	6
#define FEC0_TX_PRIORITY	7
#define FEC0_RX_INIT		16
#define FEC0_TX_INIT		17
#define FEC1_RX_TASK		2
#define FEC1_TX_TASK		3
#define FEC1_RX_PRIORITY	6
#define FEC1_TX_PRIORITY	7
#define FEC1_RX_INIT		30
#define FEC1_TX_INIT		31
#endif

#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))

#ifdef CONFIG_SLTTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
#define CONFIG_SYS_TMR_BASE		(MMAP_SLT0)
#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
#define CONFIG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
#endif

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS		(128)

#ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_BAR0		(0x40000000)
#define CONFIG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
#endif
#endif				/* CONFIG_M547x */

#ifdef CONFIG_M548x
#include <asm/immap_547x_8x.h>
#include <asm/m547x_8x.h>

#ifdef CONFIG_FSLDMAFEC
#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)

#define FEC0_RX_TASK		0
#define FEC0_TX_TASK		1
#define FEC0_RX_PRIORITY	6
#define FEC0_TX_PRIORITY	7
#define FEC0_RX_INIT		16
#define FEC0_TX_INIT		17
#define FEC1_RX_TASK		2
#define FEC1_TX_TASK		3
#define FEC1_RX_PRIORITY	6
#define FEC1_TX_PRIORITY	7
#define FEC1_RX_INIT		30
#define FEC1_TX_INIT		31
#endif

#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))

/* Timer */
#ifdef CONFIG_SLTTMR
#define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
#define CONFIG_SYS_TMR_BASE		(MMAP_SLT0)
#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
#define CONFIG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
#endif

#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
#define CONFIG_SYS_NUM_IRQS		(128)

#ifdef CONFIG_PCI
#define CONFIG_SYS_PCI_BAR0		(CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_BAR1		(CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_PCI_TBATR0		(CONFIG_SYS_MBAR)
#define CONFIG_SYS_PCI_TBATR1		(CONFIG_SYS_SDRAM_BASE)
#endif
#endif				/* CONFIG_M548x */

#endif				/* __IMMAP_H */
Commit	Line	Data
48dbfeab TL	1	/*
	2	* ColdFire Internal Memory Map and Defines
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __IMMAP_H
	27	#define __IMMAP_H
c883f6ea	28
1552af70 TL	29	#ifdef CONFIG_M52277
	30	#include <asm/immap_5227x.h>
	31	#include <asm/m5227x.h>
	32
6d0f6bcf	33	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
1552af70	34
6d0f6bcf	35	#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
1552af70 TL	36
1552af70 TL	37	#ifdef CONFIG_LCD
6d0f6bcf	38	#define CONFIG_SYS_LCD_BASE (MMAP_LCD)
1552af70 TL	39	#endif
	40
	41	/* Timer */
	42	#ifdef CONFIG_MCFTMR
6d0f6bcf JCPV	43	#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
	44	#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
	45	#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
	46	#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
	47	#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
	48	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	49	#define CONFIG_SYS_TMRINTR_PRI (6)
	50	#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
1552af70 TL	51	#endif
	52
	53	#ifdef CONFIG_MCFPIT
6d0f6bcf JCPV	54	#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
	55	#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
	56	#define CONFIG_SYS_PIT_PRESCALE (6)
1552af70 TL	57	#endif
1552af70 TL	58
6d0f6bcf JCPV	59	#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
6d0f6bcf JCPV	60	#define CONFIG_SYS_NUM_IRQS (128)
1552af70 TL	61	#endif /* CONFIG_M52277 */
1552af70 TL	62
4a442d31 TL	63	#ifdef CONFIG_M5235
	64	#include <asm/immap_5235.h>
	65	#include <asm/m5235.h>
	66
6d0f6bcf JCPV	67	#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
6d0f6bcf JCPV	68	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
4a442d31 TL	69
	70	/* Timer */
	71	#ifdef CONFIG_MCFTMR
6d0f6bcf JCPV	72	#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
	73	#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
	74	#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
	75	#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
	76	#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
	77	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	78	#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
	79	#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
4a442d31 TL	80	#endif
	81
	82	#ifdef CONFIG_MCFPIT
6d0f6bcf JCPV	83	#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
	84	#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
	85	#define CONFIG_SYS_PIT_PRESCALE (6)
4a442d31 TL	86	#endif
4a442d31 TL	87
6d0f6bcf JCPV	88	#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
6d0f6bcf JCPV	89	#define CONFIG_SYS_NUM_IRQS (128)
4a442d31 TL	90	#endif /* CONFIG_M5235 */
4a442d31 TL	91
56115665 TL	92	#ifdef CONFIG_M5249
	93	#include <asm/immap_5249.h>
	94	#include <asm/m5249.h>
	95
6d0f6bcf	96	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
56115665	97
6d0f6bcf JCPV	98	#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
6d0f6bcf JCPV	99	#define CONFIG_SYS_NUM_IRQS (64)
56115665 TL	100
	101	/* Timer */
	102	#ifdef CONFIG_MCFTMR
6d0f6bcf JCPV	103	#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
	104	#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
	105	#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
	106	#define CONFIG_SYS_TMRINTR_NO (31)
	107	#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
	108	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	109	#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC \| MCFSIM_ICR_LEVEL7 \| MCFSIM_ICR_PRI3)
	110	#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
56115665 TL	111	#endif
	112	#endif /* CONFIG_M5249 */
	113
a1436a84 TL	114	#ifdef CONFIG_M5253
	115	#include <asm/immap_5253.h>
	116	#include <asm/m5249.h>
	117	#include <asm/m5253.h>
	118
6d0f6bcf	119	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
a1436a84	120
6d0f6bcf JCPV	121	#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
6d0f6bcf JCPV	122	#define CONFIG_SYS_NUM_IRQS (64)
a1436a84 TL	123
	124	/* Timer */
	125	#ifdef CONFIG_MCFTMR
6d0f6bcf JCPV	126	#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
	127	#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
	128	#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR))
	129	#define CONFIG_SYS_TMRINTR_NO (27)
	130	#define CONFIG_SYS_TMRINTR_MASK (0x00000400)
	131	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	132	#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC \| MCFSIM_ICR_LEVEL3 \| MCFSIM_ICR_PRI3)
	133	#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8)
a1436a84 TL	134	#endif
	135	#endif /* CONFIG_M5253 */
	136
56115665 TL	137	#ifdef CONFIG_M5271
	138	#include <asm/immap_5271.h>
	139	#include <asm/m5271.h>
	140
6d0f6bcf JCPV	141	#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
6d0f6bcf JCPV	142	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
56115665 TL	143
	144	/* Timer */
	145	#ifdef CONFIG_MCFTMR
6d0f6bcf JCPV	146	#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
	147	#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
	148	#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
	149	#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
	150	#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
	151	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	152	#define CONFIG_SYS_TMRINTR_PRI (0) /* Level must include inorder to work */
	153	#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
56115665 TL	154	#endif
56115665 TL	155
6d0f6bcf JCPV	156	#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
6d0f6bcf JCPV	157	#define CONFIG_SYS_NUM_IRQS (128)
56115665 TL	158	#endif /* CONFIG_M5271 */
	159
	160	#ifdef CONFIG_M5272
	161	#include <asm/immap_5272.h>
	162	#include <asm/m5272.h>
	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
6d0f6bcf JCPV	165	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
56115665	166
6d0f6bcf JCPV	167	#define CONFIG_SYS_INTR_BASE (MMAP_INTC)
6d0f6bcf JCPV	168	#define CONFIG_SYS_NUM_IRQS (64)
56115665 TL	169
	170	/* Timer */
	171	#ifdef CONFIG_MCFTMR
6d0f6bcf JCPV	172	#define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0)
	173	#define CONFIG_SYS_TMR_BASE (MMAP_TMR3)
	174	#define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
	175	#define CONFIG_SYS_TMRINTR_NO (INT_TMR3)
	176	#define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24)
	177	#define CONFIG_SYS_TMRINTR_PEND (0)
	178	#define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI \| INT_ICR1_TMR3IPL(5))
	179	#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
56115665 TL	180	#endif
	181	#endif /* CONFIG_M5272 */
	182
f71d9d91 MF	183	#ifdef CONFIG_M5275
	184	#include <asm/immap_5275.h>
	185	#include <asm/m5275.h>
	186
6d0f6bcf JCPV	187	#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
	188	#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
	189	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
f71d9d91	190
6d0f6bcf JCPV	191	#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
6d0f6bcf JCPV	192	#define CONFIG_SYS_NUM_IRQS (192)
f71d9d91 MF	193
	194	/* Timer */
	195	#ifdef CONFIG_MCFTMR
6d0f6bcf JCPV	196	#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
	197	#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
	198	#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
	199	#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
	200	#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22)
	201	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	202	#define CONFIG_SYS_TMRINTR_PRI (0x1E)
	203	#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
f71d9d91 MF	204	#endif
	205	#endif /* CONFIG_M5275 */
	206
56115665 TL	207	#ifdef CONFIG_M5282
	208	#include <asm/immap_5282.h>
	209	#include <asm/m5282.h>
	210
6d0f6bcf JCPV	211	#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
6d0f6bcf JCPV	212	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40))
56115665	213
6d0f6bcf JCPV	214	#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
6d0f6bcf JCPV	215	#define CONFIG_SYS_NUM_IRQS (128)
56115665 TL	216
	217	/* Timer */
	218	#ifdef CONFIG_MCFTMR
6d0f6bcf JCPV	219	#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
	220	#define CONFIG_SYS_TMR_BASE (MMAP_DTMR3)
	221	#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
	222	#define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3)
	223	#define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3)
	224	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	225	#define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */
	226	#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
56115665 TL	227	#endif
	228	#endif /* CONFIG_M5282 */
	229
aa5f1f9d	230	#if defined(CONFIG_M5329) \|\| defined(CONFIG_M5373)
48dbfeab TL	231	#include <asm/immap_5329.h>
	232	#include <asm/m5329.h>
	233
6d0f6bcf JCPV	234	#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC)
	235	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
	236	#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
48dbfeab TL	237
	238	/* Timer */
	239	#ifdef CONFIG_MCFTMR
6d0f6bcf JCPV	240	#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
	241	#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
	242	#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
	243	#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
	244	#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
	245	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	246	#define CONFIG_SYS_TMRINTR_PRI (6)
	247	#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
48dbfeab TL	248	#endif
	249
	250	#ifdef CONFIG_MCFPIT
6d0f6bcf JCPV	251	#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
	252	#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
	253	#define CONFIG_SYS_PIT_PRESCALE (6)
48dbfeab TL	254	#endif
48dbfeab TL	255
6d0f6bcf JCPV	256	#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
6d0f6bcf JCPV	257	#define CONFIG_SYS_NUM_IRQS (128)
aa5f1f9d	258	#endif /* CONFIG_M5329 && CONFIG_M5373 */
c883f6ea	259
05316f8e	260	#if defined(CONFIG_M54451) \|\| defined(CONFIG_M54455)
8ae158cd TL	261	#include <asm/immap_5445x.h>
	262	#include <asm/m5445x.h>
	263
6d0f6bcf	264	#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
05316f8e	265	#if defined(CONFIG_M54455EVB)
6d0f6bcf	266	#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
05316f8e	267	#endif
8ae158cd	268
6d0f6bcf	269	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000))
8ae158cd	270
6d0f6bcf	271	#define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC)
8ae158cd TL	272
	273	/* Timer */
	274	#ifdef CONFIG_MCFTMR
6d0f6bcf JCPV	275	#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0)
	276	#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1)
	277	#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
	278	#define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1)
	279	#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33)
	280	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	281	#define CONFIG_SYS_TMRINTR_PRI (6)
	282	#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8)
8ae158cd TL	283	#endif
	284
	285	#ifdef CONFIG_MCFPIT
6d0f6bcf JCPV	286	#define CONFIG_SYS_UDELAY_BASE (MMAP_PIT0)
	287	#define CONFIG_SYS_PIT_BASE (MMAP_PIT1)
	288	#define CONFIG_SYS_PIT_PRESCALE (6)
8ae158cd TL	289	#endif
8ae158cd TL	290
6d0f6bcf JCPV	291	#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
6d0f6bcf JCPV	292	#define CONFIG_SYS_NUM_IRQS (128)
8ae158cd TL	293
8ae158cd TL	294	#ifdef CONFIG_PCI
6d0f6bcf JCPV	295	#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
	296	#define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE)
	297	#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
	298	#define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE)
8ae158cd	299	#endif
05316f8e	300	#endif /* CONFIG_M54451 \|\| CONFIG_M54455 */
8ae158cd	301
4621fc3f TL	302	#ifdef CONFIG_M547x
	303	#include <asm/immap_547x_8x.h>
	304	#include <asm/m547x_8x.h>
	305
	306	#ifdef CONFIG_FSLDMAFEC
6d0f6bcf JCPV	307	#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
6d0f6bcf JCPV	308	#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
4621fc3f TL	309
	310	#define FEC0_RX_TASK 0
	311	#define FEC0_TX_TASK 1
	312	#define FEC0_RX_PRIORITY 6
	313	#define FEC0_TX_PRIORITY 7
	314	#define FEC0_RX_INIT 16
	315	#define FEC0_TX_INIT 17
	316	#define FEC1_RX_TASK 2
	317	#define FEC1_TX_TASK 3
	318	#define FEC1_RX_PRIORITY 6
	319	#define FEC1_TX_PRIORITY 7
	320	#define FEC1_RX_INIT 30
	321	#define FEC1_TX_INIT 31
	322	#endif
	323
6d0f6bcf	324	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
4621fc3f TL	325
4621fc3f TL	326	#ifdef CONFIG_SLTTMR
6d0f6bcf JCPV	327	#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
	328	#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
	329	#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
	330	#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
	331	#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
	332	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	333	#define CONFIG_SYS_TMRINTR_PRI (0x1E)
	334	#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
4621fc3f TL	335	#endif
4621fc3f TL	336
6d0f6bcf JCPV	337	#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
6d0f6bcf JCPV	338	#define CONFIG_SYS_NUM_IRQS (128)
4621fc3f TL	339
4621fc3f TL	340	#ifdef CONFIG_PCI
6d0f6bcf JCPV	341	#define CONFIG_SYS_PCI_BAR0 (0x40000000)
	342	#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
	343	#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
	344	#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
4621fc3f TL	345	#endif
	346	#endif /* CONFIG_M547x */
	347
	348	#ifdef CONFIG_M548x
	349	#include <asm/immap_547x_8x.h>
	350	#include <asm/m547x_8x.h>
	351
	352	#ifdef CONFIG_FSLDMAFEC
6d0f6bcf JCPV	353	#define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0)
6d0f6bcf JCPV	354	#define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1)
4621fc3f TL	355
	356	#define FEC0_RX_TASK 0
	357	#define FEC0_TX_TASK 1
	358	#define FEC0_RX_PRIORITY 6
	359	#define FEC0_TX_PRIORITY 7
	360	#define FEC0_RX_INIT 16
	361	#define FEC0_TX_INIT 17
	362	#define FEC1_RX_TASK 2
	363	#define FEC1_TX_TASK 3
	364	#define FEC1_RX_PRIORITY 6
	365	#define FEC1_TX_PRIORITY 7
	366	#define FEC1_RX_INIT 30
	367	#define FEC1_TX_INIT 31
	368	#endif
	369
6d0f6bcf	370	#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100))
4621fc3f TL	371
	372	/* Timer */
	373	#ifdef CONFIG_SLTTMR
6d0f6bcf JCPV	374	#define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1)
	375	#define CONFIG_SYS_TMR_BASE (MMAP_SLT0)
	376	#define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
	377	#define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0)
	378	#define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54)
	379	#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK)
	380	#define CONFIG_SYS_TMRINTR_PRI (0x1E)
	381	#define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000)
4621fc3f TL	382	#endif
4621fc3f TL	383
6d0f6bcf JCPV	384	#define CONFIG_SYS_INTR_BASE (MMAP_INTC0)
6d0f6bcf JCPV	385	#define CONFIG_SYS_NUM_IRQS (128)
4621fc3f TL	386
4621fc3f TL	387	#ifdef CONFIG_PCI
6d0f6bcf JCPV	388	#define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR)
	389	#define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE)
	390	#define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR)
	391	#define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE)
4621fc3f TL	392	#endif
	393	#endif /* CONFIG_M548x */
	394
48dbfeab	395	#endif /* __IMMAP_H */