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Commit | Line | Data |
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c609719b | 1 | /* |
a20b27a3 | 2 | * (C) Copyright 2001-2004 |
c609719b WD |
3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | /* | |
16 | * High Level Configuration Options | |
17 | * (easy to change) | |
18 | */ | |
19 | ||
20 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ | |
c609719b | 21 | #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ |
c837dcb1 | 22 | #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ |
6f35c531 | 23 | #undef CONFIG_CPCI405_6U /* enable this for 6U boards */ |
c609719b | 24 | |
2ae18241 WD |
25 | #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 |
26 | ||
3a8f28d0 | 27 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
c609719b | 28 | |
a20b27a3 | 29 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
c609719b WD |
30 | |
31 | #define CONFIG_BAUDRATE 9600 | |
c609719b | 32 | |
c609719b | 33 | #undef CONFIG_BOOTARGS |
a20b27a3 SR |
34 | #undef CONFIG_BOOTCOMMAND |
35 | ||
36 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
c609719b WD |
37 | |
38 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 39 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
c609719b | 40 | |
96e21f86 | 41 | #define CONFIG_PPC4xx_EMAC |
c609719b | 42 | #define CONFIG_MII 1 /* MII PHY management */ |
c837dcb1 | 43 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
a20b27a3 | 44 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
6f35c531 MF |
45 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ |
46 | ||
6f35c531 | 47 | #undef CONFIG_HAS_ETH1 |
c609719b WD |
48 | |
49 | #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ | |
50 | ||
5d2ebe1b JL |
51 | /* |
52 | * BOOTP options | |
53 | */ | |
54 | #define CONFIG_BOOTP_SUBNETMASK | |
55 | #define CONFIG_BOOTP_GATEWAY | |
56 | #define CONFIG_BOOTP_HOSTNAME | |
57 | #define CONFIG_BOOTP_BOOTPATH | |
58 | #define CONFIG_BOOTP_DNS | |
59 | #define CONFIG_BOOTP_DNS2 | |
60 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
61 | ||
49cf7e8e JL |
62 | /* |
63 | * Command line configuration. | |
64 | */ | |
49cf7e8e JL |
65 | #define CONFIG_CMD_PCI |
66 | #define CONFIG_CMD_IRQ | |
67 | #define CONFIG_CMD_IDE | |
49cf7e8e | 68 | #define CONFIG_CMD_DATE |
49cf7e8e JL |
69 | #define CONFIG_CMD_BSP |
70 | #define CONFIG_CMD_EEPROM | |
71 | ||
c609719b WD |
72 | #define CONFIG_MAC_PARTITION |
73 | #define CONFIG_DOS_PARTITION | |
74 | ||
a20b27a3 SR |
75 | #define CONFIG_SUPPORT_VFAT |
76 | ||
c837dcb1 | 77 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
c609719b | 78 | |
c837dcb1 | 79 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
c609719b WD |
80 | |
81 | /* | |
82 | * Miscellaneous configurable options | |
83 | */ | |
c6265f7f | 84 | #undef CONFIG_SYS_LONGHELP /* undef to save memory */ |
c609719b | 85 | |
49cf7e8e | 86 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 87 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
c609719b | 88 | #else |
6d0f6bcf | 89 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
c609719b | 90 | #endif |
6d0f6bcf JCPV |
91 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
92 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
93 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
c609719b | 94 | |
6d0f6bcf | 95 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
c609719b | 96 | |
6d0f6bcf | 97 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
c609719b | 98 | |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
100 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
c609719b | 101 | |
550650dd | 102 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
550650dd SR |
103 | #define CONFIG_SYS_NS16550_SERIAL |
104 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
105 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
106 | ||
6d0f6bcf | 107 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ |
6d0f6bcf | 108 | #define CONFIG_SYS_BASE_BAUD 691200 |
c609719b | 109 | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
111 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
c609719b | 112 | |
ac53ee83 MF |
113 | #define CONFIG_CMDLINE_EDITING /* add command line history */ |
114 | ||
6d0f6bcf | 115 | #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ |
53cf9435 | 116 | |
c609719b WD |
117 | /*----------------------------------------------------------------------- |
118 | * PCI stuff | |
119 | *----------------------------------------------------------------------- | |
120 | */ | |
a20b27a3 SR |
121 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
122 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
123 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
124 | ||
842033e6 | 125 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
a20b27a3 | 126 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
a20b27a3 SR |
127 | /* resource configuration */ |
128 | ||
129 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ | |
130 | ||
131 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ | |
132 | ||
133 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ | |
134 | ||
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
136 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ | |
137 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ | |
138 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ | |
139 | #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ | |
140 | #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ | |
141 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
142 | #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ | |
143 | #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ | |
468ebf19 | 144 | #define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */ |
c609719b | 145 | |
82379b55 MF |
146 | #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ |
147 | ||
c609719b WD |
148 | /*----------------------------------------------------------------------- |
149 | * IDE/ATA stuff | |
150 | *----------------------------------------------------------------------- | |
151 | */ | |
c837dcb1 WD |
152 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
153 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
c609719b WD |
154 | #define CONFIG_IDE_RESET 1 /* reset for ide supported */ |
155 | ||
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
157 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ | |
c609719b | 158 | |
6d0f6bcf JCPV |
159 | #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 |
160 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
c609719b | 161 | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
163 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
164 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ | |
c609719b WD |
165 | |
166 | /*----------------------------------------------------------------------- | |
167 | * Start addresses for the final memory configuration | |
168 | * (Set up by the startup code) | |
6d0f6bcf | 169 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
c609719b | 170 | */ |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
172 | #define CONFIG_SYS_FLASH_BASE 0xFFFC0000 | |
173 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
174 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ | |
175 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ | |
c609719b | 176 | |
3ba605d4 MF |
177 | #define CONFIG_PRAM 0 /* use pram variable to overwrite */ |
178 | ||
c609719b WD |
179 | /* |
180 | * For booting Linux, the board info and command line data | |
181 | * have to be in the first 8 MB of memory, since this is | |
182 | * the maximum mapped by the Linux kernel during initialization. | |
183 | */ | |
6d0f6bcf | 184 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
ac53ee83 | 185 | |
c609719b WD |
186 | /*----------------------------------------------------------------------- |
187 | * FLASH organization | |
188 | */ | |
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
190 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
c609719b | 191 | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
193 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
c609719b | 194 | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
196 | #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ | |
197 | #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ | |
c609719b WD |
198 | /* |
199 | * The following defines are added for buggy IOP480 byte interface. | |
200 | * All other boards should use the standard values (CPCI405 etc.) | |
201 | */ | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ |
203 | #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ | |
204 | #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ | |
c609719b | 205 | |
6d0f6bcf | 206 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
c609719b | 207 | |
c609719b WD |
208 | #if 0 /* Use NVRAM for environment variables */ |
209 | /*----------------------------------------------------------------------- | |
210 | * NVRAM organization | |
211 | */ | |
9314cee6 | 212 | #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
0e8d1586 JCPV |
213 | #define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ |
214 | #define CONFIG_ENV_ADDR \ | |
6d0f6bcf | 215 | (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */ |
c609719b WD |
216 | |
217 | #else /* Use EEPROM for environment variables */ | |
218 | ||
bb1f8b4f | 219 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
0e8d1586 JCPV |
220 | #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
221 | #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ | |
8bde7f77 | 222 | /* total size of a CAT24WC16 is 2048 bytes */ |
c609719b WD |
223 | #endif |
224 | ||
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
226 | #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ | |
227 | #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ | |
c609719b WD |
228 | |
229 | /*----------------------------------------------------------------------- | |
230 | * I2C EEPROM (CAT24WC16) for environment | |
231 | */ | |
880540de DE |
232 | #define CONFIG_SYS_I2C |
233 | #define CONFIG_SYS_I2C_PPC4XX | |
234 | #define CONFIG_SYS_I2C_PPC4XX_CH0 | |
235 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000 | |
236 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F | |
c609719b | 237 | |
6d0f6bcf JCPV |
238 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
239 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ | |
c837dcb1 | 240 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
242 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ | |
c609719b | 243 | /* 16 byte page write mode using*/ |
c837dcb1 | 244 | /* last 4 bits of the address */ |
6d0f6bcf | 245 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
c609719b | 246 | |
c609719b WD |
247 | /* |
248 | * Init Memory Controller: | |
249 | * | |
250 | * BR0/1 and OR0/1 (FLASH) | |
251 | */ | |
252 | ||
253 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ | |
254 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ | |
255 | ||
256 | /*----------------------------------------------------------------------- | |
257 | * External Bus Controller (EBC) Setup | |
258 | */ | |
259 | ||
c837dcb1 | 260 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
6d0f6bcf JCPV |
261 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
262 | #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 263 | |
c837dcb1 | 264 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
6d0f6bcf JCPV |
265 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
266 | #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ | |
c609719b | 267 | |
c837dcb1 | 268 | /* Memory Bank 2 (CAN0, 1) initialization */ |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
270 | #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ | |
271 | #define CONFIG_SYS_LED_ADDR 0xF0000380 | |
c609719b | 272 | |
c837dcb1 | 273 | /* Memory Bank 3 (CompactFlash IDE) initialization */ |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
275 | #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
c609719b | 276 | |
c837dcb1 | 277 | /* Memory Bank 4 (NVRAM/RTC) initialization */ |
6d0f6bcf JCPV |
278 | /*#define CONFIG_SYS_EBC_PB4AP 0x01805280 / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1 */ |
279 | #define CONFIG_SYS_EBC_PB4AP 0x01805680 /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1 */ | |
280 | #define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ | |
c609719b | 281 | |
c837dcb1 | 282 | /* Memory Bank 5 (optional Quart) initialization */ |
6d0f6bcf JCPV |
283 | #define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ |
284 | #define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ | |
c609719b | 285 | |
c837dcb1 | 286 | /* Memory Bank 6 (FPGA internal) initialization */ |
6d0f6bcf JCPV |
287 | #define CONFIG_SYS_EBC_PB6AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
288 | #define CONFIG_SYS_EBC_PB6CR 0xF041A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ | |
289 | #define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000 | |
c609719b WD |
290 | |
291 | /*----------------------------------------------------------------------- | |
292 | * FPGA stuff | |
293 | */ | |
294 | /* FPGA internal regs */ | |
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_FPGA_MODE 0x00 |
296 | #define CONFIG_SYS_FPGA_STATUS 0x02 | |
297 | #define CONFIG_SYS_FPGA_TS 0x04 | |
298 | #define CONFIG_SYS_FPGA_TS_LOW 0x06 | |
299 | #define CONFIG_SYS_FPGA_TS_CAP0 0x10 | |
300 | #define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12 | |
301 | #define CONFIG_SYS_FPGA_TS_CAP1 0x14 | |
302 | #define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16 | |
303 | #define CONFIG_SYS_FPGA_TS_CAP2 0x18 | |
304 | #define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a | |
305 | #define CONFIG_SYS_FPGA_TS_CAP3 0x1c | |
306 | #define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e | |
c609719b WD |
307 | |
308 | /* FPGA Mode Reg */ | |
6d0f6bcf JCPV |
309 | #define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001 |
310 | #define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002 | |
311 | #define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004 /* only set on CPCI-405 Ver 3 */ | |
312 | #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100 | |
313 | #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000 | |
314 | #define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000 | |
c609719b WD |
315 | |
316 | /* FPGA Status Reg */ | |
6d0f6bcf JCPV |
317 | #define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001 |
318 | #define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002 | |
319 | #define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004 | |
320 | #define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008 | |
321 | #define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000 | |
c609719b | 322 | |
6d0f6bcf JCPV |
323 | #define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */ |
324 | #define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for XC2S15 */ | |
c609719b WD |
325 | |
326 | /* FPGA program pin configuration */ | |
6d0f6bcf JCPV |
327 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
328 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ | |
329 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ | |
330 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */ | |
331 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */ | |
c609719b WD |
332 | |
333 | /*----------------------------------------------------------------------- | |
334 | * Definitions for initial stack pointer and data area (in data cache) | |
335 | */ | |
6d0f6bcf | 336 | #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ |
c609719b | 337 | |
6d0f6bcf | 338 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
553f0982 | 339 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
25ddd1fb | 340 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 341 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
c609719b | 342 | |
c609719b | 343 | #endif /* __CONFIG_H */ |