[people/ms/u-boot.git] / include / configs / KUP4X.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 * Derived from ../tqm8xx/tqm8xx.c
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC859T		1	/* This is a MPC859T CPU		*/
#define CONFIG_KUP4X		1	/* ...on a KUP4X module			*/

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1			*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate			*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled			*/
#else
#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second		*/
#endif

#define CONFIG_BOARD_TYPES	1	/* support board types			*/

#define CONFIG_SYS_8XX_FACT		8	/* Multiply by 8			*/
#define CONFIG_SYS_8XX_XIN		16000000	/* 16 MHz in			*/


#define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT))

/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
/* in general, we always know this for FADS+new ADS anyway */
#define CONFIG_8xx_GCLK_FREQ	 MPC8XX_HZ


#undef	CONFIG_BOOTARGS


#define CONFIG_EXTRA_ENV_SETTINGS						\
"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"				\
  "run addhw;diskboot 200000 0:1;bootm 200000\0"				\
"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
 run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
 usb stop; bootm 200000\0"      \
"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0"				\
"panic_boot=echo No Bootdevice !!! reset\0"					\
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"	\
"ramargs=setenv bootargs root=/dev/ram rw\0"					\
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}"	\
 ":${netmask}:${hostname}:${netdev}:off\0"					\
"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0"		\
"netdev=eth0\0"									\
"silent=1\0"									\
"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0"		\
"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};"		\
 "cp.b 200000 40040000 14000\0"

#define CONFIG_BOOTCOMMAND  \
    "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"


#define CONFIG_MISC_INIT_R	1
#define CONFIG_MISC_INIT_F	1

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#define	CONFIG_WATCHDOG		1	/* watchdog enabled		*/

#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/*
 * enable I2C and select the hardware/software driver
 */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/

#define CONFIG_SYS_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
#define CONFIG_SYS_I2C_SLAVE		0xFE

#ifdef CONFIG_SOFT_I2C
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
#endif	/* CONFIG_SOFT_I2C */


/*-----------------------------------------------------------------------
 * I2C Configuration
 */

#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander			*/
#define CONFIG_SYS_I2C_RTC_ADDR	0x51	/* PCF8563 RTC				*/


/* List of I2C addresses to be verified by POST */

#define I2C_ADDR_LIST	{CONFIG_SYS_I2C_PICIO_ADDR,	\
			CONFIG_SYS_I2C_RTC_ADDR,	\
			}


#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/

#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_MII

#if 0
#define CONFIG_ETHADDR                  00:0B:64:80:00:00 /* our OUI from IEEE */
#endif
#undef CONFIG_KUP4K_LOGO

/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE


#if 1
/* POST support */

#define CONFIG_POST		(CONFIG_SYS_POST_CPU	   | \
				 CONFIG_SYS_POST_RTC	   | \
				 CONFIG_SYS_POST_I2C)
#endif


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB

#ifdef CONFIG_POST
    #define CONFIG_CMD_DIAG
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x000400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x003C00000	/* 4 ... 60 MB in DRAM	*/
#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }

#define CONFIG_SYS_CONSOLE_INFO_QUIET 1

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	0x10000

/* Address and size of Redundant Environment Sector	*/
#if 0
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif
/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#if 1
#define CONFIG_SYS_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x4B26500D	/* 'K&P<CR>' */
#endif
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)


/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)


/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register	15-30
 *-----------------------------------------------------------------------
 * set the PLL, the low-power modes and the reset control (15-29)
 */
#define CONFIG_SYS_PLPRCR	((CONFIG_SYS_8XX_FACT << PLPRCR_MFI_SHIFT) |	\
				PLPRCR_SPLSS | PLPRCR_TEXPS)


/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF00
#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */

/* KUP4K use both slots, SLOT_A as "primary". */
#define CONFIG_PCMCIA_SLOT_A 1

#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

#define PCMCIA_SOCKETS_NO 1
#define PCMCIA_MEM_WIN_NO 8
/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#define CONFIG_IDE_LED			1   /* LED   for ide supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_IDE1_OFFSET	(4 * CONFIG_SYS_PCMCIA_MEM_SIZE)

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100


/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */
#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_2_CLK | OR_EHTR | OR_BI)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )


/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00


#define CONFIG_SYS_MPTPR 0x400

/*
 * MAMR settings for SDRAM
 */
#define CONFIG_SYS_MAMR 0x80802114


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/


#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot	*/
#if 0
#define CONFIG_AUTOBOOT_PROMPT		\
	"Boote in %d Sekunden - stop mit \"2\"\n", bootdelay
#endif
#define CONFIG_AUTOBOOT_STOP_STR	"."	/* easy to stop for now		*/
#define CONFIG_SILENT_CONSOLE	1

#define CONFIG_USB_STORAGE	1
#define CONFIG_USB_SL811HS	1

#endif	/* __CONFIG_H */
Commit	Line	Data
0608e04d	1	/*
414eec35	2	* (C) Copyright 2000-2005
0608e04d WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* board/config.h - configuration options, board specific
	27	* Derived from ../tqm8xx/tqm8xx.c
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37
	38	#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */
	39	#define CONFIG_KUP4X 1 /* ...on a KUP4X module */
	40
	41	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	42	#undef CONFIG_8xx_CONS_SMC2
	43	#undef CONFIG_8xx_CONS_NONE
	44	#define CONFIG_BAUDRATE 115200 /* console baudrate */
	45	#if 0
	46	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	47	#else
	48	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
	49	#endif
	50
0608e04d WD	51	#define CONFIG_BOARD_TYPES 1 /* support board types */
0608e04d WD	52
6d0f6bcf JCPV	53	#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */
6d0f6bcf JCPV	54	#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */
0608e04d WD	55
0608e04d WD	56
6d0f6bcf	57	#define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT))
0608e04d WD	58
	59	/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
	60	/* in general, we always know this for FADS+new ADS anyway */
	61	#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
	62
	63
	64	#undef CONFIG_BOOTARGS
	65
	66
	67	#define CONFIG_EXTRA_ENV_SETTINGS \
	68	"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
	69	"run addhw;diskboot 200000 0:1;bootm 200000\0" \
02b11f8e WD	70	"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
	71	run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
	72	usb stop; bootm 200000\0" \
0608e04d WD	73	"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
0608e04d WD	74	"panic_boot=echo No Bootdevice !!! reset\0" \
fe126d8b	75	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
0608e04d	76	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	77	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
	78	":${netmask}:${hostname}:${netdev}:off\0" \
	79	"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
0608e04d WD	80	"netdev=eth0\0" \
	81	"silent=1\0" \
	82	"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
fe126d8b	83	"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \
0608e04d WD	84	"cp.b 200000 40040000 14000\0"
	85
	86	#define CONFIG_BOOTCOMMAND \
02b11f8e	87	"run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"
0608e04d WD	88
	89
	90	#define CONFIG_MISC_INIT_R 1
	91	#define CONFIG_MISC_INIT_F 1
	92
	93	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	94	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
0608e04d	95
02b11f8e	96	#define CONFIG_WATCHDOG 1 /* watchdog enabled */
0608e04d WD	97
	98	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	99
	100	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	101
7be044e4 JL	102	/*
	103	* BOOTP options
	104	*/
	105	#define CONFIG_BOOTP_SUBNETMASK
	106	#define CONFIG_BOOTP_GATEWAY
	107	#define CONFIG_BOOTP_HOSTNAME
	108	#define CONFIG_BOOTP_BOOTPATH
	109	#define CONFIG_BOOTP_BOOTFILESIZE
	110
0608e04d WD	111
	112	#define CONFIG_MAC_PARTITION
	113	#define CONFIG_DOS_PARTITION
	114
02b11f8e WD	115	/*
	116	* enable I2C and select the hardware/software driver
	117	*/
	118	#undef CONFIG_HARD_I2C /* I2C with hardware support */
	119	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	120
6d0f6bcf JCPV	121	#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
6d0f6bcf JCPV	122	#define CONFIG_SYS_I2C_SLAVE 0xFE
02b11f8e WD	123
	124	#ifdef CONFIG_SOFT_I2C
	125	/*
	126	* Software (bit-bang) I2C driver configuration
	127	*/
	128	#define PB_SCL 0x00000020 /* PB 26 */
	129	#define PB_SDA 0x00000010 /* PB 27 */
	130
	131	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	132	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	133	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	134	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	135	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	136	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	137	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	138	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	139	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
	140	#endif /* CONFIG_SOFT_I2C */
	141
	142
	143	/*-----------------------------------------------------------------------
	144	* I2C Configuration
	145	*/
	146
6d0f6bcf JCPV	147	#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
6d0f6bcf JCPV	148	#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
02b11f8e WD	149
	150
	151	/* List of I2C addresses to be verified by POST */
0608e04d	152
6d0f6bcf JCPV	153	#define I2C_ADDR_LIST {CONFIG_SYS_I2C_PICIO_ADDR, \
6d0f6bcf JCPV	154	CONFIG_SYS_I2C_RTC_ADDR, \
02b11f8e WD	155	}
	156
	157
	158	#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
	159
6d0f6bcf	160	#define CONFIG_SYS_DISCOVER_PHY
63ff004c	161	#define CONFIG_MII
02b11f8e WD	162
	163	#if 0
	164	#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
	165	#endif
0608e04d WD	166	#undef CONFIG_KUP4K_LOGO
	167
	168	/* Define to allow the user to overwrite serial and ethaddr */
	169	#define CONFIG_ENV_OVERWRITE
	170
02b11f8e WD	171
	172	#if 1
	173	/* POST support */
	174
6d0f6bcf JCPV	175	#define CONFIG_POST (CONFIG_SYS_POST_CPU \| \
	176	CONFIG_SYS_POST_RTC \| \
	177	CONFIG_SYS_POST_I2C)
02b11f8e WD	178	#endif
02b11f8e WD	179
348f258f JL	180
	181	/*
	182	* Command line configuration.
	183	*/
	184	#include <config_cmd_default.h>
	185
	186	#define CONFIG_CMD_DATE
	187	#define CONFIG_CMD_DHCP
	188	#define CONFIG_CMD_FAT
	189	#define CONFIG_CMD_I2C
	190	#define CONFIG_CMD_IDE
	191	#define CONFIG_CMD_NFS
348f258f JL	192	#define CONFIG_CMD_SNTP
	193	#define CONFIG_CMD_USB
	194
af075ee9 JL	195	#ifdef CONFIG_POST
	196	#define CONFIG_CMD_DIAG
	197	#endif
0608e04d WD	198
	199	/*
	200	* Miscellaneous configurable options
	201	*/
6d0f6bcf JCPV	202	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	203	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
348f258f	204	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	205	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0608e04d	206	#else
6d0f6bcf	207	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0608e04d	208	#endif
6d0f6bcf JCPV	209	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	210	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	211	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0608e04d	212
6d0f6bcf JCPV	213	#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
	214	#define CONFIG_SYS_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */
	215	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
0608e04d	216
6d0f6bcf	217	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
0608e04d	218
6d0f6bcf	219	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
0608e04d	220
6d0f6bcf	221	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
0608e04d WD	222
	223	/*
	224	* Low Level Configuration Settings
	225	* (address mappings, register initial values, etc.)
	226	* You should know what you are doing if you make changes here.
	227	*/
	228	/*-----------------------------------------------------------------------
	229	* Internal Memory Mapped Register
	230	*/
6d0f6bcf	231	#define CONFIG_SYS_IMMR 0xFFF00000
0608e04d WD	232
	233	/*-----------------------------------------------------------------------
	234	* Definitions for initial stack pointer and data area (in DPRAM)
	235	*/
6d0f6bcf JCPV	236	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	237	#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	238	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	239	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	240	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0608e04d WD	241
	242	/*-----------------------------------------------------------------------
	243	* Start addresses for the final memory configuration
	244	* (Set up by the startup code)
6d0f6bcf	245	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0608e04d	246	*/
6d0f6bcf JCPV	247	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	248	#define CONFIG_SYS_FLASH_BASE 0x40000000
	249	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */
	250	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	251	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
0608e04d WD	252
	253	/*
	254	* For booting Linux, the board info and command line data
	255	* have to be in the first 8 MB of memory, since this is
	256	* the maximum mapped by the Linux kernel during initialization.
	257	*/
6d0f6bcf	258	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0608e04d WD	259
	260	/*-----------------------------------------------------------------------
	261	* FLASH organization
	262	*/
6d0f6bcf JCPV	263	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	264	#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
0608e04d	265
6d0f6bcf JCPV	266	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	267	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0608e04d	268
5a1aceb0	269	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	270	#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
	271	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
	272	#define CONFIG_ENV_SECT_SIZE 0x10000
0608e04d WD	273
	274	/* Address and size of Redundant Environment Sector */
	275	#if 0
0e8d1586 JCPV	276	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
0e8d1586 JCPV	277	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
0608e04d WD	278	#endif
	279	/*-----------------------------------------------------------------------
	280	* Hardware Information Block
	281	*/
02b11f8e	282	#if 1
6d0f6bcf JCPV	283	#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
	284	#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
	285	#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
0608e04d WD	286	#endif
	287	/*-----------------------------------------------------------------------
	288	* Cache Configuration
	289	*/
6d0f6bcf	290	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
348f258f	291	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	292	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
0608e04d WD	293	#endif
	294
	295	/*-----------------------------------------------------------------------
	296	* SYPCR - System Protection Control 11-9
	297	* SYPCR can only be written once after reset!
	298	*-----------------------------------------------------------------------
	299	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	300	*/
02b11f8e	301	#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
6d0f6bcf	302	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
0608e04d WD	303	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
0608e04d WD	304	#else
6d0f6bcf	305	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
0608e04d WD	306	#endif
	307
	308	/*-----------------------------------------------------------------------
	309	* SIUMCR - SIU Module Configuration 11-6
	310	*-----------------------------------------------------------------------
	311	* PCMCIA config., multi-function pin tri-state
	312	*/
6d0f6bcf	313	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC00)
0608e04d WD	314
	315	/*-----------------------------------------------------------------------
	316	* TBSCR - Time Base Status and Control 11-26
	317	*-----------------------------------------------------------------------
	318	* Clear Reference Interrupt Status, Timebase freezing enabled
	319	*/
6d0f6bcf	320	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
0608e04d WD	321
	322
	323	/*-----------------------------------------------------------------------
	324	* PISCR - Periodic Interrupt Status and Control 11-31
	325	*-----------------------------------------------------------------------
	326	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	327	*/
6d0f6bcf	328	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
0608e04d WD	329
	330
	331	/*-----------------------------------------------------------------------
	332	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	333	*-----------------------------------------------------------------------
	334	* set the PLL, the low-power modes and the reset control (15-29)
	335	*/
6d0f6bcf	336	#define CONFIG_SYS_PLPRCR ((CONFIG_SYS_8XX_FACT << PLPRCR_MFI_SHIFT) \| \
0608e04d WD	337	PLPRCR_SPLSS \| PLPRCR_TEXPS)
	338
	339
	340	/*-----------------------------------------------------------------------
	341	* SCCR - System Clock and reset Control Register 15-27
	342	*-----------------------------------------------------------------------
	343	* Set clock output, timebase and RTC source and divider,
	344	* power management and some other internal clocks
	345	*/
	346	#define SCCR_MASK SCCR_EBDF00
6d0f6bcf	347	#define CONFIG_SYS_SCCR (SCCR_TBS \| SCCR_EBDF01 \| \
0608e04d WD	348	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	349	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	350	SCCR_DFALCD00)
	351
	352	/*-----------------------------------------------------------------------
	353	* PCMCIA stuff
	354	*-----------------------------------------------------------------------
	355	*
	356	*/
	357
	358	/* KUP4K use both slots, SLOT_A as "primary". */
	359	#define CONFIG_PCMCIA_SLOT_A 1
	360
6d0f6bcf JCPV	361	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	362	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	363	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	364	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	365	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	366	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	367	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	368	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
0608e04d WD	369
	370	#define PCMCIA_SOCKETS_NO 1
	371	#define PCMCIA_MEM_WIN_NO 8
	372	/*-----------------------------------------------------------------------
	373	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	374	*-----------------------------------------------------------------------
	375	*/
	376
	377	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	378
	379	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	380	#define CONFIG_IDE_LED 1 /* LED for ide supported */
	381	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	382
6d0f6bcf JCPV	383	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	384	#define CONFIG_SYS_IDE_MAXDEVICE 2
0608e04d	385
6d0f6bcf	386	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
0608e04d	387
6d0f6bcf	388	#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
0608e04d	389
6d0f6bcf	390	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
0608e04d WD	391
0608e04d WD	392	/* Offset for data I/O */
6d0f6bcf	393	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
0608e04d WD	394
0608e04d WD	395	/* Offset for normal register accesses */
6d0f6bcf	396	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
0608e04d WD	397
0608e04d WD	398	/* Offset for alternate registers */
6d0f6bcf	399	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
0608e04d WD	400
	401
	402	/*-----------------------------------------------------------------------
	403	*
	404	*-----------------------------------------------------------------------
	405	*
	406	*/
6d0f6bcf	407	#define CONFIG_SYS_DER 0
0608e04d WD	408
	409	/*
	410	* Init Memory Controller:
	411	*
	412	* BR0/1 and OR0/1 (FLASH)
	413	*/
	414	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	415
	416	/* used to re-map FLASH both when starting from SRAM or FLASH:
	417	* restrict access enough to keep SRAM working (if any)
	418	* but not too much to meddle with FLASH accesses
	419	*/
6d0f6bcf JCPV	420	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	421	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
0608e04d WD	422
	423	/*
	424	* FLASH timing:
	425	*/
6d0f6bcf	426	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
0608e04d WD	427	OR_SCY_2_CLK \| OR_EHTR \| OR_BI)
0608e04d WD	428
6d0f6bcf JCPV	429	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	430	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	431	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
0608e04d WD	432
	433
	434	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	435	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
0608e04d WD	436
0608e04d WD	437
6d0f6bcf	438	#define CONFIG_SYS_MPTPR 0x400
0608e04d WD	439
	440	/*
	441	* MAMR settings for SDRAM
	442	*/
6d0f6bcf	443	#define CONFIG_SYS_MAMR 0x80802114
0608e04d WD	444
	445
	446	/*
	447	* Internal Definitions
	448	*
	449	* Boot Flags
	450	*/
	451	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	452	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	453
	454
	455	#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
	456	#if 0
f2302d44 SR	457	#define CONFIG_AUTOBOOT_PROMPT \
f2302d44 SR	458	"Boote in %d Sekunden - stop mit \"2\"\n", bootdelay
0608e04d WD	459	#endif
	460	#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
	461	#define CONFIG_SILENT_CONSOLE 1
	462
5cf91d6b WD	463	#define CONFIG_USB_STORAGE 1
	464	#define CONFIG_USB_SL811HS 1
	465
0608e04d	466	#endif /* __CONFIG_H */