[people/ms/u-boot.git] / include / configs / M5249EVB.h

/*
 * Configuation settings for the esd TASREG board.
 *
 * (C) Copyright 2004
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5249EVB_H
#define _M5249EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef  CONFIG_WATCHDOG

#undef CONFIG_MONITOR_IS_IN_RAM		/* no pre-loader required!!! ;-) */

/*
 * BOOTP options
 */
#undef CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_BOOTP_BOOTPATH
#undef CONFIG_BOOTP_GATEWAY
#undef CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */

#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/

#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support	*/
#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/

#define CONFIG_SYS_LOAD_ADDR		0x200000	/* default load address */

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

/*
 * Clock configuration: enable only one of the following options
 */

#undef  CONFIG_SYS_PLL_BYPASS				/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK		1		/* MCF5249 can run at 140MHz   */
#define	CONFIG_SYS_CLK			132025600	/* MCF5249 can run at 140MHz   */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define	CONFIG_SYS_MBAR2		0x80000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text);

#define CONFIG_ENV_OFFSET		0x4000	/* Address of Environment Sector*/
#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	0x2000 /* see README - env sector total size	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)

#if 0 /* test-only */
#define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
#endif

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(1 * 1024*1024)	/* Reserve 1 MB for malloc()	*/
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
					 CF_ADDRMASK(2) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */

/* CS0 - AMD Flash, address 0xffc00000 */
#define	CONFIG_SYS_CS0_BASE		0xffe00000
#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */

/* CS1 - FPGA, address 0xe0000000 */
#define	CONFIG_SYS_CS1_BASE		0xe0000000
#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define	CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none          */
#define	CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54*/
#define	CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable       */
#define	CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable       */
#define	CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define	CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led                     */

#endif	/* M5249 */
Commit	Line	Data
a605aacd TL	1	/*
	2	* Configuation settings for the esd TASREG board.
	3	*
	4	* (C) Copyright 2004
	5	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
a605aacd TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M5249EVB_H
	15	#define _M5249EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
a605aacd TL	21	#define CONFIG_MCFTMR
	22
	23	#define CONFIG_MCFUART
6d0f6bcf	24	#define CONFIG_SYS_UART_PORT (0)
a605aacd TL	25
	26	#undef CONFIG_WATCHDOG
	27
	28	#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
	29
	30	/*
	31	* BOOTP options
	32	*/
	33	#undef CONFIG_BOOTP_BOOTFILESIZE
	34	#undef CONFIG_BOOTP_BOOTPATH
	35	#undef CONFIG_BOOTP_GATEWAY
	36	#undef CONFIG_BOOTP_HOSTNAME
	37
	38	/*
	39	* Command line configuration.
	40	*/
a605aacd	41
6d0f6bcf	42	#define CONFIG_SYS_LONGHELP /* undef to save memory */
a605aacd	43
6d0f6bcf	44	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
a605aacd	45
6d0f6bcf	46	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
a605aacd	47	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
a605aacd TL	48	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
a605aacd TL	49
6d0f6bcf	50	#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
a605aacd	51
6d0f6bcf JCPV	52	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	53	#define CONFIG_SYS_MEMTEST_END 0x380000
a605aacd	54
a605aacd TL	55	/*
	56	* Clock configuration: enable only one of the following options
	57	*/
	58
6d0f6bcf JCPV	59	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	60	#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */
	61	#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */
a605aacd TL	62
	63	/*
	64	* Low Level Configuration Settings
	65	* (address mappings, register initial values, etc.)
	66	* You should know what you are doing if you make changes here.
	67	*/
	68
6d0f6bcf JCPV	69	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	70	#define CONFIG_SYS_MBAR2 0x80000000
a605aacd TL	71
	72	/*-----------------------------------------------------------------------
	73	* Definitions for initial stack pointer and data area (in DPRAM)
	74	*/
6d0f6bcf	75	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	76	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb	77	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	78	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
a605aacd	79
5296cb1d	80	#define LDS_BOARD_TEXT \
0649cd0d SG	81	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d SG	82	env/embedded.o(.text);
5296cb1d	83
0e8d1586 JCPV	84	#define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/
	85	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
	86	#define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */
a605aacd TL	87
	88	/*-----------------------------------------------------------------------
	89	* Start addresses for the final memory configuration
	90	* (Set up by the startup code)
6d0f6bcf	91	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
a605aacd	92	*/
6d0f6bcf JCPV	93	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	94	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
012522fe	95	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
a605aacd TL	96
	97	#if 0 /* test-only */
	98	#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
	99	#endif
	100
6d0f6bcf	101	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
a605aacd	102
6d0f6bcf JCPV	103	#define CONFIG_SYS_MONITOR_LEN 0x20000
	104	#define CONFIG_SYS_MALLOC_LEN (1 * 10241024) / Reserve 1 MB for malloc() */
	105	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
a605aacd TL	106
	107	/*
	108	* For booting Linux, the board info and command line data
	109	* have to be in the first 8 MB of memory, since this is
	110	* the maximum mapped by the Linux kernel during initialization ??
	111	*/
6d0f6bcf	112	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
a605aacd TL	113
	114	/*-----------------------------------------------------------------------
	115	* FLASH organization
	116	*/
6d0f6bcf JCPV	117	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	118	#ifdef CONFIG_SYS_FLASH_CFI
a605aacd	119
00b1883a	120	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	121	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	122	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	123	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	124	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	125	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	126	# define CONFIG_SYS_FLASH_CHECKSUM
	127	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
a605aacd TL	128	#endif
	129
	130	/*-----------------------------------------------------------------------
	131	* Cache Configuration
	132	*/
6d0f6bcf	133	#define CONFIG_SYS_CACHELINE_SIZE 16
a605aacd	134
dd9f054e	135	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	136	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	137	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	138	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	139	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	140	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
	141	CF_ADDRMASK(2) \| \
	142	CF_ACR_EN \| CF_ACR_SM_ALL)
	143	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	144	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	145	CF_ACR_EN \| CF_ACR_SM_ALL)
	146	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	147	CF_CACR_DBWE)
	148
a605aacd TL	149	/*-----------------------------------------------------------------------
	150	* Memory bank definitions
	151	*/
	152
	153	/* CS0 - AMD Flash, address 0xffc00000 */
012522fe TL	154	#define CONFIG_SYS_CS0_BASE 0xffe00000
012522fe TL	155	#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */
a605aacd	156	/ Note: There is a CSMR0/DRAM vector problem, need to disable C/I */
012522fe	157	#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
a605aacd TL	158
a605aacd TL	159	/* CS1 - FPGA, address 0xe0000000 */
012522fe TL	160	#define CONFIG_SYS_CS1_BASE 0xe0000000
	161	#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */
	162	#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
a605aacd TL	163
	164	/*-----------------------------------------------------------------------
	165	* Port configuration
	166	*/
6d0f6bcf JCPV	167	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	168	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
	169	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	170	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	171	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	172	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	173	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
a605aacd TL	174
a605aacd TL	175	#endif /* M5249 */