[people/ms/u-boot.git] / include / configs / M5253DEMO.h

/*
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * Hayden Fraser (Hayden.Fraser@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _M5253DEMO_H
#define _M5253DEMO_H

#define CONFIG_MCF52x2		/* define processor family */
#define CONFIG_M5253		/* define processor type */
#define CONFIG_M5253DEMO	/* define board type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

#undef CONFIG_WATCHDOG		/* disable watchdog */

#define CONFIG_BOOTDELAY	5

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_ENV_OFFSET		0x4000
#	define CONFIG_ENV_SECT_SIZE	0x1000
#	define CONFIG_ENV_IS_IN_FLASH	1
#else
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
#	define CONFIG_ENV_SECT_SIZE	0x1000
#	define CONFIG_ENV_IS_IN_FLASH	1
#endif

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_PING

#ifdef CONFIG_CMD_IDE
/* ATA */
#	define CONFIG_DOS_PARTITION
#	define CONFIG_MAC_PARTITION
#	define CONFIG_IDE_RESET		1
#	define CONFIG_IDE_PREINIT	1
#	define CONFIG_ATAPI
#	undef CONFIG_LBA48

#	define CONFIG_SYS_IDE_MAXBUS		1
#	define CONFIG_SYS_IDE_MAXDEVICE	2

#	define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
#	define CONFIG_SYS_ATA_IDE0_OFFSET	0

#	define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
#	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
#	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
#	define _IO_BASE			0
#endif

#define CONFIG_DRIVER_DM9000
#ifdef CONFIG_DRIVER_DM9000
#	define CONFIG_DM9000_BASE	((CONFIG_SYS_CSAR1 << 16) | 0x300)
#	define DM9000_IO		CONFIG_DM9000_BASE
#	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
#	undef CONFIG_DM9000_DEBUG

#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR		10.82.121.249
#	define CONFIG_NETMASK		255.255.252.0
#	define CONFIG_SERVERIP		10.82.120.80
#	define CONFIG_GATEWAYIP		10.82.123.254
#	define CONFIG_OVERWRITE_ETHADDR_ONCE

#	define CONFIG_EXTRA_ENV_SETTINGS		\
		"netdev=eth0\0"				\
		"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
		"loadaddr=10000\0"			\
		"u-boot=u-boot.bin\0"			\
		"load=tftp ${loadaddr) ${u-boot}\0"	\
		"upd=run load; run prog\0"		\
		"prog=prot off 0 2ffff;"	\
		"era 0 2ffff;"			\
		"cp.b ${loadaddr} 0 ${filesize};"	\
		"save\0"				\
		""
#endif

#define CONFIG_HOSTNAME		M5253DEMO

/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hw support */
#define CONFIG_SYS_I2C_SPEED		80000
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x00000280
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET	(0)

#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#	define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#define CONFIG_SYS_HZ			1000

#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
#	define CONFIG_SYS_PLLCR	0x1243E054
#	define CONFIG_SYS_CLK		140000000
#else
#	define CONFIG_SYS_PLLCR	0x135a4140
#	define CONFIG_SYS_CLK		70000000
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */

#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CSAR0 << 16)
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define FLASH_SST6401B		0x200
#define SST_ID_xF6401B		0x236D236D

#undef CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
/*
 * Unable to use CFI driver, due to incompatible sector erase command by SST.
 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 * 0x30 is block erase in SST
 */
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_FLASH_CFI_LEGACY
#else
#	define CONFIG_SYS_SST_SECT		2048
#	define CONFIG_SYS_SST_SECTSZ		0x1000
#	define CONFIG_SYS_FLASH_WRITE_TOUT	500
#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

/* Port configuration */
#define CONFIG_SYS_FECI2C		0xF0

#define CONFIG_SYS_CSAR0		0xFF80
#define CONFIG_SYS_CSMR0		0x007F0021
#define CONFIG_SYS_CSCR0		0x1D80

#define CONFIG_SYS_CSAR1               0xE000
#define CONFIG_SYS_CSMR1               0x00000001
#define CONFIG_SYS_CSCR1               0x3DD8

#define CONFIG_SYS_CSAR2		0
#define CONFIG_SYS_CSMR2		0
#define CONFIG_SYS_CSCR2		0

#define CONFIG_SYS_CSAR3		0
#define CONFIG_SYS_CSMR3		0
#define CONFIG_SYS_CSCR3		0

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */

#endif				/* _M5253DEMO_H */
Commit	Line	Data
6d33c6ac TL	1	/*
	2	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	3	* Hayden Fraser (Hayden.Fraser@freescale.com)
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef _M5253DEMO_H
	25	#define _M5253DEMO_H
	26
	27	#define CONFIG_MCF52x2 /* define processor family */
	28	#define CONFIG_M5253 /* define processor type */
	29	#define CONFIG_M5253DEMO /* define board type */
	30
	31	#define CONFIG_MCFTMR
	32
	33	#define CONFIG_MCFUART
6d0f6bcf	34	#define CONFIG_SYS_UART_PORT (0)
6d33c6ac	35	#define CONFIG_BAUDRATE 115200
6d0f6bcf	36	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
6d33c6ac TL	37
	38	#undef CONFIG_WATCHDOG /* disable watchdog */
	39
	40	#define CONFIG_BOOTDELAY 5
	41
	42	/* Configuration for environment
	43	* Environment is embedded in u-boot in the second sector of the flash
	44	*/
	45	#ifdef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	46	# define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	47	# define CONFIG_ENV_SECT_SIZE 0x1000
5a1aceb0	48	# define CONFIG_ENV_IS_IN_FLASH 1
6d33c6ac	49	#else
6d0f6bcf	50	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
0e8d1586	51	# define CONFIG_ENV_SECT_SIZE 0x1000
5a1aceb0	52	# define CONFIG_ENV_IS_IN_FLASH 1
6d33c6ac TL	53	#endif
	54
	55	/*
	56	* Command line configuration.
	57	*/
	58	#include <config_cmd_default.h>
	59
	60	#define CONFIG_CMD_LOADB
	61	#define CONFIG_CMD_LOADS
	62	#define CONFIG_CMD_EXT2
	63	#define CONFIG_CMD_FAT
	64	#define CONFIG_CMD_IDE
	65	#define CONFIG_CMD_MEMORY
	66	#define CONFIG_CMD_MISC
	67	#define CONFIG_CMD_PING
	68
	69	#ifdef CONFIG_CMD_IDE
	70	/* ATA */
	71	# define CONFIG_DOS_PARTITION
	72	# define CONFIG_MAC_PARTITION
	73	# define CONFIG_IDE_RESET 1
	74	# define CONFIG_IDE_PREINIT 1
	75	# define CONFIG_ATAPI
	76	# undef CONFIG_LBA48
	77
6d0f6bcf JCPV	78	# define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	79	# define CONFIG_SYS_IDE_MAXDEVICE 2
6d33c6ac	80
6d0f6bcf JCPV	81	# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
6d0f6bcf JCPV	82	# define CONFIG_SYS_ATA_IDE0_OFFSET 0
6d33c6ac	83
6d0f6bcf JCPV	84	# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	85	# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	86	# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	87	# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
6d33c6ac TL	88	# define _IO_BASE 0
	89	#endif
	90
	91	#define CONFIG_DRIVER_DM9000
	92	#ifdef CONFIG_DRIVER_DM9000
6d0f6bcf	93	# define CONFIG_DM9000_BASE ((CONFIG_SYS_CSAR1 << 16) \| 0x300)
6d33c6ac TL	94	# define DM9000_IO CONFIG_DM9000_BASE
	95	# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	96	# undef CONFIG_DM9000_DEBUG
	97
	98	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	99	# define CONFIG_IPADDR 10.82.121.249
	100	# define CONFIG_NETMASK 255.255.252.0
	101	# define CONFIG_SERVERIP 10.82.120.80
	102	# define CONFIG_GATEWAYIP 10.82.123.254
	103	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	104
	105	# define CONFIG_EXTRA_ENV_SETTINGS \
	106	"netdev=eth0\0" \
6d0f6bcf	107	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
6d33c6ac TL	108	"loadaddr=10000\0" \
	109	"u-boot=u-boot.bin\0" \
	110	"load=tftp ${loadaddr) ${u-boot}\0" \
	111	"upd=run load; run prog\0" \
	112	"prog=prot off 0 2ffff;" \
	113	"era 0 2ffff;" \
	114	"cp.b ${loadaddr} 0 ${filesize};" \
	115	"save\0" \
	116	""
	117	#endif
	118
	119	#define CONFIG_HOSTNAME M5253DEMO
	120
eec567a6 TL	121	/* I2C */
	122	#define CONFIG_FSL_I2C
	123	#define CONFIG_HARD_I2C /* I2C with hw support */
6d0f6bcf JCPV	124	#define CONFIG_SYS_I2C_SPEED 80000
	125	#define CONFIG_SYS_I2C_SLAVE 0x7F
	126	#define CONFIG_SYS_I2C_OFFSET 0x00000280
	127	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	128	#define CONFIG_SYS_I2C_PINMUX_REG ((u32 ) (CONFIG_SYS_MBAR+0x19C))
	129	#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
	130	#define CONFIG_SYS_I2C_PINMUX_SET (0)
eec567a6	131
6d0f6bcf JCPV	132	#define CONFIG_SYS_PROMPT "=> "
6d0f6bcf JCPV	133	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d33c6ac TL	134
6d33c6ac TL	135	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	136	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
6d33c6ac	137	#else
6d0f6bcf	138	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6d33c6ac	139	#endif
6d0f6bcf JCPV	140	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	141	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	142	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
6d33c6ac	143
6d0f6bcf	144	#define CONFIG_SYS_LOAD_ADDR 0x00100000
6d33c6ac	145
6d0f6bcf JCPV	146	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	147	#define CONFIG_SYS_MEMTEST_END 0x380000
6d33c6ac	148
6d0f6bcf	149	#define CONFIG_SYS_HZ 1000
6d33c6ac	150
6d0f6bcf JCPV	151	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	152	#define CONFIG_SYS_FAST_CLK
	153	#ifdef CONFIG_SYS_FAST_CLK
	154	# define CONFIG_SYS_PLLCR 0x1243E054
	155	# define CONFIG_SYS_CLK 140000000
6d33c6ac	156	#else
6d0f6bcf JCPV	157	# define CONFIG_SYS_PLLCR 0x135a4140
6d0f6bcf JCPV	158	# define CONFIG_SYS_CLK 70000000
6d33c6ac TL	159	#endif
	160
	161	/*
	162	* Low Level Configuration Settings
	163	* (address mappings, register initial values, etc.)
	164	* You should know what you are doing if you make changes here.
	165	*/
	166
6d0f6bcf JCPV	167	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	168	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
6d33c6ac TL	169
	170	/*
	171	* Definitions for initial stack pointer and data area (in DPRAM)
	172	*/
6d0f6bcf JCPV	173	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
	174	#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
	175	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	176	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	177	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6d33c6ac TL	178
	179	/*
	180	* Start addresses for the final memory configuration
	181	* (Set up by the startup code)
6d0f6bcf	182	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
6d33c6ac	183	*/
6d0f6bcf JCPV	184	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	185	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
6d33c6ac TL	186
6d33c6ac TL	187	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	188	# define CONFIG_SYS_MONITOR_BASE 0x20000
6d33c6ac	189	#else
6d0f6bcf	190	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d33c6ac TL	191	#endif
6d33c6ac TL	192
6d0f6bcf JCPV	193	#define CONFIG_SYS_MONITOR_LEN 0x40000
	194	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	195	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
6d33c6ac TL	196
	197	/*
	198	* For booting Linux, the board info and command line data
	199	* have to be in the first 8 MB of memory, since this is
	200	* the maximum mapped by the Linux kernel during initialization ??
	201	*/
6d0f6bcf	202	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
6d33c6ac TL	203
6d33c6ac TL	204	/* FLASH organization */
6d0f6bcf JCPV	205	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CSAR0 << 16)
	206	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	207	#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
	208	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
6d33c6ac TL	209
	210	#define FLASH_SST6401B 0x200
	211	#define SST_ID_xF6401B 0x236D236D
	212
6d0f6bcf JCPV	213	#undef CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	214	#ifdef CONFIG_SYS_FLASH_CFI
6d33c6ac TL	215	/*
	216	* Unable to use CFI driver, due to incompatible sector erase command by SST.
	217	* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
	218	* 0x30 is block erase in SST
	219	*/
0de0afbc	220	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	221	# define CONFIG_SYS_FLASH_SIZE 0x800000
6d0f6bcf JCPV	222	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
6d33c6ac TL	223	# define CONFIG_FLASH_CFI_LEGACY
6d33c6ac TL	224	#else
6d0f6bcf JCPV	225	# define CONFIG_SYS_SST_SECT 2048
	226	# define CONFIG_SYS_SST_SECTSZ 0x1000
	227	# define CONFIG_SYS_FLASH_WRITE_TOUT 500
6d33c6ac TL	228	#endif
	229
	230	/* Cache Configuration */
6d0f6bcf	231	#define CONFIG_SYS_CACHELINE_SIZE 16
6d33c6ac TL	232
6d33c6ac TL	233	/* Port configuration */
6d0f6bcf	234	#define CONFIG_SYS_FECI2C 0xF0
6d33c6ac	235
6d0f6bcf JCPV	236	#define CONFIG_SYS_CSAR0 0xFF80
	237	#define CONFIG_SYS_CSMR0 0x007F0021
	238	#define CONFIG_SYS_CSCR0 0x1D80
6d33c6ac	239
6d0f6bcf JCPV	240	#define CONFIG_SYS_CSAR1 0xE000
	241	#define CONFIG_SYS_CSMR1 0x00000001
	242	#define CONFIG_SYS_CSCR1 0x3DD8
6d33c6ac	243
6d0f6bcf JCPV	244	#define CONFIG_SYS_CSAR2 0
	245	#define CONFIG_SYS_CSMR2 0
	246	#define CONFIG_SYS_CSCR2 0
6d33c6ac	247
6d0f6bcf JCPV	248	#define CONFIG_SYS_CSAR3 0
	249	#define CONFIG_SYS_CSMR3 0
	250	#define CONFIG_SYS_CSCR3 0
6d33c6ac TL	251
	252	/*-----------------------------------------------------------------------
	253	* Port configuration
	254	*/
6d0f6bcf JCPV	255	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	256	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
	257	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	258	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	259	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	260	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	261	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
6d33c6ac TL	262
6d33c6ac TL	263	#endif /* _M5253DEMO_H */