[people/ms/u-boot.git] / include / configs / M5253EVBE.h

/*
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * Hayden Fraser (Hayden.Fraser@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _M5253EVBE_H
#define _M5253EVBE_H

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG		/* disable watchdog */


/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#endif

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text)

/*
 * BOOTP options
 */
#undef CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

/* ATA */
#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT	1
#define CONFIG_ATAPI
#undef CONFIG_LBA48

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2

#define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
#define CONFIG_SYS_ATA_IDE0_OFFSET	0

#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
#	define CONFIG_SYS_PLLCR	0x1243E054
#	define CONFIG_SYS_CLK		140000000
#else
#	define CONFIG_SYS_PLLCR	0x135a4140
#	define CONFIG_SYS_CLK		70000000
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		8	/* SDRAM size in MB */

#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_SIZE		0x200000
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
					 CF_ADDRMASK(2) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/* Port configuration */
#define CONFIG_SYS_FECI2C		0xF0

#define CONFIG_SYS_CS0_BASE		0xFFE00000
#define CONFIG_SYS_CS0_MASK		0x001F0021
#define CONFIG_SYS_CS0_CTRL		0x00001D80

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */

#endif				/* _M5253EVB_H */
Commit	Line	Data
a1436a84 TL	1	/*
	2	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	3	* Hayden Fraser (Hayden.Fraser@freescale.com)
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
a1436a84 TL	6	*/
	7
	8	#ifndef _M5253EVBE_H
	9	#define _M5253EVBE_H
	10
a1436a84 TL	11	#define CONFIG_MCFTMR
	12
	13	#define CONFIG_MCFUART
6d0f6bcf	14	#define CONFIG_SYS_UART_PORT (0)
a1436a84 TL	15
	16	#undef CONFIG_WATCHDOG /* disable watchdog */
	17
a1436a84 TL	18
	19	/* Configuration for environment
	20	* Environment is embedded in u-boot in the second sector of the flash
	21	*/
	22	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	23	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	24	#define CONFIG_ENV_SECT_SIZE 0x2000
a1436a84	25	#else
0e8d1586 JCPV	26	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	27	#define CONFIG_ENV_SECT_SIZE 0x2000
a1436a84 TL	28	#endif
a1436a84 TL	29
5296cb1d	30	#define LDS_BOARD_TEXT \
5296cb1d	31	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d	32	env/embedded.o(.text)
5296cb1d	33
a1436a84 TL	34	/*
	35	* BOOTP options
	36	*/
	37	#undef CONFIG_BOOTP_BOOTFILESIZE
a1436a84 TL	38
	39	/*
	40	* Command line configuration.
	41	*/
a1436a84 TL	42
a1436a84 TL	43	/* ATA */
a1436a84 TL	44	#define CONFIG_IDE_RESET 1
	45	#define CONFIG_IDE_PREINIT 1
	46	#define CONFIG_ATAPI
	47	#undef CONFIG_LBA48
	48
6d0f6bcf JCPV	49	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	50	#define CONFIG_SYS_IDE_MAXDEVICE 2
a1436a84	51
6d0f6bcf JCPV	52	#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
6d0f6bcf JCPV	53	#define CONFIG_SYS_ATA_IDE0_OFFSET 0
a1436a84	54
6d0f6bcf JCPV	55	#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	56	#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	57	#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	58	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
a1436a84	59
6d0f6bcf	60	#define CONFIG_SYS_LOAD_ADDR 0x00100000
a1436a84	61
6d0f6bcf JCPV	62	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	63	#define CONFIG_SYS_MEMTEST_END 0x380000
a1436a84	64
6d0f6bcf JCPV	65	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	66	#define CONFIG_SYS_FAST_CLK
	67	#ifdef CONFIG_SYS_FAST_CLK
	68	# define CONFIG_SYS_PLLCR 0x1243E054
	69	# define CONFIG_SYS_CLK 140000000
a1436a84	70	#else
6d0f6bcf JCPV	71	# define CONFIG_SYS_PLLCR 0x135a4140
6d0f6bcf JCPV	72	# define CONFIG_SYS_CLK 70000000
a1436a84 TL	73	#endif
	74
	75	/*
	76	* Low Level Configuration Settings
	77	* (address mappings, register initial values, etc.)
	78	* You should know what you are doing if you make changes here.
	79	*/
	80
6d0f6bcf JCPV	81	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	82	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
a1436a84 TL	83
	84	/*
	85	* Definitions for initial stack pointer and data area (in DPRAM)
	86	*/
6d0f6bcf	87	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	88	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	89	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	90	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
a1436a84 TL	91
	92	/*
	93	* Start addresses for the final memory configuration
	94	* (Set up by the startup code)
6d0f6bcf	95	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
a1436a84	96	*/
6d0f6bcf JCPV	97	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	98	#define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
a1436a84 TL	99
a1436a84 TL	100	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	101	#define CONFIG_SYS_MONITOR_BASE 0x20000
a1436a84	102	#else
6d0f6bcf	103	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
a1436a84 TL	104	#endif
a1436a84 TL	105
6d0f6bcf JCPV	106	#define CONFIG_SYS_MONITOR_LEN 0x40000
	107	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	108	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
a1436a84 TL	109
	110	/*
	111	* For booting Linux, the board info and command line data
	112	* have to be in the first 8 MB of memory, since this is
	113	* the maximum mapped by the Linux kernel during initialization ??
	114	*/
6d0f6bcf	115	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	116	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
a1436a84 TL	117
a1436a84 TL	118	/* FLASH organization */
012522fe	119	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
6d0f6bcf JCPV	120	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	121	#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
	122	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
a1436a84	123
6d0f6bcf	124	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	125	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	126	#define CONFIG_SYS_FLASH_SIZE 0x200000
6d0f6bcf JCPV	127	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
a1436a84 TL	128
a1436a84 TL	129	/* Cache Configuration */
6d0f6bcf	130	#define CONFIG_SYS_CACHELINE_SIZE 16
a1436a84	131
dd9f054e	132	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	133	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	134	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	135	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	136	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	137	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
	138	CF_ADDRMASK(2) \| \
	139	CF_ACR_EN \| CF_ACR_SM_ALL)
	140	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	141	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	142	CF_ACR_EN \| CF_ACR_SM_ALL)
	143	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	144	CF_CACR_DBWE)
	145
a1436a84	146	/* Port configuration */
6d0f6bcf	147	#define CONFIG_SYS_FECI2C 0xF0
a1436a84	148
012522fe TL	149	#define CONFIG_SYS_CS0_BASE 0xFFE00000
	150	#define CONFIG_SYS_CS0_MASK 0x001F0021
	151	#define CONFIG_SYS_CS0_CTRL 0x00001D80
a1436a84 TL	152
	153	/*-----------------------------------------------------------------------
	154	* Port configuration
	155	*/
6d0f6bcf JCPV	156	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	157	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
	158	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	159	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	160	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	161	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	162	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
a1436a84 TL	163
a1436a84 TL	164	#endif /* _M5253EVB_H */