]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/M5275EVB.h
m68k: Drop unreferenced CONFIG_* defines
[people/ms/u-boot.git] / include / configs / M5275EVB.h
CommitLineData
545c8e0a
MF
1/*
2 * Configuation settings for the Motorola MC5275EVB board.
3 *
4 * By Arthur Shipkowski <art@videon-central.com>
5 * Copyright (C) 2005 Videon Central, Inc.
6 *
7 * Based off of M5272C3 board code by Josef Baumgartner
8 * <josef.baumgartner@telex.de>
9 *
3765b3e7 10 * SPDX-License-Identifier: GPL-2.0+
545c8e0a
MF
11 */
12
13/*
14 * board/config.h - configuration options, board specific
15 */
16
17#ifndef _M5275EVB_H
18#define _M5275EVB_H
19
20/*
21 * High Level Configuration Options
22 * (easy to change)
23 */
545c8e0a
MF
24
25#define CONFIG_MCFTMR
26
27#define CONFIG_MCFUART
6d0f6bcf 28#define CONFIG_SYS_UART_PORT (0)
545c8e0a
MF
29
30/* Configuration for environment
31 * Environment is embedded in u-boot in the second sector of the flash
32 */
33#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586
JCPV
34#define CONFIG_ENV_OFFSET 0x4000
35#define CONFIG_ENV_SECT_SIZE 0x2000
545c8e0a 36#else
0e8d1586
JCPV
37#define CONFIG_ENV_ADDR 0xffe04000
38#define CONFIG_ENV_SECT_SIZE 0x2000
545c8e0a
MF
39#endif
40
5296cb1d 41#define LDS_BOARD_TEXT \
0649cd0d
SG
42 . = DEFINED(env_offset) ? env_offset : .; \
43 env/embedded.o(.text);
5296cb1d 44
545c8e0a
MF
45/*
46 * BOOTP options
47 */
48#define CONFIG_BOOTP_BOOTFILESIZE
49#define CONFIG_BOOTP_BOOTPATH
50#define CONFIG_BOOTP_GATEWAY
51#define CONFIG_BOOTP_HOSTNAME
52
53/* Available command configuration */
545c8e0a 54
545c8e0a
MF
55#define CONFIG_MCFFEC
56#ifdef CONFIG_MCFFEC
545c8e0a 57#define CONFIG_MII 1
0f3ba7e9 58#define CONFIG_MII_INIT 1
6d0f6bcf
JCPV
59#define CONFIG_SYS_DISCOVER_PHY
60#define CONFIG_SYS_RX_ETH_BUFFER 8
61#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
62#define CONFIG_SYS_FEC0_PINMUX 0
63#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
64#define CONFIG_SYS_FEC1_PINMUX 0
65#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
545c8e0a
MF
66#define MCFFEC_TOUT_LOOP 50000
67#define CONFIG_HAS_ETH1
6d0f6bcf
JCPV
68/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
69#ifndef CONFIG_SYS_DISCOVER_PHY
545c8e0a
MF
70#define FECDUPLEX FULL
71#define FECSPEED _100BASET
72#else
6d0f6bcf
JCPV
73#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
74#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
545c8e0a
MF
75#endif
76#endif
77#endif
78
79/* I2C */
00f792e0
HS
80#define CONFIG_SYS_I2C
81#define CONFIG_SYS_I2C_FSL
82#define CONFIG_SYS_FSL_I2C_SPEED 80000
83#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
84#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
6d0f6bcf
JCPV
85#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
86#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
87#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0)
88#define CONFIG_SYS_I2C_PINMUX_SET (0x000F)
545c8e0a 89
6d0f6bcf 90#define CONFIG_SYS_LONGHELP /* undef to save memory */
545c8e0a 91
6d0f6bcf 92#define CONFIG_SYS_LOAD_ADDR 0x800000
545c8e0a 93
545c8e0a 94#define CONFIG_BOOTCOMMAND "bootm ffe40000"
6d0f6bcf
JCPV
95#define CONFIG_SYS_MEMTEST_START 0x400
96#define CONFIG_SYS_MEMTEST_END 0x380000
545c8e0a 97
0e8a7555
TL
98#ifdef CONFIG_MCFFEC
99# define CONFIG_NET_RETRY_COUNT 5
100# define CONFIG_OVERWRITE_ETHADDR_ONCE
101#endif /* FEC_ENET */
102
103#define CONFIG_EXTRA_ENV_SETTINGS \
104 "netdev=eth0\0" \
105 "loadaddr=10000\0" \
106 "uboot=u-boot.bin\0" \
107 "load=tftp ${loadaddr} ${uboot}\0" \
108 "upd=run load; run prog\0" \
109 "prog=prot off ffe00000 ffe3ffff;" \
110 "era ffe00000 ffe3ffff;" \
111 "cp.b ${loadaddr} ffe00000 ${filesize};"\
112 "save\0" \
113 ""
114
6d0f6bcf 115#define CONFIG_SYS_CLK 150000000
545c8e0a
MF
116
117/*
118 * Low Level Configuration Settings
119 * (address mappings, register initial values, etc.)
120 * You should know what you are doing if you make changes here.
121 */
122
6d0f6bcf 123#define CONFIG_SYS_MBAR 0x40000000
545c8e0a
MF
124
125/*-----------------------------------------------------------------------
126 * Definitions for initial stack pointer and data area (in DPRAM)
127 */
6d0f6bcf 128#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982 129#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb 130#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 131#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
545c8e0a
MF
132
133/*-----------------------------------------------------------------------
134 * Start addresses for the final memory configuration
135 * (Set up by the startup code)
6d0f6bcf 136 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
545c8e0a 137 */
6d0f6bcf
JCPV
138#define CONFIG_SYS_SDRAM_BASE 0x00000000
139#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
012522fe 140#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
545c8e0a
MF
141
142#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf 143#define CONFIG_SYS_MONITOR_BASE 0x20000
545c8e0a 144#else
6d0f6bcf 145#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
545c8e0a
MF
146#endif
147
6d0f6bcf
JCPV
148#define CONFIG_SYS_MONITOR_LEN 0x20000
149#define CONFIG_SYS_MALLOC_LEN (256 << 10)
150#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
545c8e0a
MF
151
152/*
153 * For booting Linux, the board info and command line data
154 * have to be in the first 8 MB of memory, since this is
155 * the maximum mapped by the Linux kernel during initialization ??
156 */
d6e4baf4
TL
157#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
158#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
545c8e0a
MF
159
160/*-----------------------------------------------------------------------
161 * FLASH organization
162 */
6d0f6bcf
JCPV
163#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
164#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
165#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
545c8e0a 166
6d0f6bcf 167#define CONFIG_SYS_FLASH_CFI 1
00b1883a 168#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf 169#define CONFIG_SYS_FLASH_SIZE 0x200000
545c8e0a
MF
170
171/*-----------------------------------------------------------------------
172 * Cache Configuration
173 */
6d0f6bcf 174#define CONFIG_SYS_CACHELINE_SIZE 16
545c8e0a 175
dd9f054e 176#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982 177 CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e 178#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982 179 CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e
TL
180#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
181#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
182 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
183 CF_ACR_EN | CF_ACR_SM_ALL)
184#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
185 CF_CACR_DISD | CF_CACR_INVI | \
186 CF_CACR_CEIB | CF_CACR_DCM | \
187 CF_CACR_EUSP)
188
545c8e0a
MF
189/*-----------------------------------------------------------------------
190 * Memory bank definitions
191 */
012522fe
TL
192#define CONFIG_SYS_CS0_BASE 0xffe00000
193#define CONFIG_SYS_CS0_CTRL 0x00001980
194#define CONFIG_SYS_CS0_MASK 0x001F0001
545c8e0a 195
012522fe
TL
196#define CONFIG_SYS_CS1_BASE 0x30000000
197#define CONFIG_SYS_CS1_CTRL 0x00001900
198#define CONFIG_SYS_CS1_MASK 0x00070001
545c8e0a
MF
199
200/*-----------------------------------------------------------------------
201 * Port configuration
202 */
6d0f6bcf 203#define CONFIG_SYS_FECI2C 0x0FA0
545c8e0a
MF
204
205#endif /* _M5275EVB_H */