[people/ms/u-boot.git] / include / configs / M53017EVB.h

/*
 * Configuation settings for the Freescale MCF53017EVB.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M53017EVB_H
#define _M53017EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT		5000

#define CONFIG_SYS_UNIFY_CACHE

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_TX_ETH_BUFFER	8
#	define CONFIG_SYS_FEC_BUF_USE_SRAM
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#	define CONFIG_HAS_ETH1

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_PINMUX	0
#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC1_IOBASE
#	define MCFFEC_TOUT_LOOP		50000

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_CNT		(0x8000)
#define CONFIG_SYS_RTC_SETUP		(RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

#define CONFIG_UDP_CHECKSUM

#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M53017
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 3ffff;"		\
	"era 0 3ffff;"				\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */
#define CONFIG_SYS_LONGHELP	/* undef to save memory */

#ifdef CONFIG_CMD_KGDB
#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Arg Buf Sz */
#define CONFIG_SYS_LOAD_ADDR	0x40010000

#define CONFIG_SYS_CLK		80000000
#define CONFIG_SYS_CPU_CLK	CONFIG_SYS_CLK * 3

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x20000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x80010000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER		1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_FLASH_SPANSION_S29WS_N	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_OFFSET		(CONFIG_SYS_FLASH_BASE + 0x40000)
#define CONFIG_ENV_SIZE			0x1000
#define CONFIG_ENV_SECT_SIZE		0x8000

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o       (.text*)

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
					 CF_CACR_DCM_P)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash
 * CS1 - Ext SRAM
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0

#define CONFIG_SYS_CS1_BASE		0xC0000000
#define CONFIG_SYS_CS1_MASK		0x00070001
#define CONFIG_SYS_CS1_CTRL		0x00001FA0

#endif				/* _M53017EVB_H */
Commit	Line	Data
536e7dac TL	1	/*
	2	* Configuation settings for the Freescale MCF53017EVB.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
536e7dac TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M53017EVB_H
	15	#define _M53017EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
536e7dac TL	21
	22	#define CONFIG_MCFUART
	23	#define CONFIG_SYS_UART_PORT (0)
536e7dac TL	24
	25	#undef CONFIG_WATCHDOG
	26	#define CONFIG_WATCHDOG_TIMEOUT 5000
	27
536e7dac TL	28	#define CONFIG_SYS_UNIFY_CACHE
	29
	30	#define CONFIG_MCFFEC
	31	#ifdef CONFIG_MCFFEC
536e7dac TL	32	# define CONFIG_MII 1
	33	# define CONFIG_MII_INIT 1
	34	# define CONFIG_SYS_DISCOVER_PHY
	35	# define CONFIG_SYS_RX_ETH_BUFFER 8
9e8e9270 TL	36	# define CONFIG_SYS_TX_ETH_BUFFER 8
9e8e9270 TL	37	# define CONFIG_SYS_FEC_BUF_USE_SRAM
536e7dac TL	38	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	39	# define CONFIG_HAS_ETH1
	40
	41	# define CONFIG_SYS_FEC0_PINMUX 0
	42	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	43	# define CONFIG_SYS_FEC1_PINMUX 0
	44	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE
	45	# define MCFFEC_TOUT_LOOP 50000
052c0891	46
536e7dac TL	47	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
	48	# ifndef CONFIG_SYS_DISCOVER_PHY
	49	# define FECDUPLEX FULL
	50	# define FECSPEED _100BASET
	51	# else
	52	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	53	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	54	# endif
	55	# endif /* CONFIG_SYS_DISCOVER_PHY */
	56	#endif
	57
	58	#define CONFIG_MCFRTC
	59	#undef RTC_DEBUG
	60	#define CONFIG_SYS_RTC_CNT (0x8000)
	61	#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP \| RTC_OCEN_CLKEN)
	62
	63	/* Timer */
	64	#define CONFIG_MCFTMR
	65	#undef CONFIG_MCFPIT
	66
	67	/* I2C */
00f792e0 HS	68	#define CONFIG_SYS_I2C
	69	#define CONFIG_SYS_I2C_FSL
	70	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	71	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	72	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
536e7dac TL	73	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
536e7dac TL	74
536e7dac TL	75	#define CONFIG_UDP_CHECKSUM
	76
	77	#ifdef CONFIG_MCFFEC
536e7dac TL	78	# define CONFIG_IPADDR 192.162.1.2
	79	# define CONFIG_NETMASK 255.255.255.0
	80	# define CONFIG_SERVERIP 192.162.1.1
	81	# define CONFIG_GATEWAYIP 192.162.1.1
536e7dac TL	82	#endif /* FEC_ENET */
	83
	84	#define CONFIG_HOSTNAME M53017
	85	#define CONFIG_EXTRA_ENV_SETTINGS \
	86	"netdev=eth0\0" \
	87	"loadaddr=40010000\0" \
	88	"u-boot=u-boot.bin\0" \
	89	"load=tftp ${loadaddr) ${u-boot}\0" \
	90	"upd=run load; run prog\0" \
	91	"prog=prot off 0 3ffff;" \
	92	"era 0 3ffff;" \
	93	"cp.b ${loadaddr} 0 ${filesize};" \
	94	"save\0" \
	95	""
	96
	97	#define CONFIG_PRAM 512 /* 512 KB */
536e7dac TL	98	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	99
	100	#ifdef CONFIG_CMD_KGDB
	101	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	102	#else
	103	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	104	#endif
	105
	106	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	107	#define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */
	108	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */
	109	#define CONFIG_SYS_LOAD_ADDR 0x40010000
	110
536e7dac TL	111	#define CONFIG_SYS_CLK 80000000
	112	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
	113
	114	#define CONFIG_SYS_MBAR 0xFC000000
	115
	116	/*
	117	* Low Level Configuration Settings
	118	* (address mappings, register initial values, etc.)
	119	* You should know what you are doing if you make changes here.
	120	*/
	121	/*
	122	* Definitions for initial stack pointer and data area (in DPRAM)
	123	*/
	124	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	125	#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */
9e8e9270	126	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	127	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
536e7dac TL	128	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	129
	130	/*
	131	* Start addresses for the final memory configuration
	132	* (Set up by the startup code)
	133	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
	134	*/
	135	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	136	#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
	137	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	138	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
9e8e9270	139	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
536e7dac TL	140	#define CONFIG_SYS_SDRAM_EMOD 0x80010000
	141	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
	142
	143	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	144	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	145
	146	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	147	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	148
	149	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	150	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	151
	152	/*
	153	* For booting Linux, the board info and command line data
	154	* have to be in the first 8 MB of memory, since this is
	155	* the maximum mapped by the Linux kernel during initialization ??
	156	*/
	157	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	158	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
536e7dac TL	159
	160	/*-----------------------------------------------------------------------
	161	* FLASH organization
	162	*/
	163	#define CONFIG_SYS_FLASH_CFI
	164	#ifdef CONFIG_SYS_FLASH_CFI
	165	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff TL	166	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
bbf6bbff TL	167	# define CONFIG_FLASH_SPANSION_S29WS_N 1
4567c7bf	168	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
536e7dac TL	169	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	170	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	171	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	172	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	173	#endif
	174
	175	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	176
	177	/* Configuration for environment
	178	* Environment is embedded in u-boot in the second sector of the flash
	179	*/
944ab340	180	#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000)
536e7dac TL	181	#define CONFIG_ENV_SIZE 0x1000
536e7dac TL	182	#define CONFIG_ENV_SECT_SIZE 0x8000
536e7dac	183
5296cb1d	184	#define LDS_BOARD_TEXT \
	185	. = DEFINED(env_offset) ? env_offset : .; \
	186	common/env_embedded.o (.text*)
	187
536e7dac TL	188	/*-----------------------------------------------------------------------
	189	* Cache Configuration
	190	*/
	191	#define CONFIG_SYS_CACHELINE_SIZE 16
	192
dd9f054e	193	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	194	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	195	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	196	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	197	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
	198	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	199	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	200	CF_ACR_EN \| CF_ACR_SM_ALL)
	201	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC \| CF_CACR_CINVA \| \
	202	CF_CACR_DCM_P)
	203
536e7dac TL	204	/*-----------------------------------------------------------------------
	205	* Chipselect bank definitions
	206	*/
	207	/*
	208	* CS0 - NOR Flash
	209	* CS1 - Ext SRAM
	210	* CS2 - Available
	211	* CS3 - Available
	212	* CS4 - Available
	213	* CS5 - Available
	214	*/
	215	#define CONFIG_SYS_CS0_BASE 0
	216	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	217	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	218
	219	#define CONFIG_SYS_CS1_BASE 0xC0000000
	220	#define CONFIG_SYS_CS1_MASK 0x00070001
	221	#define CONFIG_SYS_CS1_CTRL 0x00001FA0
	222
	223	#endif /* _M53017EVB_H */