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05316f8e TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF54451 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
05316f8e TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M54451EVB_H | |
15 | #define _M54451EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
05316f8e TL |
21 | #define CONFIG_M54451EVB /* M54451EVB board */ |
22 | ||
23 | #define CONFIG_MCFUART | |
6d0f6bcf | 24 | #define CONFIG_SYS_UART_PORT (0) |
05316f8e | 25 | |
c74dda8b AD |
26 | #define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*) |
27 | ||
05316f8e TL |
28 | #undef CONFIG_WATCHDOG |
29 | ||
30 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
31 | ||
32 | /* | |
33 | * BOOTP options | |
34 | */ | |
35 | #define CONFIG_BOOTP_BOOTFILESIZE | |
36 | #define CONFIG_BOOTP_BOOTPATH | |
37 | #define CONFIG_BOOTP_GATEWAY | |
38 | #define CONFIG_BOOTP_HOSTNAME | |
39 | ||
05316f8e TL |
40 | /* Network configuration */ |
41 | #define CONFIG_MCFFEC | |
42 | #ifdef CONFIG_MCFFEC | |
05316f8e TL |
43 | # define CONFIG_MII 1 |
44 | # define CONFIG_MII_INIT 1 | |
6d0f6bcf JCPV |
45 | # define CONFIG_SYS_DISCOVER_PHY |
46 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
47 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
05316f8e | 48 | |
6d0f6bcf JCPV |
49 | # define CONFIG_SYS_FEC0_PINMUX 0 |
50 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
05316f8e TL |
51 | # define MCFFEC_TOUT_LOOP 50000 |
52 | ||
05316f8e TL |
53 | # define CONFIG_ETHPRIME "FEC0" |
54 | # define CONFIG_IPADDR 192.162.1.2 | |
55 | # define CONFIG_NETMASK 255.255.255.0 | |
56 | # define CONFIG_SERVERIP 192.162.1.1 | |
57 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
05316f8e | 58 | |
6d0f6bcf JCPV |
59 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
60 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
05316f8e TL |
61 | # define FECDUPLEX FULL |
62 | # define FECSPEED _100BASET | |
63 | # else | |
6d0f6bcf JCPV |
64 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
65 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
05316f8e | 66 | # endif |
6d0f6bcf | 67 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
05316f8e TL |
68 | #endif |
69 | ||
70 | #define CONFIG_HOSTNAME M54451EVB | |
6d0f6bcf | 71 | #ifdef CONFIG_SYS_STMICRO_BOOT |
05316f8e | 72 | /* ST Micro serial flash */ |
6d0f6bcf | 73 | #define CONFIG_SYS_LOAD_ADDR2 0x40010007 |
05316f8e TL |
74 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
75 | "netdev=eth0\0" \ | |
5368c55d | 76 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
05316f8e TL |
77 | "loadaddr=0x40010000\0" \ |
78 | "sbfhdr=sbfhdr.bin\0" \ | |
79 | "uboot=u-boot.bin\0" \ | |
80 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
5368c55d | 81 | "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ |
05316f8e | 82 | "upd=run load; run prog\0" \ |
09933fb0 | 83 | "prog=sf probe 0:1 1000000 3;" \ |
05316f8e TL |
84 | "sf erase 0 30000;" \ |
85 | "sf write ${loadaddr} 0 30000;" \ | |
86 | "save\0" \ | |
87 | "" | |
88 | #else | |
6d0f6bcf | 89 | #define CONFIG_SYS_UBOOT_END 0x3FFFF |
05316f8e TL |
90 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
91 | "netdev=eth0\0" \ | |
5368c55d | 92 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ |
05316f8e TL |
93 | "loadaddr=40010000\0" \ |
94 | "u-boot=u-boot.bin\0" \ | |
95 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
96 | "upd=run load; run prog\0" \ | |
5368c55d MV |
97 | "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ |
98 | "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ | |
05316f8e TL |
99 | "cp.b ${loadaddr} 0 ${filesize};" \ |
100 | "save\0" \ | |
101 | "" | |
102 | #endif | |
103 | ||
104 | /* Realtime clock */ | |
105 | #define CONFIG_MCFRTC | |
106 | #undef RTC_DEBUG | |
6d0f6bcf | 107 | #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) |
05316f8e TL |
108 | |
109 | /* Timer */ | |
110 | #define CONFIG_MCFTMR | |
111 | #undef CONFIG_MCFPIT | |
112 | ||
113 | /* I2c */ | |
00f792e0 HS |
114 | #define CONFIG_SYS_I2C |
115 | #define CONFIG_SYS_I2C_FSL | |
116 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
117 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
118 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
709b384b | 119 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
05316f8e TL |
120 | |
121 | /* DSPI and Serial Flash */ | |
ee0a8462 | 122 | #define CONFIG_CF_SPI |
05316f8e TL |
123 | #define CONFIG_CF_DSPI |
124 | #define CONFIG_SERIAL_FLASH | |
125 | #define CONFIG_HARD_SPI | |
6d0f6bcf | 126 | #define CONFIG_SYS_SBFHDR_SIZE 0x7 |
05316f8e | 127 | #ifdef CONFIG_CMD_SPI |
05316f8e | 128 | |
ee0a8462 TL |
129 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ |
130 | DSPI_CTAR_PCSSCK_1CLK | \ | |
131 | DSPI_CTAR_PASC(0) | \ | |
132 | DSPI_CTAR_PDT(0) | \ | |
133 | DSPI_CTAR_CSSCK(0) | \ | |
134 | DSPI_CTAR_ASC(0) | \ | |
135 | DSPI_CTAR_DT(1)) | |
136 | # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) | |
137 | # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) | |
05316f8e TL |
138 | #endif |
139 | ||
140 | /* Input, PCI, Flexbus, and VCO */ | |
141 | #define CONFIG_EXTRA_CLOCK | |
142 | ||
709b384b | 143 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
05316f8e | 144 | |
6d0f6bcf | 145 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
05316f8e | 146 | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
148 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
05316f8e | 149 | |
6d0f6bcf | 150 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
05316f8e | 151 | |
709b384b | 152 | #define CONFIG_SYS_MBAR 0xFC000000 |
05316f8e TL |
153 | |
154 | /* | |
155 | * Low Level Configuration Settings | |
156 | * (address mappings, register initial values, etc.) | |
157 | * You should know what you are doing if you make changes here. | |
158 | */ | |
159 | ||
160 | /*----------------------------------------------------------------------- | |
161 | * Definitions for initial stack pointer and data area (in DPRAM) | |
162 | */ | |
6d0f6bcf | 163 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 164 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 165 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 166 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) |
6d0f6bcf | 167 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
553f0982 | 168 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
05316f8e TL |
169 | |
170 | /*----------------------------------------------------------------------- | |
171 | * Start addresses for the final memory configuration | |
172 | * (Set up by the startup code) | |
6d0f6bcf | 173 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
05316f8e | 174 | */ |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
176 | #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ | |
177 | #define CONFIG_SYS_SDRAM_CFG1 0x33633F30 | |
178 | #define CONFIG_SYS_SDRAM_CFG2 0x57670000 | |
179 | #define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 | |
180 | #define CONFIG_SYS_SDRAM_EMOD 0x80810000 | |
181 | #define CONFIG_SYS_SDRAM_MODE 0x008D0000 | |
182 | #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 | |
183 | ||
184 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 | |
185 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
05316f8e TL |
186 | |
187 | #ifdef CONFIG_CF_SBF | |
09933fb0 | 188 | # define CONFIG_SERIAL_BOOT |
14d0a02a | 189 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
05316f8e | 190 | #else |
6d0f6bcf | 191 | # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
05316f8e | 192 | #endif |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
194 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
05316f8e | 195 | |
09933fb0 JJ |
196 | /* Reserve 256 kB for malloc() */ |
197 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
05316f8e TL |
198 | /* |
199 | * For booting Linux, the board info and command line data | |
200 | * have to be in the first 8 MB of memory, since this is | |
201 | * the maximum mapped by the Linux kernel during initialization ?? | |
202 | */ | |
203 | /* Initial Memory map for Linux */ | |
6d0f6bcf | 204 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
05316f8e TL |
205 | |
206 | /* Configuration for environment | |
09933fb0 JJ |
207 | * Environment is not embedded in u-boot. First time runing may have env |
208 | * crc error warning if there is no correct environment on the flash. | |
05316f8e | 209 | */ |
709b384b | 210 | #if defined(CONFIG_SYS_STMICRO_BOOT) |
0e8d1586 JCPV |
211 | # define CONFIG_ENV_SPI_CS 1 |
212 | # define CONFIG_ENV_OFFSET 0x20000 | |
213 | # define CONFIG_ENV_SIZE 0x2000 | |
214 | # define CONFIG_ENV_SECT_SIZE 0x10000 | |
05316f8e | 215 | #else |
09933fb0 | 216 | # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) |
709b384b | 217 | # define CONFIG_ENV_SIZE 0x2000 |
09933fb0 | 218 | # define CONFIG_ENV_SECT_SIZE 0x20000 |
05316f8e TL |
219 | #endif |
220 | #undef CONFIG_ENV_OVERWRITE | |
05316f8e | 221 | |
ee0a8462 TL |
222 | /* FLASH organization */ |
223 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
05316f8e | 224 | |
6d0f6bcf JCPV |
225 | #define CONFIG_SYS_FLASH_CFI |
226 | #ifdef CONFIG_SYS_FLASH_CFI | |
05316f8e TL |
227 | |
228 | # define CONFIG_FLASH_CFI_DRIVER 1 | |
709b384b | 229 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 |
6d0f6bcf JCPV |
230 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
231 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
232 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
233 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
234 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
235 | # define CONFIG_SYS_FLASH_CHECKSUM | |
236 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } | |
05316f8e TL |
237 | |
238 | #endif | |
239 | ||
240 | /* | |
241 | * This is setting for JFFS2 support in u-boot. | |
242 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
243 | */ | |
709b384b | 244 | #ifdef CONFIG_CMD_JFFS2 |
05316f8e TL |
245 | # define CONFIG_JFFS2_DEV "nor0" |
246 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 | |
6d0f6bcf | 247 | # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) |
05316f8e TL |
248 | #endif |
249 | ||
709b384b | 250 | /* Cache Configuration */ |
6d0f6bcf | 251 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
05316f8e | 252 | |
dd9f054e | 253 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 254 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 255 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 256 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
257 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) |
258 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
259 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
260 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
261 | CF_ACR_EN | CF_ACR_SM_ALL) | |
262 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ | |
263 | CF_CACR_ICINVA | CF_CACR_EUSP) | |
264 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
265 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
266 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
267 | ||
05316f8e TL |
268 | /*----------------------------------------------------------------------- |
269 | * Memory bank definitions | |
270 | */ | |
271 | /* | |
709b384b | 272 | * CS0 - NOR Flash 16MB |
05316f8e TL |
273 | * CS1 - Available |
274 | * CS2 - Available | |
275 | * CS3 - Available | |
276 | * CS4 - Available | |
277 | * CS5 - Available | |
278 | */ | |
279 | ||
709b384b | 280 | /* Flash */ |
6d0f6bcf | 281 | #define CONFIG_SYS_CS0_BASE 0x00000000 |
709b384b TL |
282 | #define CONFIG_SYS_CS0_MASK 0x00FF0001 |
283 | #define CONFIG_SYS_CS0_CTRL 0x00004D80 | |
05316f8e | 284 | |
6d0f6bcf | 285 | #define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE |
05316f8e TL |
286 | |
287 | #endif /* _M54451EVB_H */ |