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57a12720 TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF5485 FireEngine board. | |
3 | * | |
4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
57a12720 TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M5485EVB_H | |
15 | #define _M5485EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
57a12720 | 21 | |
57a12720 | 22 | #define CONFIG_MCFUART |
6d0f6bcf | 23 | #define CONFIG_SYS_UART_PORT (0) |
57a12720 | 24 | |
1313db48 | 25 | #undef CONFIG_HW_WATCHDOG |
57a12720 TL |
26 | #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ |
27 | ||
57a12720 TL |
28 | #define CONFIG_SLTTMR |
29 | ||
30 | #define CONFIG_FSLDMAFEC | |
31 | #ifdef CONFIG_FSLDMAFEC | |
57a12720 | 32 | # define CONFIG_MII 1 |
0f3ba7e9 | 33 | # define CONFIG_MII_INIT 1 |
57a12720 TL |
34 | # define CONFIG_HAS_ETH1 |
35 | ||
6d0f6bcf JCPV |
36 | # define CONFIG_SYS_DMA_USE_INTSRAM 1 |
37 | # define CONFIG_SYS_DISCOVER_PHY | |
38 | # define CONFIG_SYS_RX_ETH_BUFFER 32 | |
39 | # define CONFIG_SYS_TX_ETH_BUFFER 48 | |
40 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
57a12720 | 41 | |
6d0f6bcf JCPV |
42 | # define CONFIG_SYS_FEC0_PINMUX 0 |
43 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
44 | # define CONFIG_SYS_FEC1_PINMUX 0 | |
45 | # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
57a12720 | 46 | |
53677ef1 | 47 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
48 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
49 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
57a12720 TL |
50 | # define FECDUPLEX FULL |
51 | # define FECSPEED _100BASET | |
52 | # else | |
6d0f6bcf JCPV |
53 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
54 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
57a12720 | 55 | # endif |
6d0f6bcf | 56 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
57a12720 | 57 | |
57a12720 TL |
58 | # define CONFIG_IPADDR 192.162.1.2 |
59 | # define CONFIG_NETMASK 255.255.255.0 | |
60 | # define CONFIG_SERVERIP 192.162.1.1 | |
61 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
57a12720 TL |
62 | |
63 | #endif | |
64 | ||
65 | #ifdef CONFIG_CMD_USB | |
57a12720 | 66 | # define CONFIG_USB_OHCI_NEW |
57a12720 | 67 | /*# define CONFIG_PCI_OHCI*/ |
6d0f6bcf JCPV |
68 | # define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 |
69 | # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
70 | # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" | |
71 | # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS | |
57a12720 TL |
72 | #endif |
73 | ||
74 | /* I2C */ | |
00f792e0 HS |
75 | #define CONFIG_SYS_I2C |
76 | #define CONFIG_SYS_I2C_FSL | |
77 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
78 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
79 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 | |
6d0f6bcf | 80 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
57a12720 TL |
81 | |
82 | /* PCI */ | |
83 | #ifdef CONFIG_CMD_PCI | |
f33fca22 | 84 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
57a12720 | 85 | |
6d0f6bcf JCPV |
86 | #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 |
87 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS | |
88 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 | |
57a12720 | 89 | |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_PCI_IO_BUS 0x71000000 |
91 | #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS | |
92 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 | |
57a12720 | 93 | |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 |
95 | #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS | |
96 | #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 | |
57a12720 TL |
97 | #endif |
98 | ||
57a12720 TL |
99 | #define CONFIG_UDP_CHECKSUM |
100 | ||
101 | #define CONFIG_HOSTNAME M548xEVB | |
102 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
103 | "netdev=eth0\0" \ | |
104 | "loadaddr=10000\0" \ | |
105 | "u-boot=u-boot.bin\0" \ | |
106 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
107 | "upd=run load; run prog\0" \ | |
108 | "prog=prot off bank 1;" \ | |
09933fb0 | 109 | "era ff800000 ff83ffff;" \ |
57a12720 TL |
110 | "cp.b ${loadaddr} ff800000 ${filesize};"\ |
111 | "save\0" \ | |
112 | "" | |
113 | ||
114 | #define CONFIG_PRAM 512 /* 512 KB */ | |
6d0f6bcf | 115 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
57a12720 | 116 | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
118 | #define CONFIG_SYS_LOAD_ADDR 0x00010000 | |
57a12720 | 119 | |
6d0f6bcf JCPV |
120 | #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK |
121 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 | |
57a12720 | 122 | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_MBAR 0xF0000000 |
124 | #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) | |
125 | #define CONFIG_SYS_INTSRAMSZ 0x8000 | |
57a12720 | 126 | |
6d0f6bcf | 127 | /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ |
57a12720 TL |
128 | |
129 | /* | |
130 | * Low Level Configuration Settings | |
131 | * (address mappings, register initial values, etc.) | |
132 | * You should know what you are doing if you make changes here. | |
133 | */ | |
134 | /*----------------------------------------------------------------------- | |
135 | * Definitions for initial stack pointer and data area (in DPRAM) | |
136 | */ | |
6d0f6bcf | 137 | #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 |
553f0982 | 138 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 139 | #define CONFIG_SYS_INIT_RAM_CTRL 0x21 |
553f0982 | 140 | #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ |
142 | #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 | |
25ddd1fb | 143 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
6d0f6bcf | 144 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
57a12720 TL |
145 | |
146 | /*----------------------------------------------------------------------- | |
147 | * Start addresses for the final memory configuration | |
148 | * (Set up by the startup code) | |
6d0f6bcf | 149 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
57a12720 | 150 | */ |
6d0f6bcf JCPV |
151 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
152 | #define CONFIG_SYS_SDRAM_CFG1 0x73711630 | |
153 | #define CONFIG_SYS_SDRAM_CFG2 0x46770000 | |
154 | #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 | |
155 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
156 | #define CONFIG_SYS_SDRAM_MODE 0x018D0000 | |
157 | #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA | |
158 | #ifdef CONFIG_SYS_DRAMSZ1 | |
159 | # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) | |
57a12720 | 160 | #else |
6d0f6bcf | 161 | # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ |
57a12720 TL |
162 | #endif |
163 | ||
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
165 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
57a12720 | 166 | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
168 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
57a12720 | 169 | |
6d0f6bcf | 170 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
57a12720 | 171 | |
09933fb0 JJ |
172 | /* Reserve 256 kB for malloc() */ |
173 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
57a12720 TL |
174 | /* |
175 | * For booting Linux, the board info and command line data | |
176 | * have to be in the first 8 MB of memory, since this is | |
177 | * the maximum mapped by the Linux kernel during initialization ?? | |
178 | */ | |
6d0f6bcf | 179 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
57a12720 TL |
180 | |
181 | /*----------------------------------------------------------------------- | |
182 | * FLASH organization | |
183 | */ | |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_FLASH_CFI |
185 | #ifdef CONFIG_SYS_FLASH_CFI | |
186 | # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) | |
00b1883a | 187 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
188 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
189 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
190 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
191 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
192 | #ifdef CONFIG_SYS_NOR1SZ | |
193 | # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
194 | # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) | |
195 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } | |
57a12720 | 196 | #else |
6d0f6bcf JCPV |
197 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
198 | # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) | |
57a12720 TL |
199 | #endif |
200 | #endif | |
201 | ||
202 | /* Configuration for environment | |
09933fb0 JJ |
203 | * Environment is not embedded in u-boot. First time runing may have env |
204 | * crc error warning if there is no correct environment on the flash. | |
57a12720 | 205 | */ |
09933fb0 JJ |
206 | #define CONFIG_ENV_OFFSET 0x40000 |
207 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
57a12720 TL |
208 | |
209 | /*----------------------------------------------------------------------- | |
210 | * Cache Configuration | |
211 | */ | |
6d0f6bcf | 212 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
57a12720 | 213 | |
dd9f054e | 214 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 215 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 216 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 217 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
218 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ |
219 | CF_CACR_IDCM) | |
220 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
221 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
222 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
223 | CF_ACR_EN | CF_ACR_SM_ALL) | |
224 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ | |
225 | CF_CACR_IEC | CF_CACR_ICINVA) | |
226 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
227 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
228 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
229 | ||
57a12720 TL |
230 | /*----------------------------------------------------------------------- |
231 | * Chipselect bank definitions | |
232 | */ | |
233 | /* | |
234 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
235 | * CS1 - NOR Flash | |
236 | * CS2 - Available | |
237 | * CS3 - Available | |
238 | * CS4 - Available | |
239 | * CS5 - Available | |
240 | */ | |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_CS0_BASE 0xFF800000 |
242 | #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) | |
243 | #define CONFIG_SYS_CS0_CTRL 0x00101980 | |
244 | ||
245 | #ifdef CONFIG_SYS_NOR1SZ | |
246 | #define CONFIG_SYS_CS1_BASE 0xE0000000 | |
247 | #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) | |
248 | #define CONFIG_SYS_CS1_CTRL 0x00101D80 | |
57a12720 TL |
249 | #endif |
250 | ||
251 | #endif /* _M5485EVB_H */ |