[people/ms/u-boot.git] / include / configs / MBX.h

/*
 * (C) Copyright 2000
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 *
 * Configuation settings for the MBX8xx board.
 *
 * -----------------------------------------------------------------
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
/*
 * Changed 2002-10-01
 * Added PCMCIA defines mostly taken from other U-Boot boards that
 * have PCMCIA already working.  If you find any bugs, incorrect assumptions
 * feel free to fix them yourself and submit a patch.
 * Rod Boyce <rod_boyce@stratexnet.com.
 */
/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
#define CONFIG_MBX		1	/* ...on an MBX module		*/

#define	CONFIG_SYS_TEXT_BASE	0xfe000000

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600
/* Define this to use the PCI bus */
#undef CONFIG_USE_PCI

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
#define CONFIG_8xx_GCLK_FREQ    (50000000UL)
#if 1
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootm 20000" /* autoboot command	*/

#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
				"nfsaddrs=10.0.0.99:10.0.0.2"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE   /* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_PCMCIA
#define CONFIG_CMD_IDE


#define CONFIG_DOS_PARTITION

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot	*/
#ifdef	CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Physical memory map as defined by the MBX PGM
 */
#define CONFIG_SYS_IMMR		0xFA200000 /* Internal Memory Mapped Register*/
#define CONFIG_SYS_NVRAM_BASE		0xFA000000 /* NVRAM			     */
#define CONFIG_SYS_NVRAM_OR		0xffe00000 /* w/o speed dependent flags!!    */
#define CONFIG_SYS_CSR_BASE		0xFA100000 /* Control/Status Registers	     */
#define CONFIG_SYS_PCIMEM_BASE		0x80000000 /* PCI I/O and Memory Spaces	     */
#define CONFIG_SYS_PCIMEM_OR		0xA0000108
#define CONFIG_SYS_PCIBRIDGE_BASE	0xFA210000 /* PCI-Bus Bridge Registers	     */
#define CONFIG_SYS_PCIBRIDGE_OR	0xFFFF0108

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2f00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
#define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)

/*-----------------------------------------------------------------------
 * Offset in DPMEM where we keep the VPD data
 */
#define CONFIG_SYS_DPRAMVPD		(CONFIG_SYS_INIT_VPD_OFFSET - 0x2000)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xfe000000
#ifdef	DEBUG
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#endif
#undef	CONFIG_SYS_MONITOR_BASE	/* 0x200000	   to run U-Boot from RAM */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	16	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * NVRAM Configuration
 *
 * Note: the MBX is special because there is already a firmware on this
 * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
 * access the NVRAM at the offset 0x1000.
 */
#define CONFIG_ENV_IS_IN_NVRAM	1	/* turn on NVRAM env feature */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_NVRAM_BASE + 0x1000)
#define CONFIG_ENV_SIZE		0x1000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
/* #define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME) */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC11 | SIUMCR_SEME | SIUMCR_BSC )

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)
#define CONFIG_SYS_SCCR	SCCR_TBS

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

#define CONFIG_SYS_PCMCIA_INTERRUPT	SIU_LEVEL6

#define CONFIG_PCMCIA_SLOT_A	1


/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O */
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 * Debug Entry Mode
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER 0

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2000
	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Marius Groeger <mgroeger@sysgo.de>
	5	*
	6	* Configuation settings for the MBX8xx board.
	7	*
	8	* -----------------------------------------------------------------
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27	/*
	28	* Changed 2002-10-01
	29	* Added PCMCIA defines mostly taken from other U-Boot boards that
	30	* have PCMCIA already working. If you find any bugs, incorrect assumptions
	31	* feel free to fix them yourself and submit a patch.
	32	* Rod Boyce <rod_boyce@stratexnet.com.
	33	*/
	34	/*
	35	* board/config.h - configuration options, board specific
	36	*/
	37
	38	#ifndef __CONFIG_H
	39	#define __CONFIG_H
	40
	41	/*
	42	* High Level Configuration Options
	43	* (easy to change)
	44	*/
	45
	46	#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
	47	#define CONFIG_MBX 1 /* ...on an MBX module */
	48
2ae18241 WD	49	#define CONFIG_SYS_TEXT_BASE 0xfe000000
2ae18241 WD	50
e2211743 WD	51	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	52	#undef CONFIG_8xx_CONS_SMC2
	53	#undef CONFIG_8xx_CONS_NONE
	54	#define CONFIG_BAUDRATE 9600
	55	/* Define this to use the PCI bus */
	56	#undef CONFIG_USE_PCI
	57
	58	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	59	#define CONFIG_8xx_GCLK_FREQ (50000000UL)
	60	#if 1
	61	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	62	#else
	63	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	64	#endif
	65	#define CONFIG_BOOTCOMMAND "bootm 20000" /* autoboot command */
	66
	67	#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
	68	"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
	69	"nfsaddrs=10.0.0.99:10.0.0.2"
	70
	71	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	72	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
e2211743 WD	73
	74	#undef CONFIG_WATCHDOG /* watchdog disabled */
	75
e2211743	76
659e2f67 JL	77	/*
	78	* BOOTP options
	79	*/
	80	#define CONFIG_BOOTP_BOOTFILESIZE
	81	#define CONFIG_BOOTP_BOOTPATH
	82	#define CONFIG_BOOTP_GATEWAY
	83	#define CONFIG_BOOTP_HOSTNAME
	84
	85
8353e139 JL	86	/*
	87	* Command line configuration.
	88	*/
	89	#define CONFIG_CMD_NET
	90	#define CONFIG_CMD_DFL
	91	#define CONFIG_CMD_SDRAM
	92	#define CONFIG_CMD_PCMCIA
	93	#define CONFIG_CMD_IDE
e2211743	94
8353e139 JL	95
8353e139 JL	96	#define CONFIG_DOS_PARTITION
e2211743 WD	97
	98	/*
	99	* Miscellaneous configurable options
	100	*/
6d0f6bcf JCPV	101	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	102	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	103	#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */
	104	#ifdef CONFIG_SYS_HUSH_PARSER
	105	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
e2211743	106	#endif
8353e139	107	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	108	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	109	#else
6d0f6bcf	110	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	111	#endif
6d0f6bcf JCPV	112	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	113	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	114	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743	115
6d0f6bcf JCPV	116	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	117	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
e2211743	118
6d0f6bcf	119	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
e2211743	120
6d0f6bcf	121	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
e2211743	122
6d0f6bcf	123	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
e2211743 WD	124
	125	/*
	126	* Low Level Configuration Settings
	127	* (address mappings, register initial values, etc.)
	128	* You should know what you are doing if you make changes here.
	129	*/
	130
	131	/*-----------------------------------------------------------------------
	132	* Physical memory map as defined by the MBX PGM
	133	*/
6d0f6bcf JCPV	134	#define CONFIG_SYS_IMMR 0xFA200000 /* Internal Memory Mapped Register*/
	135	#define CONFIG_SYS_NVRAM_BASE 0xFA000000 /* NVRAM */
	136	#define CONFIG_SYS_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
	137	#define CONFIG_SYS_CSR_BASE 0xFA100000 /* Control/Status Registers */
	138	#define CONFIG_SYS_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
	139	#define CONFIG_SYS_PCIMEM_OR 0xA0000108
	140	#define CONFIG_SYS_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
	141	#define CONFIG_SYS_PCIBRIDGE_OR 0xFFFF0108
e2211743 WD	142
	143	/*-----------------------------------------------------------------------
	144	* Definitions for initial stack pointer and data area (in DPRAM)
	145	*/
6d0f6bcf	146	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	147	#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
6d0f6bcf	148	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
553f0982	149	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
6d0f6bcf JCPV	150	#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
	151	#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
	152	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
e2211743 WD	153
	154	/*-----------------------------------------------------------------------
	155	* Offset in DPMEM where we keep the VPD data
	156	*/
6d0f6bcf	157	#define CONFIG_SYS_DPRAMVPD (CONFIG_SYS_INIT_VPD_OFFSET - 0x2000)
e2211743 WD	158
	159	/*-----------------------------------------------------------------------
	160	* Start addresses for the final memory configuration
	161	* (Set up by the startup code)
6d0f6bcf	162	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743	163	*/
6d0f6bcf JCPV	164	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	165	#define CONFIG_SYS_FLASH_BASE 0xfe000000
e2211743	166	#ifdef DEBUG
6d0f6bcf	167	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
e2211743	168	#else
6d0f6bcf	169	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
e2211743	170	#endif
6d0f6bcf JCPV	171	#undef CONFIG_SYS_MONITOR_BASE /* 0x200000 to run U-Boot from RAM */
	172	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	173	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e2211743 WD	174
	175	/*
	176	* For booting Linux, the board info and command line data
	177	* have to be in the first 8 MB of memory, since this is
	178	* the maximum mapped by the Linux kernel during initialization.
	179	*/
6d0f6bcf	180	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
e2211743 WD	181
	182	/*-----------------------------------------------------------------------
	183	* FLASH organization
	184	*/
6d0f6bcf JCPV	185	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	186	#define CONFIG_SYS_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
e2211743	187
6d0f6bcf JCPV	188	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
e2211743 WD	190
	191	/*-----------------------------------------------------------------------
	192	* NVRAM Configuration
	193	*
	194	* Note: the MBX is special because there is already a firmware on this
	195	* board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
	196	* access the NVRAM at the offset 0x1000.
	197	*/
9314cee6	198	#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
6d0f6bcf	199	#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_BASE + 0x1000)
0e8d1586	200	#define CONFIG_ENV_SIZE 0x1000
e2211743 WD	201
	202	/*-----------------------------------------------------------------------
	203	* Cache Configuration
	204	*/
6d0f6bcf	205	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
8353e139	206	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	207	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
e2211743 WD	208	#endif
	209
	210	/*-----------------------------------------------------------------------
	211	* SYPCR - System Protection Control 11-9
	212	* SYPCR can only be written once after reset!
	213	*-----------------------------------------------------------------------
	214	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	215	*/
	216	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	217	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
e2211743 WD	218	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
e2211743 WD	219	#else
6d0f6bcf	220	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF)
e2211743 WD	221	#endif
	222
	223	/*-----------------------------------------------------------------------
	224	* SIUMCR - SIU Module Configuration 11-6
	225	*-----------------------------------------------------------------------
	226	* PCMCIA config., multi-function pin tri-state
	227	*/
6d0f6bcf JCPV	228	/* #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DPC \| SIUMCR_MLRC10 \| SIUMCR_SEME) */
6d0f6bcf JCPV	229	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DPC \| SIUMCR_MLRC11 \| SIUMCR_SEME \| SIUMCR_BSC )
e2211743 WD	230
	231	/*-----------------------------------------------------------------------
	232	* TBSCR - Time Base Status and Control 11-26
	233	*-----------------------------------------------------------------------
	234	* Clear Reference Interrupt Status, Timebase freezing enabled
	235	*/
6d0f6bcf	236	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
e2211743 WD	237
	238	/*-----------------------------------------------------------------------
	239	* PISCR - Periodic Interrupt Status and Control 11-31
	240	*-----------------------------------------------------------------------
	241	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	242	*/
6d0f6bcf	243	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF \| PISCR_PTE)
e2211743 WD	244
	245	/*-----------------------------------------------------------------------
	246	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	247	*-----------------------------------------------------------------------
	248	* Reset PLL lock status sticky bit, timer expired status bit and timer
	249	* interrupt status bit - leave PLL multiplication factor unchanged !
	250	*/
6d0f6bcf	251	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
e2211743 WD	252
	253	/*-----------------------------------------------------------------------
	254	* SCCR - System Clock and reset Control Register 15-27
	255	*-----------------------------------------------------------------------
	256	* Set clock output, timebase and RTC source and divider,
	257	* power management and some other internal clocks
	258	*/
	259	#define SCCR_MASK (SCCR_RTDIV \| SCCR_RTSEL)
6d0f6bcf	260	#define CONFIG_SYS_SCCR SCCR_TBS
e2211743 WD	261
	262	/*-----------------------------------------------------------------------
	263	* PCMCIA stuff
	264	*-----------------------------------------------------------------------
	265	*
	266	*/
6d0f6bcf JCPV	267	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	268	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	269	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	270	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	271	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	272	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	273	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	274	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
e2211743	275
6d0f6bcf	276	#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6
e2211743 WD	277
	278	#define CONFIG_PCMCIA_SLOT_A 1
	279
	280
	281	/*-----------------------------------------------------------------------
	282	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	283	*-----------------------------------------------------------------------
	284	*/
	285
	286	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	287
	288	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	289	#undef CONFIG_IDE_LED /* LED for ide not supported */
	290	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	291
6d0f6bcf JCPV	292	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	293	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
e2211743	294
6d0f6bcf	295	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
e2211743	296
6d0f6bcf	297	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
e2211743 WD	298
e2211743 WD	299	/* Offset for data I/O */
6d0f6bcf	300	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
e2211743 WD	301
e2211743 WD	302	/* Offset for normal register accesses */
6d0f6bcf	303	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
e2211743 WD	304
e2211743 WD	305	/* Offset for alternate registers */
6d0f6bcf	306	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
e2211743 WD	307
	308	/*-----------------------------------------------------------------------
	309	* Debug Entry Mode
	310	*-----------------------------------------------------------------------
	311	*
	312	*/
6d0f6bcf	313	#define CONFIG_SYS_DER 0
e2211743	314
e2211743	315	#endif /* __CONFIG_H */