projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 991425fe | 1 | /* |
| 2ae18241 | 2 | * (C) Copyright 2006-2010 |
| 991425fe MB |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 991425fe MB |
6 | */ |
| 7 | ||
| 8 | /* | |
| 9 | * mpc8349emds board configuration file | |
| 10 | * | |
| 11 | */ | |
| 12 | ||
| 13 | #ifndef __CONFIG_H | |
| 14 | #define __CONFIG_H | |
| 15 | ||
| 991425fe MB |
16 | /* |
| 17 | * High Level Configuration Options | |
| 18 | */ | |
| 19 | #define CONFIG_E300 1 /* E300 Family */ | |
| 0f898604 | 20 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
| 2c7920af | 21 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
| 991425fe MB |
22 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
| 23 | #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ | |
| 24 | ||
| 2ae18241 WD |
25 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
| 26 | ||
| 27 | #define CONFIG_PCI_66M | |
| 28 | #ifdef CONFIG_PCI_66M | |
| 991425fe MB |
29 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
| 30 | #else | |
| 31 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
| 32 | #endif | |
| 33 | ||
| 447ad576 IS |
34 | #ifdef CONFIG_PCISLAVE |
| 35 | #define CONFIG_PCI | |
| 36 | #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ | |
| 37 | #endif /* CONFIG_PCISLAVE */ | |
| 38 | ||
| 991425fe | 39 | #ifndef CONFIG_SYS_CLK_FREQ |
| 2ae18241 | 40 | #ifdef CONFIG_PCI_66M |
| 991425fe | 41 | #define CONFIG_SYS_CLK_FREQ 66000000 |
| 8fe9bf61 | 42 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
| 991425fe MB |
43 | #else |
| 44 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
| 8fe9bf61 | 45 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
| 991425fe MB |
46 | #endif |
| 47 | #endif | |
| 48 | ||
| 49 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
| 50 | ||
| 6d0f6bcf | 51 | #define CONFIG_SYS_IMMR 0xE0000000 |
| 991425fe | 52 | |
| 32795eca | 53 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 6d0f6bcf JCPV |
54 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
| 55 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
| 991425fe MB |
56 | |
| 57 | /* | |
| 58 | * DDR Setup | |
| 59 | */ | |
| 8d172c0f | 60 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
| d326f4a2 | 61 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
| 991425fe MB |
62 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
| 63 | ||
| d4b91066 YS |
64 | /* |
| 65 | * define CONFIG_FSL_DDR2 to use unified DDR driver | |
| 66 | * undefine it to use old spd_sdram.c | |
| 67 | */ | |
| 68 | #define CONFIG_FSL_DDR2 | |
| 69 | #ifdef CONFIG_FSL_DDR2 | |
| 70 | #define CONFIG_SYS_SPD_BUS_NUM 0 | |
| 71 | #define SPD_EEPROM_ADDRESS1 0x52 | |
| 72 | #define SPD_EEPROM_ADDRESS2 0x51 | |
| 73 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 74 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
| 75 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 76 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
| 77 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 78 | #endif | |
| 79 | ||
| dc9e499c RJ |
80 | /* |
| 81 | * 32-bit data path mode. | |
| cf48eb9a | 82 | * |
| dc9e499c RJ |
83 | * Please note that using this mode for devices with the real density of 64-bit |
| 84 | * effectively reduces the amount of available memory due to the effect of | |
| 85 | * wrapping around while translating address to row/columns, for example in the | |
| 86 | * 256MB module the upper 128MB get aliased with contents of the lower | |
| 87 | * 128MB); normally this define should be used for devices with real 32-bit | |
| cf48eb9a | 88 | * data path. |
| dc9e499c RJ |
89 | */ |
| 90 | #undef CONFIG_DDR_32BIT | |
| 91 | ||
| 32795eca JH |
92 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
| 93 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 6d0f6bcf | 94 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
| 32795eca JH |
95 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
| 96 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
| 991425fe MB |
97 | #undef CONFIG_DDR_2T_TIMING |
| 98 | ||
| 8d172c0f XX |
99 | /* |
| 100 | * DDRCDR - DDR Control Driver Register | |
| 101 | */ | |
| 6d0f6bcf | 102 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
| 8d172c0f | 103 | |
| 991425fe | 104 | #if defined(CONFIG_SPD_EEPROM) |
| dc9e499c RJ |
105 | /* |
| 106 | * Determine DDR configuration from I2C interface. | |
| 107 | */ | |
| 108 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
| 991425fe | 109 | #else |
| dc9e499c RJ |
110 | /* |
| 111 | * Manually set up DDR parameters | |
| 112 | */ | |
| 6d0f6bcf | 113 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
| 8d172c0f | 114 | #if defined(CONFIG_DDR_II) |
| 6d0f6bcf | 115 | #define CONFIG_SYS_DDRCDR 0x80080001 |
| 32795eca | 116 | #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f |
| 6d0f6bcf | 117 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 |
| 32795eca JH |
118 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 |
| 119 | #define CONFIG_SYS_DDR_TIMING_1 0x38357322 | |
| 120 | #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 | |
| 121 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
| 122 | #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 | |
| 6d0f6bcf JCPV |
123 | #define CONFIG_SYS_DDR_MODE 0x47d00432 |
| 124 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
| 32795eca | 125 | #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 |
| 6d0f6bcf JCPV |
126 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
| 127 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
| 8d172c0f | 128 | #else |
| 2e651b24 | 129 | #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ |
| 32795eca JH |
130 | | CSCONFIG_ROW_BIT_13 \ |
| 131 | | CSCONFIG_COL_BIT_10) | |
| 6d0f6bcf JCPV |
132 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 |
| 133 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
| 32795eca | 134 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
| 6d0f6bcf | 135 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
| dc9e499c RJ |
136 | |
| 137 | #if defined(CONFIG_DDR_32BIT) | |
| 138 | /* set burst length to 8 for 32-bit data path */ | |
| 32795eca JH |
139 | /* DLL,normal,seq,4/2.5, 8 burst len */ |
| 140 | #define CONFIG_SYS_DDR_MODE 0x00000023 | |
| dc9e499c RJ |
141 | #else |
| 142 | /* the default burst length is 4 - for 64-bit data path */ | |
| 32795eca JH |
143 | /* DLL,normal,seq,4/2.5, 4 burst len */ |
| 144 | #define CONFIG_SYS_DDR_MODE 0x00000022 | |
| dc9e499c | 145 | #endif |
| 991425fe | 146 | #endif |
| 8d172c0f | 147 | #endif |
| 991425fe MB |
148 | |
| 149 | /* | |
| 150 | * SDRAM on the Local Bus | |
| 151 | */ | |
| 6d0f6bcf JCPV |
152 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
| 153 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
| 991425fe MB |
154 | |
| 155 | /* | |
| 156 | * FLASH on the Local Bus | |
| 157 | */ | |
| 32795eca JH |
158 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
| 159 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
| 6d0f6bcf | 160 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
| 32795eca JH |
161 | #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ |
| 162 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
| 6d0f6bcf | 163 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
| 991425fe | 164 | |
| 7d6a0982 JH |
165 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
| 166 | | BR_PS_16 /* 16 bit port */ \ | |
| 167 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
| 168 | | BR_V) /* valid */ | |
| 169 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
| 32795eca JH |
170 | | OR_UPM_XAM \ |
| 171 | | OR_GPCM_CSNT \ | |
| 172 | | OR_GPCM_ACS_DIV2 \ | |
| 173 | | OR_GPCM_XACS \ | |
| 174 | | OR_GPCM_SCY_15 \ | |
| 7d6a0982 JH |
175 | | OR_GPCM_TRLX_SET \ |
| 176 | | OR_GPCM_EHTR_SET \ | |
| 32795eca | 177 | | OR_GPCM_EAD) |
| 7d6a0982 | 178 | |
| 32795eca JH |
179 | /* window base at flash base */ |
| 180 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
| 7d6a0982 | 181 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
| 991425fe | 182 | |
| 32795eca JH |
183 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 184 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
| 991425fe | 185 | |
| 6d0f6bcf JCPV |
186 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 187 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 188 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 991425fe | 189 | |
| 14d0a02a | 190 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 991425fe | 191 | |
| 6d0f6bcf JCPV |
192 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 193 | #define CONFIG_SYS_RAMBOOT | |
| 991425fe | 194 | #else |
| 6d0f6bcf | 195 | #undef CONFIG_SYS_RAMBOOT |
| 991425fe MB |
196 | #endif |
| 197 | ||
| 198 | /* | |
| 199 | * BCSR register on local bus 32KB, 8-bit wide for MDS config reg | |
| 200 | */ | |
| 32795eca JH |
201 | #define CONFIG_SYS_BCSR 0xE2400000 |
| 202 | /* Access window base at BCSR base */ | |
| 203 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
| 7d6a0982 JH |
204 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
| 205 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
| 206 | | BR_PS_8 \ | |
| 207 | | BR_MS_GPCM \ | |
| 208 | | BR_V) | |
| 209 | /* 0x00000801 */ | |
| 210 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
| 211 | | OR_GPCM_XAM \ | |
| 212 | | OR_GPCM_CSNT \ | |
| 213 | | OR_GPCM_SCY_15 \ | |
| 214 | | OR_GPCM_TRLX_CLEAR \ | |
| 215 | | OR_GPCM_EHTR_CLEAR) | |
| 216 | /* 0xFFFFE8F0 */ | |
| 991425fe | 217 | |
| 6d0f6bcf | 218 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 32795eca JH |
219 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
| 220 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
| 991425fe | 221 | |
| 32795eca JH |
222 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 223 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| 6d0f6bcf | 224 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 991425fe | 225 | |
| 32795eca | 226 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
| c8a90646 | 227 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
| 991425fe MB |
228 | |
| 229 | /* | |
| 230 | * Local Bus LCRR and LBCR regs | |
| 231 | * LCRR: DLL bypass, Clock divider is 4 | |
| 232 | * External Local Bus rate is | |
| 233 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
| 234 | */ | |
| 32795eca JH |
235 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
| 236 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
| 6d0f6bcf | 237 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
| 991425fe | 238 | |
| 8d172c0f XX |
239 | /* |
| 240 | * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. | |
| 6d0f6bcf | 241 | * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM |
| 8d172c0f | 242 | */ |
| 6d0f6bcf | 243 | #undef CONFIG_SYS_LB_SDRAM |
| 991425fe | 244 | |
| 6d0f6bcf | 245 | #ifdef CONFIG_SYS_LB_SDRAM |
| 991425fe MB |
246 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ |
| 247 | /* | |
| 248 | * Base Register 2 and Option Register 2 configure SDRAM. | |
| 6d0f6bcf | 249 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
| 991425fe MB |
250 | * |
| 251 | * For BR2, need: | |
| 252 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
| 253 | * port-size = 32-bits = BR2[19:20] = 11 | |
| 254 | * no parity checking = BR2[21:22] = 00 | |
| 255 | * SDRAM for MSEL = BR2[24:26] = 011 | |
| 256 | * Valid = BR[31] = 1 | |
| 257 | * | |
| 258 | * 0 4 8 12 16 20 24 28 | |
| 259 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
| 991425fe MB |
260 | */ |
| 261 | ||
| 7d6a0982 JH |
262 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ |
| 263 | | BR_PS_32 /* 32-bit port */ \ | |
| 264 | | BR_MS_SDRAM /* MSEL = SDRAM */ \ | |
| 265 | | BR_V) /* Valid */ | |
| 266 | /* 0xF0001861 */ | |
| 267 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE | |
| 268 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) | |
| 991425fe MB |
269 | |
| 270 | /* | |
| 6d0f6bcf | 271 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
| 991425fe MB |
272 | * |
| 273 | * For OR2, need: | |
| 274 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
| 275 | * XAM, OR2[17:18] = 11 | |
| 276 | * 9 columns OR2[19-21] = 010 | |
| 277 | * 13 rows OR2[23-25] = 100 | |
| 278 | * EAD set for extra time OR[31] = 1 | |
| 279 | * | |
| 280 | * 0 4 8 12 16 20 24 28 | |
| 281 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
| 282 | */ | |
| 283 | ||
| 7d6a0982 JH |
284 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ |
| 285 | | OR_SDRAM_XAM \ | |
| 286 | | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ | |
| 287 | | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ | |
| 288 | | OR_SDRAM_EAD) | |
| 289 | /* 0xFC006901 */ | |
| 991425fe | 290 | |
| 32795eca JH |
291 | /* LB sdram refresh timer, about 6us */ |
| 292 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
| 293 | /* LB refresh timer prescal, 266MHz/32 */ | |
| 294 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
| 991425fe | 295 | |
| 32795eca | 296 | #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ |
| 540dcf1c KG |
297 | | LSDMR_BSMA1516 \ |
| 298 | | LSDMR_RFCR8 \ | |
| 299 | | LSDMR_PRETOACT6 \ | |
| 300 | | LSDMR_ACTTORW3 \ | |
| 301 | | LSDMR_BL8 \ | |
| 302 | | LSDMR_WRC3 \ | |
| 32795eca | 303 | | LSDMR_CL3) |
| 991425fe MB |
304 | |
| 305 | /* | |
| 306 | * SDRAM Controller configuration sequence. | |
| 307 | */ | |
| 540dcf1c KG |
308 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
| 309 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
| 310 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
| 311 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
| 312 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
| 991425fe MB |
313 | #endif |
| 314 | ||
| 315 | /* | |
| 316 | * Serial Port | |
| 317 | */ | |
| 318 | #define CONFIG_CONS_INDEX 1 | |
| 6d0f6bcf JCPV |
319 | #define CONFIG_SYS_NS16550 |
| 320 | #define CONFIG_SYS_NS16550_SERIAL | |
| 321 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 322 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 991425fe | 323 | |
| 6d0f6bcf | 324 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 32795eca | 325 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
| 991425fe | 326 | |
| 6d0f6bcf JCPV |
327 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
| 328 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
| 991425fe | 329 | |
| 22d71a71 | 330 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| a059e90e | 331 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| 991425fe | 332 | /* Use the HUSH parser */ |
| 6d0f6bcf | 333 | #define CONFIG_SYS_HUSH_PARSER |
| 991425fe | 334 | |
| bf0b542d | 335 | /* pass open firmware flat tree */ |
| 35cc4e48 | 336 | #define CONFIG_OF_LIBFDT 1 |
| bf0b542d | 337 | #define CONFIG_OF_BOARD_SETUP 1 |
| 5b8bc606 | 338 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| bf0b542d | 339 | |
| 991425fe | 340 | /* I2C */ |
| 32795eca JH |
341 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
| 342 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| be5e6181 | 343 | #define CONFIG_FSL_I2C |
| b24f119d | 344 | #define CONFIG_I2C_MULTI_BUS |
| 32795eca JH |
345 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 346 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 347 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */ | |
| 348 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 349 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 991425fe | 350 | |
| 80ddd226 | 351 | /* SPI */ |
| 8931ab17 | 352 | #define CONFIG_MPC8XXX_SPI |
| 80ddd226 | 353 | #undef CONFIG_SOFT_SPI /* SPI bit-banged */ |
| 80ddd226 BW |
354 | |
| 355 | /* GPIOs. Used as SPI chip selects */ | |
| 6d0f6bcf JCPV |
356 | #define CONFIG_SYS_GPIO1_PRELIM |
| 357 | #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ | |
| 358 | #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ | |
| 80ddd226 | 359 | |
| 991425fe | 360 | /* TSEC */ |
| 6d0f6bcf | 361 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
| 32795eca | 362 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
| 6d0f6bcf | 363 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
| 32795eca | 364 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
| 991425fe | 365 | |
| 8fe9bf61 | 366 | /* USB */ |
| 6d0f6bcf | 367 | #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ |
| 991425fe MB |
368 | |
| 369 | /* | |
| 370 | * General PCI | |
| 371 | * Addresses are mapped 1-1. | |
| 372 | */ | |
| 6d0f6bcf JCPV |
373 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 374 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
| 375 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 376 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
| 377 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
| 378 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
| 32795eca JH |
379 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
| 380 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
| 381 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
| 6d0f6bcf JCPV |
382 | |
| 383 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
| 384 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
| 385 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
| 386 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
| 387 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
| 388 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
| 32795eca JH |
389 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
| 390 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
| 391 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
| 991425fe MB |
392 | |
| 393 | #if defined(CONFIG_PCI) | |
| 394 | ||
| 8fe9bf61 | 395 | #define PCI_ONE_PCI1 |
| 991425fe MB |
396 | #if defined(PCI_64BIT) |
| 397 | #undef PCI_ALL_PCI1 | |
| 398 | #undef PCI_TWO_PCI1 | |
| 399 | #undef PCI_ONE_PCI1 | |
| 400 | #endif | |
| 401 | ||
| 991425fe | 402 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 162338e1 | 403 | #define CONFIG_83XX_PCI_STREAMING |
| 991425fe MB |
404 | |
| 405 | #undef CONFIG_EEPRO100 | |
| 406 | #undef CONFIG_TULIP | |
| 407 | ||
| 408 | #if !defined(CONFIG_PCI_PNP) | |
| 409 | #define PCI_ENET0_IOADDR 0xFIXME | |
| 410 | #define PCI_ENET0_MEMADDR 0xFIXME | |
| 53677ef1 | 411 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
| 991425fe MB |
412 | #endif |
| 413 | ||
| 414 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 6d0f6bcf | 415 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
| 991425fe MB |
416 | |
| 417 | #endif /* CONFIG_PCI */ | |
| 418 | ||
| 419 | /* | |
| 420 | * TSEC configuration | |
| 421 | */ | |
| 32795eca | 422 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
| 991425fe MB |
423 | |
| 424 | #if defined(CONFIG_TSEC_ENET) | |
| 991425fe MB |
425 | |
| 426 | #define CONFIG_GMII 1 /* MII PHY management */ | |
| 32795eca | 427 | #define CONFIG_TSEC1 1 |
| 255a3577 | 428 | #define CONFIG_TSEC1_NAME "TSEC0" |
| 32795eca | 429 | #define CONFIG_TSEC2 1 |
| 255a3577 | 430 | #define CONFIG_TSEC2_NAME "TSEC1" |
| 991425fe MB |
431 | #define TSEC1_PHY_ADDR 0 |
| 432 | #define TSEC2_PHY_ADDR 1 | |
| 433 | #define TSEC1_PHYIDX 0 | |
| 434 | #define TSEC2_PHYIDX 0 | |
| 3a79013e AF |
435 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 436 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 991425fe MB |
437 | |
| 438 | /* Options are: TSEC[0-1] */ | |
| 439 | #define CONFIG_ETHPRIME "TSEC0" | |
| 440 | ||
| 441 | #endif /* CONFIG_TSEC_ENET */ | |
| 442 | ||
| 443 | /* | |
| 444 | * Configure on-board RTC | |
| 445 | */ | |
| 32795eca JH |
446 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
| 447 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
| 991425fe MB |
448 | |
| 449 | /* | |
| 450 | * Environment | |
| 451 | */ | |
| 6d0f6bcf | 452 | #ifndef CONFIG_SYS_RAMBOOT |
| 5a1aceb0 | 453 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 32795eca JH |
454 | #define CONFIG_ENV_ADDR \ |
| 455 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
| 0e8d1586 JCPV |
456 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 457 | #define CONFIG_ENV_SIZE 0x2000 | |
| 991425fe MB |
458 | |
| 459 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
460 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 461 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 991425fe MB |
462 | |
| 463 | #else | |
| 32795eca | 464 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
| 93f6d725 | 465 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 6d0f6bcf | 466 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 0e8d1586 | 467 | #define CONFIG_ENV_SIZE 0x2000 |
| 991425fe MB |
468 | #endif |
| 469 | ||
| 470 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 471 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 991425fe | 472 | |
| 8ea5499a | 473 | |
| 659e2f67 JL |
474 | /* |
| 475 | * BOOTP options | |
| 476 | */ | |
| 477 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 478 | #define CONFIG_BOOTP_BOOTPATH | |
| 479 | #define CONFIG_BOOTP_GATEWAY | |
| 480 | #define CONFIG_BOOTP_HOSTNAME | |
| 481 | ||
| 482 | ||
| 8ea5499a JL |
483 | /* |
| 484 | * Command line configuration. | |
| 485 | */ | |
| 486 | #include <config_cmd_default.h> | |
| 487 | ||
| 488 | #define CONFIG_CMD_PING | |
| 489 | #define CONFIG_CMD_I2C | |
| 490 | #define CONFIG_CMD_DATE | |
| 491 | #define CONFIG_CMD_MII | |
| 492 | ||
| 991425fe | 493 | #if defined(CONFIG_PCI) |
| 8ea5499a | 494 | #define CONFIG_CMD_PCI |
| 991425fe | 495 | #endif |
| 8ea5499a | 496 | |
| 6d0f6bcf | 497 | #if defined(CONFIG_SYS_RAMBOOT) |
| bdab39d3 | 498 | #undef CONFIG_CMD_SAVEENV |
| 8ea5499a | 499 | #undef CONFIG_CMD_LOADS |
| 991425fe MB |
500 | #endif |
| 501 | ||
| 991425fe MB |
502 | |
| 503 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 504 | ||
| 505 | /* | |
| 506 | * Miscellaneous configurable options | |
| 507 | */ | |
| 6d0f6bcf JCPV |
508 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 509 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 510 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 991425fe | 511 | |
| 8ea5499a | 512 | #if defined(CONFIG_CMD_KGDB) |
| 32795eca | 513 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 991425fe | 514 | #else |
| 32795eca | 515 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 991425fe MB |
516 | #endif |
| 517 | ||
| 32795eca JH |
518 | /* Print Buffer Size */ |
| 519 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 520 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 521 | /* Boot Argument Buffer Size */ | |
| 522 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 523 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 991425fe MB |
524 | |
| 525 | /* | |
| 526 | * For booting Linux, the board info and command line data | |
| 9f530d59 | 527 | * have to be in the first 256 MB of memory, since this is |
| 991425fe MB |
528 | * the maximum mapped by the Linux kernel during initialization. |
| 529 | */ | |
| 32795eca JH |
530 | /* Initial Memory map for Linux*/ |
| 531 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
| 991425fe | 532 | |
| 6d0f6bcf | 533 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
| 991425fe MB |
534 | |
| 535 | #if 1 /*528/264*/ | |
| 6d0f6bcf | 536 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
537 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 538 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 539 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
540 | HRCWL_VCO_1X2 |\ |
| 541 | HRCWL_CORE_TO_CSB_2X1) | |
| 542 | #elif 0 /*396/132*/ | |
| 6d0f6bcf | 543 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
544 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 545 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 546 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
547 | HRCWL_VCO_1X4 |\ |
| 548 | HRCWL_CORE_TO_CSB_3X1) | |
| 549 | #elif 0 /*264/132*/ | |
| 6d0f6bcf | 550 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
551 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 552 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 553 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
554 | HRCWL_VCO_1X4 |\ |
| 555 | HRCWL_CORE_TO_CSB_2X1) | |
| 556 | #elif 0 /*132/132*/ | |
| 6d0f6bcf | 557 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
558 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 559 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 560 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
561 | HRCWL_VCO_1X4 |\ |
| 562 | HRCWL_CORE_TO_CSB_1X1) | |
| 563 | #elif 0 /*264/264 */ | |
| 6d0f6bcf | 564 | #define CONFIG_SYS_HRCW_LOW (\ |
| 991425fe MB |
565 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 566 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 8fe9bf61 | 567 | HRCWL_CSB_TO_CLKIN |\ |
| 991425fe MB |
568 | HRCWL_VCO_1X4 |\ |
| 569 | HRCWL_CORE_TO_CSB_1X1) | |
| 570 | #endif | |
| 571 | ||
| 447ad576 | 572 | #ifdef CONFIG_PCISLAVE |
| 6d0f6bcf | 573 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 447ad576 IS |
574 | HRCWH_PCI_AGENT |\ |
| 575 | HRCWH_64_BIT_PCI |\ | |
| 576 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
| 577 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
| 578 | HRCWH_CORE_ENABLE |\ | |
| 579 | HRCWH_FROM_0X00000100 |\ | |
| 580 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 581 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 582 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 583 | HRCWH_TSEC1M_IN_GMII |\ | |
| 32795eca | 584 | HRCWH_TSEC2M_IN_GMII) |
| 447ad576 | 585 | #else |
| 991425fe | 586 | #if defined(PCI_64BIT) |
| 6d0f6bcf | 587 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 991425fe MB |
588 | HRCWH_PCI_HOST |\ |
| 589 | HRCWH_64_BIT_PCI |\ | |
| 590 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 591 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
| 592 | HRCWH_CORE_ENABLE |\ | |
| 593 | HRCWH_FROM_0X00000100 |\ | |
| 594 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 595 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 596 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 597 | HRCWH_TSEC1M_IN_GMII |\ | |
| 32795eca | 598 | HRCWH_TSEC2M_IN_GMII) |
| 991425fe | 599 | #else |
| 6d0f6bcf | 600 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 991425fe MB |
601 | HRCWH_PCI_HOST |\ |
| 602 | HRCWH_32_BIT_PCI |\ | |
| 603 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 604 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
| 605 | HRCWH_CORE_ENABLE |\ | |
| 606 | HRCWH_FROM_0X00000100 |\ | |
| 607 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 608 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 609 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 610 | HRCWH_TSEC1M_IN_GMII |\ | |
| 32795eca | 611 | HRCWH_TSEC2M_IN_GMII) |
| 447ad576 IS |
612 | #endif /* PCI_64BIT */ |
| 613 | #endif /* CONFIG_PCISLAVE */ | |
| 991425fe | 614 | |
| a5fe514e LN |
615 | /* |
| 616 | * System performance | |
| 617 | */ | |
| 6d0f6bcf | 618 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
| 32795eca | 619 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
| 6d0f6bcf JCPV |
620 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
| 621 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
| 622 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
| 623 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
| a5fe514e | 624 | |
| 991425fe | 625 | /* System IO Config */ |
| 3c9b1ee1 | 626 | #define CONFIG_SYS_SICRH 0 |
| 6d0f6bcf | 627 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
| 991425fe | 628 | |
| 6d0f6bcf | 629 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
| 32795eca JH |
630 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
| 631 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
| 991425fe | 632 | |
| 32795eca | 633 | /* #define CONFIG_SYS_HID0_FINAL (\ |
| 991425fe MB |
634 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
| 635 | HID0_ENABLE_M_BIT |\ | |
| 32795eca | 636 | HID0_ENABLE_ADDRESS_BROADCAST) */ |
| 991425fe MB |
637 | |
| 638 | ||
| 6d0f6bcf | 639 | #define CONFIG_SYS_HID2 HID2_HBE |
| 31d82672 | 640 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 991425fe MB |
641 | |
| 642 | /* DDR @ 0x00000000 */ | |
| 32795eca | 643 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
| 72cd4087 | 644 | | BATL_PP_RW \ |
| 32795eca JH |
645 | | BATL_MEMCOHERENCE) |
| 646 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
| 647 | | BATU_BL_256M \ | |
| 648 | | BATU_VS \ | |
| 649 | | BATU_VP) | |
| 991425fe MB |
650 | |
| 651 | /* PCI @ 0x80000000 */ | |
| 652 | #ifdef CONFIG_PCI | |
| 842033e6 | 653 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 32795eca | 654 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
| 72cd4087 | 655 | | BATL_PP_RW \ |
| 32795eca JH |
656 | | BATL_MEMCOHERENCE) |
| 657 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
| 658 | | BATU_BL_256M \ | |
| 659 | | BATU_VS \ | |
| 660 | | BATU_VP) | |
| 661 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
| 72cd4087 | 662 | | BATL_PP_RW \ |
| 32795eca JH |
663 | | BATL_CACHEINHIBIT \ |
| 664 | | BATL_GUARDEDSTORAGE) | |
| 665 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
| 666 | | BATU_BL_256M \ | |
| 667 | | BATU_VS \ | |
| 668 | | BATU_VP) | |
| 991425fe | 669 | #else |
| 6d0f6bcf JCPV |
670 | #define CONFIG_SYS_IBAT1L (0) |
| 671 | #define CONFIG_SYS_IBAT1U (0) | |
| 672 | #define CONFIG_SYS_IBAT2L (0) | |
| 673 | #define CONFIG_SYS_IBAT2U (0) | |
| 991425fe MB |
674 | #endif |
| 675 | ||
| 8fe9bf61 | 676 | #ifdef CONFIG_MPC83XX_PCI2 |
| 32795eca | 677 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
| 72cd4087 | 678 | | BATL_PP_RW \ |
| 32795eca JH |
679 | | BATL_MEMCOHERENCE) |
| 680 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
| 681 | | BATU_BL_256M \ | |
| 682 | | BATU_VS \ | |
| 683 | | BATU_VP) | |
| 684 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
| 72cd4087 | 685 | | BATL_PP_RW \ |
| 32795eca JH |
686 | | BATL_CACHEINHIBIT \ |
| 687 | | BATL_GUARDEDSTORAGE) | |
| 688 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
| 689 | | BATU_BL_256M \ | |
| 690 | | BATU_VS \ | |
| 691 | | BATU_VP) | |
| 8fe9bf61 | 692 | #else |
| 6d0f6bcf JCPV |
693 | #define CONFIG_SYS_IBAT3L (0) |
| 694 | #define CONFIG_SYS_IBAT3U (0) | |
| 695 | #define CONFIG_SYS_IBAT4L (0) | |
| 696 | #define CONFIG_SYS_IBAT4U (0) | |
| 8fe9bf61 | 697 | #endif |
| 991425fe | 698 | |
| 8fe9bf61 | 699 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
| 32795eca | 700 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
| 72cd4087 | 701 | | BATL_PP_RW \ |
| 32795eca JH |
702 | | BATL_CACHEINHIBIT \ |
| 703 | | BATL_GUARDEDSTORAGE) | |
| 704 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
| 705 | | BATU_BL_256M \ | |
| 706 | | BATU_VS \ | |
| 707 | | BATU_VP) | |
| 991425fe | 708 | |
| 8fe9bf61 | 709 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
| 32795eca | 710 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
| 72cd4087 JH |
711 | | BATL_PP_RW \ |
| 712 | | BATL_MEMCOHERENCE \ | |
| 713 | | BATL_GUARDEDSTORAGE) | |
| 32795eca JH |
714 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ |
| 715 | | BATU_BL_256M \ | |
| 716 | | BATU_VS \ | |
| 717 | | BATU_VP) | |
| 6d0f6bcf JCPV |
718 | |
| 719 | #define CONFIG_SYS_IBAT7L (0) | |
| 720 | #define CONFIG_SYS_IBAT7U (0) | |
| 721 | ||
| 722 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
| 723 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 724 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 725 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 726 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
| 727 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
| 728 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
| 729 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 730 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
| 731 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| 732 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
| 733 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| 734 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
| 735 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| 736 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
| 737 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| 991425fe | 738 | |
| 8ea5499a | 739 | #if defined(CONFIG_CMD_KGDB) |
| 991425fe MB |
740 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
| 741 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 742 | #endif | |
| 743 | ||
| 744 | /* | |
| 745 | * Environment Configuration | |
| 746 | */ | |
| 747 | #define CONFIG_ENV_OVERWRITE | |
| 748 | ||
| 749 | #if defined(CONFIG_TSEC_ENET) | |
| 991425fe | 750 | #define CONFIG_HAS_ETH1 |
| 10327dc5 | 751 | #define CONFIG_HAS_ETH0 |
| 991425fe MB |
752 | #endif |
| 753 | ||
| 991425fe | 754 | #define CONFIG_HOSTNAME mpc8349emds |
| 8b3637c6 | 755 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
| b3f44c21 | 756 | #define CONFIG_BOOTFILE "uImage" |
| 991425fe | 757 | |
| 32795eca | 758 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
| 991425fe MB |
759 | |
| 760 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
| 32795eca | 761 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 991425fe MB |
762 | |
| 763 | #define CONFIG_BAUDRATE 115200 | |
| 764 | ||
| 765 | #define CONFIG_PREBOOT "echo;" \ | |
| 32bf3d14 | 766 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
| 991425fe MB |
767 | "echo" |
| 768 | ||
| 769 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 770 | "netdev=eth0\0" \ | |
| 771 | "hostname=mpc8349emds\0" \ | |
| 772 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 773 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 774 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 775 | "addip=setenv bootargs ${bootargs} " \ | |
| 776 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 777 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 778 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
| 779 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 780 | "bootm ${kernel_addr}\0" \ | |
| 781 | "flash_self=run ramargs addip addtty;" \ | |
| 782 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
| 783 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
| 784 | "bootm\0" \ | |
| 991425fe MB |
785 | "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ |
| 786 | "update=protect off fe000000 fe03ffff; " \ | |
| 32795eca | 787 | "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ |
| d8ab58b2 | 788 | "upd=run load update\0" \ |
| 79f516bc | 789 | "fdtaddr=780000\0" \ |
| cc861f71 | 790 | "fdtfile=mpc834x_mds.dtb\0" \ |
| 991425fe MB |
791 | "" |
| 792 | ||
| 32795eca JH |
793 | #define CONFIG_NFSBOOTCOMMAND \ |
| 794 | "setenv bootargs root=/dev/nfs rw " \ | |
| 795 | "nfsroot=$serverip:$rootpath " \ | |
| 796 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
| 797 | "$netdev:off " \ | |
| 798 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 799 | "tftp $loadaddr $bootfile;" \ | |
| 800 | "tftp $fdtaddr $fdtfile;" \ | |
| 801 | "bootm $loadaddr - $fdtaddr" | |
| bf0b542d KP |
802 | |
| 803 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 32795eca JH |
804 | "setenv bootargs root=/dev/ram rw " \ |
| 805 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 806 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 807 | "tftp $loadaddr $bootfile;" \ | |
| 808 | "tftp $fdtaddr $fdtfile;" \ | |
| 809 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| bf0b542d | 810 | |
| 991425fe MB |
811 | #define CONFIG_BOOTCOMMAND "run flash_self" |
| 812 | ||
| 813 | #endif /* __CONFIG_H */ |