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Commit | Line | Data |
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2ad6b513 | 1 | /* |
4c2e3da8 | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
2ad6b513 | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
2ad6b513 TT |
5 | */ |
6 | ||
7 | /* | |
7a78f148 | 8 | MPC8349E-mITX and MPC8349E-mITX-GP board configuration file |
2ad6b513 TT |
9 | |
10 | Memory map: | |
11 | ||
12 | 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) | |
13 | 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) | |
14 | 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) | |
15 | 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) | |
16 | 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) | |
17 | 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) | |
7a78f148 | 18 | 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) |
2ad6b513 | 19 | 0xF001_0000-0xF001_FFFF Local bus expansion slot |
7a78f148 TT |
20 | 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) |
21 | 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory | |
22 | 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) | |
2ad6b513 TT |
23 | |
24 | I2C address list: | |
dd520bf3 WD |
25 | Align. Board |
26 | Bus Addr Part No. Description Length Location | |
2ad6b513 | 27 | ---------------------------------------------------------------- |
dd520bf3 | 28 | I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
2ad6b513 | 29 | |
dd520bf3 WD |
30 | I2C1 0x20 PCF8574 I2C Expander 0 U8 |
31 | I2C1 0x21 PCF8574 I2C Expander 0 U10 | |
32 | I2C1 0x38 PCF8574A I2C Expander 0 U8 | |
33 | I2C1 0x39 PCF8574A I2C Expander 0 U10 | |
34 | I2C1 0x51 (DDR) DDR EEPROM 1 U1 | |
35 | I2C1 0x68 DS1339 RTC 1 U68 | |
2ad6b513 TT |
36 | |
37 | Note that a given board has *either* a pair of 8574s or a pair of 8574As. | |
38 | */ | |
39 | ||
40 | #ifndef __CONFIG_H | |
41 | #define __CONFIG_H | |
42 | ||
fdfaa29e KP |
43 | #define CONFIG_DISPLAY_BOARDINFO |
44 | ||
14d0a02a | 45 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) |
6d0f6bcf | 46 | #define CONFIG_SYS_LOWBOOT |
7a78f148 | 47 | #endif |
2ad6b513 TT |
48 | |
49 | /* | |
50 | * High Level Configuration Options | |
51 | */ | |
2c7920af | 52 | #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ |
2ad6b513 TT |
53 | #define CONFIG_MPC8349 /* MPC8349 specific */ |
54 | ||
2ae18241 WD |
55 | #ifndef CONFIG_SYS_TEXT_BASE |
56 | #define CONFIG_SYS_TEXT_BASE 0xFEF00000 | |
57 | #endif | |
58 | ||
396abba2 | 59 | #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ |
7a78f148 | 60 | |
89c7784e TT |
61 | #define CONFIG_MISC_INIT_F |
62 | #define CONFIG_MISC_INIT_R | |
7a78f148 | 63 | |
89c7784e TT |
64 | /* |
65 | * On-board devices | |
66 | */ | |
2ad6b513 | 67 | |
7a78f148 | 68 | #ifdef CONFIG_MPC8349ITX |
396abba2 JH |
69 | /* The CF card interface on the back of the board */ |
70 | #define CONFIG_COMPACT_FLASH | |
89c7784e | 71 | #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ |
c9e34fe2 | 72 | #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ |
c31e1326 | 73 | #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ |
7a78f148 | 74 | #endif |
2ad6b513 | 75 | |
7a78f148 TT |
76 | #define CONFIG_PCI |
77 | #define CONFIG_RTC_DS1337 | |
00f792e0 | 78 | #define CONFIG_SYS_I2C |
7a78f148 | 79 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ |
2ad6b513 | 80 | |
7a78f148 TT |
81 | /* |
82 | * Device configurations | |
83 | */ | |
84 | ||
85 | /* I2C */ | |
00f792e0 HS |
86 | #ifdef CONFIG_SYS_I2C |
87 | #define CONFIG_SYS_I2C_FSL | |
88 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
89 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
90 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
91 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
92 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
93 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
2ad6b513 | 94 | |
6d0f6bcf | 95 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ |
b7be63ab | 96 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
6d0f6bcf JCPV |
97 | |
98 | #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ | |
99 | #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ | |
100 | #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ | |
101 | #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ | |
102 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ | |
396abba2 JH |
103 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ |
104 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ | |
2ad6b513 | 105 | |
2ad6b513 | 106 | /* Don't probe these addresses: */ |
396abba2 | 107 | #define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ |
6d0f6bcf JCPV |
108 | {1, CONFIG_SYS_I2C_8574_ADDR2}, \ |
109 | {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ | |
396abba2 | 110 | {1, CONFIG_SYS_I2C_8574A_ADDR2} } |
2ad6b513 | 111 | /* Bit definitions for the 8574[A] I2C expander */ |
396abba2 JH |
112 | /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ |
113 | #define I2C_8574_REVISION 0x03 | |
2ad6b513 TT |
114 | #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ |
115 | #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ | |
116 | #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ | |
117 | #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ | |
118 | ||
2ad6b513 TT |
119 | #endif |
120 | ||
7a78f148 TT |
121 | /* Compact Flash */ |
122 | #ifdef CONFIG_COMPACT_FLASH | |
2ad6b513 | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_IDE_MAXBUS 1 |
125 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
2ad6b513 | 126 | |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
128 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE | |
129 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 | |
130 | #define CONFIG_SYS_ATA_REG_OFFSET 0 | |
131 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 | |
132 | #define CONFIG_SYS_ATA_STRIDE 2 | |
2ad6b513 | 133 | |
396abba2 JH |
134 | /* If a CF card is not inserted, time out quickly */ |
135 | #define ATA_RESET_TIME 1 | |
2ad6b513 | 136 | |
c9e34fe2 VG |
137 | #endif |
138 | ||
139 | /* | |
140 | * SATA | |
141 | */ | |
142 | #ifdef CONFIG_SATA_SIL3114 | |
143 | ||
144 | #define CONFIG_SYS_SATA_MAX_DEVICE 4 | |
145 | #define CONFIG_LIBATA | |
146 | #define CONFIG_LBA48 | |
2ad6b513 | 147 | |
7a78f148 | 148 | #endif |
2ad6b513 | 149 | |
c31e1326 VG |
150 | #ifdef CONFIG_SYS_USB_HOST |
151 | /* | |
152 | * Support USB | |
153 | */ | |
c31e1326 VG |
154 | #define CONFIG_USB_STORAGE |
155 | #define CONFIG_USB_EHCI | |
156 | #define CONFIG_USB_EHCI_FSL | |
157 | ||
158 | /* Current USB implementation supports the only USB controller, | |
159 | * so we have to choose between the MPH or the DR ones */ | |
160 | #if 1 | |
161 | #define CONFIG_HAS_FSL_MPH_USB | |
162 | #else | |
163 | #define CONFIG_HAS_FSL_DR_USB | |
164 | #endif | |
165 | ||
166 | #endif | |
167 | ||
2ad6b513 | 168 | /* |
7a78f148 | 169 | * DDR Setup |
2ad6b513 | 170 | */ |
396abba2 | 171 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
6d0f6bcf JCPV |
172 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
173 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
174 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
396abba2 | 175 | #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_MEMTEST_END 0x2000 |
177 | ||
396abba2 JH |
178 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
179 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) | |
f64702b7 | 180 | |
b7be63ab VG |
181 | #define CONFIG_VERY_BIG_RAM |
182 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) | |
183 | ||
00f792e0 | 184 | #ifdef CONFIG_SYS_I2C |
7a78f148 TT |
185 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
186 | #endif | |
187 | ||
396abba2 JH |
188 | /* No SPD? Then manually set up DDR parameters */ |
189 | #ifndef CONFIG_SPD_EEPROM | |
190 | #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ | |
2e651b24 | 191 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ |
396abba2 JH |
192 | | CSCONFIG_ROW_BIT_13 \ |
193 | | CSCONFIG_COL_BIT_10) | |
2ad6b513 | 194 | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_DDR_TIMING_1 0x26242321 |
196 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ | |
2ad6b513 TT |
197 | #endif |
198 | ||
7a78f148 TT |
199 | /* |
200 | *Flash on the Local Bus | |
201 | */ | |
202 | ||
396abba2 JH |
203 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
204 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
206 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
396abba2 JH |
207 | /* 127 64KB sectors + 8 8KB sectors per device */ |
208 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
6d0f6bcf JCPV |
209 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
210 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
211 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
7a78f148 TT |
212 | |
213 | /* The ITX has two flash chips, but the ITX-GP has only one. To support both | |
214 | boards, we say we have two, but don't display a message if we find only one. */ | |
6d0f6bcf | 215 | #define CONFIG_SYS_FLASH_QUIET_TEST |
396abba2 JH |
216 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
217 | #define CONFIG_SYS_FLASH_BANKS_LIST \ | |
218 | {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} | |
219 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ | |
396abba2 | 220 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
7a78f148 | 221 | |
89c7784e TT |
222 | /* Vitesse 7385 */ |
223 | ||
224 | #ifdef CONFIG_VSC7385_ENET | |
225 | ||
226 | #define CONFIG_TSEC2 | |
227 | ||
228 | /* The flash address and size of the VSC7385 firmware image */ | |
229 | #define CONFIG_VSC7385_IMAGE 0xFEFFE000 | |
230 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
231 | ||
232 | #endif | |
233 | ||
7a78f148 TT |
234 | /* |
235 | * BRx, ORx, LBLAWBARx, and LBLAWARx | |
236 | */ | |
237 | ||
238 | /* Flash */ | |
2ad6b513 | 239 | |
7d6a0982 JH |
240 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
241 | | BR_PS_16 \ | |
242 | | BR_MS_GPCM \ | |
243 | | BR_V) | |
244 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
396abba2 JH |
245 | | OR_UPM_XAM \ |
246 | | OR_GPCM_CSNT \ | |
247 | | OR_GPCM_ACS_DIV2 \ | |
248 | | OR_GPCM_XACS \ | |
249 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
250 | | OR_GPCM_TRLX_SET \ |
251 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 252 | | OR_GPCM_EAD) |
6d0f6bcf | 253 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
7d6a0982 | 254 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) |
2ad6b513 | 255 | |
7a78f148 | 256 | /* Vitesse 7385 */ |
2ad6b513 | 257 | |
6d0f6bcf | 258 | #define CONFIG_SYS_VSC7385_BASE 0xF8000000 |
2ad6b513 | 259 | |
89c7784e TT |
260 | #ifdef CONFIG_VSC7385_ENET |
261 | ||
7d6a0982 JH |
262 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \ |
263 | | BR_PS_8 \ | |
264 | | BR_MS_GPCM \ | |
265 | | BR_V) | |
396abba2 JH |
266 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \ |
267 | | OR_GPCM_CSNT \ | |
268 | | OR_GPCM_XACS \ | |
269 | | OR_GPCM_SCY_15 \ | |
270 | | OR_GPCM_SETA \ | |
7d6a0982 JH |
271 | | OR_GPCM_TRLX_SET \ |
272 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 273 | | OR_GPCM_EAD) |
2ad6b513 | 274 | |
6d0f6bcf JCPV |
275 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE |
276 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) | |
2ad6b513 | 277 | |
7a78f148 | 278 | #endif |
2ad6b513 | 279 | |
7a78f148 TT |
280 | /* LED */ |
281 | ||
396abba2 | 282 | #define CONFIG_SYS_LED_BASE 0xF9000000 |
7d6a0982 JH |
283 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \ |
284 | | BR_PS_8 \ | |
285 | | BR_MS_GPCM \ | |
286 | | BR_V) | |
396abba2 JH |
287 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \ |
288 | | OR_GPCM_CSNT \ | |
289 | | OR_GPCM_ACS_DIV2 \ | |
290 | | OR_GPCM_XACS \ | |
291 | | OR_GPCM_SCY_9 \ | |
7d6a0982 JH |
292 | | OR_GPCM_TRLX_SET \ |
293 | | OR_GPCM_EHTR_SET \ | |
396abba2 | 294 | | OR_GPCM_EAD) |
7a78f148 TT |
295 | |
296 | /* Compact Flash */ | |
2ad6b513 TT |
297 | |
298 | #ifdef CONFIG_COMPACT_FLASH | |
299 | ||
396abba2 | 300 | #define CONFIG_SYS_CF_BASE 0xF0000000 |
2ad6b513 | 301 | |
396abba2 JH |
302 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \ |
303 | | BR_PS_16 \ | |
304 | | BR_MS_UPMA \ | |
305 | | BR_V) | |
306 | #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) | |
2ad6b513 | 307 | |
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE |
309 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) | |
2ad6b513 TT |
310 | |
311 | #endif | |
312 | ||
7a78f148 TT |
313 | /* |
314 | * U-Boot memory configuration | |
315 | */ | |
14d0a02a | 316 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
2ad6b513 | 317 | |
6d0f6bcf JCPV |
318 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
319 | #define CONFIG_SYS_RAMBOOT | |
2ad6b513 | 320 | #else |
6d0f6bcf | 321 | #undef CONFIG_SYS_RAMBOOT |
2ad6b513 TT |
322 | #endif |
323 | ||
6d0f6bcf | 324 | #define CONFIG_SYS_INIT_RAM_LOCK |
396abba2 JH |
325 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
326 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
2ad6b513 | 327 | |
396abba2 JH |
328 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
329 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 330 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
2ad6b513 | 331 | |
6d0f6bcf | 332 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
396abba2 | 333 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
c8a90646 | 334 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
2ad6b513 TT |
335 | |
336 | /* | |
337 | * Local Bus LCRR and LBCR regs | |
338 | * LCRR: DLL bypass, Clock divider is 4 | |
339 | * External Local Bus rate is | |
340 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
341 | */ | |
c7190f02 KP |
342 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
343 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 344 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
2ad6b513 | 345 | |
396abba2 JH |
346 | /* LB sdram refresh timer, about 6us */ |
347 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
348 | /* LB refresh timer prescal, 266MHz/32*/ | |
349 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
2ad6b513 | 350 | |
2ad6b513 TT |
351 | /* |
352 | * Serial Port | |
353 | */ | |
354 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
355 | #define CONFIG_SYS_NS16550_SERIAL |
356 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
357 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
2ad6b513 | 358 | |
6d0f6bcf | 359 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
396abba2 | 360 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
7a78f148 | 361 | |
8a364f09 | 362 | #define CONFIG_CONSOLE ttyS0 |
7a78f148 | 363 | #define CONFIG_BAUDRATE 115200 |
2ad6b513 | 364 | |
6d0f6bcf JCPV |
365 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
366 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
2ad6b513 | 367 | |
7a78f148 TT |
368 | /* |
369 | * PCI | |
370 | */ | |
2ad6b513 | 371 | #ifdef CONFIG_PCI |
842033e6 | 372 | #define CONFIG_PCI_INDIRECT_BRIDGE |
2ad6b513 TT |
373 | |
374 | #define CONFIG_MPC83XX_PCI2 | |
375 | ||
376 | /* | |
377 | * General PCI | |
378 | * Addresses are mapped 1-1. | |
379 | */ | |
6d0f6bcf JCPV |
380 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
381 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
382 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
383 | #define CONFIG_SYS_PCI1_MMIO_BASE \ |
384 | (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
6d0f6bcf JCPV |
385 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE |
386 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
387 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
388 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
389 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
2ad6b513 TT |
390 | |
391 | #ifdef CONFIG_MPC83XX_PCI2 | |
396abba2 JH |
392 | #define CONFIG_SYS_PCI2_MEM_BASE \ |
393 | (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) | |
6d0f6bcf JCPV |
394 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE |
395 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
396 | #define CONFIG_SYS_PCI2_MMIO_BASE \ |
397 | (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) | |
6d0f6bcf JCPV |
398 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE |
399 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
396abba2 JH |
400 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
401 | #define CONFIG_SYS_PCI2_IO_PHYS \ | |
402 | (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) | |
403 | #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ | |
2ad6b513 TT |
404 | #endif |
405 | ||
dd520bf3 | 406 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
2ad6b513 | 407 | |
2ad6b513 TT |
408 | #ifndef CONFIG_PCI_PNP |
409 | #define PCI_ENET0_IOADDR 0x00000000 | |
6d0f6bcf | 410 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE |
2ad6b513 TT |
411 | #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ |
412 | #endif | |
413 | ||
414 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
415 | ||
416 | #endif | |
417 | ||
2ae18241 WD |
418 | #define CONFIG_PCI_66M |
419 | #ifdef CONFIG_PCI_66M | |
7a78f148 TT |
420 | #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ |
421 | #else | |
422 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
423 | #endif | |
424 | ||
2ad6b513 TT |
425 | /* TSEC */ |
426 | ||
427 | #ifdef CONFIG_TSEC_ENET | |
428 | ||
2ad6b513 | 429 | #define CONFIG_MII |
659e2f67 | 430 | #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ |
2ad6b513 | 431 | |
255a3577 | 432 | #define CONFIG_TSEC1 |
2ad6b513 | 433 | |
255a3577 | 434 | #ifdef CONFIG_TSEC1 |
10327dc5 | 435 | #define CONFIG_HAS_ETH0 |
255a3577 | 436 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 437 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
dd520bf3 | 438 | #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ |
2ad6b513 | 439 | #define TSEC1_PHYIDX 0 |
3a79013e | 440 | #define TSEC1_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
441 | #endif |
442 | ||
255a3577 | 443 | #ifdef CONFIG_TSEC2 |
7a78f148 | 444 | #define CONFIG_HAS_ETH1 |
255a3577 | 445 | #define CONFIG_TSEC2_NAME "TSEC1" |
6d0f6bcf | 446 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e | 447 | |
2ad6b513 TT |
448 | #define TSEC2_PHY_ADDR 4 |
449 | #define TSEC2_PHYIDX 0 | |
3a79013e | 450 | #define TSEC2_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
451 | #endif |
452 | ||
453 | #define CONFIG_ETHPRIME "Freescale TSEC" | |
454 | ||
455 | #endif | |
456 | ||
2ad6b513 TT |
457 | /* |
458 | * Environment | |
459 | */ | |
7a78f148 TT |
460 | #define CONFIG_ENV_OVERWRITE |
461 | ||
6d0f6bcf | 462 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 463 | #define CONFIG_ENV_IS_IN_FLASH |
396abba2 JH |
464 | #define CONFIG_ENV_ADDR \ |
465 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 | 466 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ |
396abba2 | 467 | #define CONFIG_ENV_SIZE 0x2000 |
2ad6b513 | 468 | #else |
396abba2 | 469 | #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ |
00b1883a | 470 | #undef CONFIG_FLASH_CFI_DRIVER |
93f6d725 | 471 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
396abba2 JH |
472 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
473 | #define CONFIG_ENV_SIZE 0x2000 | |
2ad6b513 TT |
474 | #endif |
475 | ||
476 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
6d0f6bcf | 477 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
2ad6b513 | 478 | |
659e2f67 JL |
479 | /* |
480 | * BOOTP options | |
481 | */ | |
482 | #define CONFIG_BOOTP_BOOTFILESIZE | |
483 | #define CONFIG_BOOTP_BOOTPATH | |
484 | #define CONFIG_BOOTP_GATEWAY | |
485 | #define CONFIG_BOOTP_HOSTNAME | |
486 | ||
8ea5499a JL |
487 | /* |
488 | * Command line configuration. | |
489 | */ | |
8ea5499a JL |
490 | #define CONFIG_CMD_CACHE |
491 | #define CONFIG_CMD_DATE | |
492 | #define CONFIG_CMD_IRQ | |
8ea5499a | 493 | #define CONFIG_CMD_SDRAM |
2ad6b513 | 494 | |
c31e1326 | 495 | #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ |
396abba2 JH |
496 | || defined(CONFIG_USB_STORAGE) |
497 | #define CONFIG_DOS_PARTITION | |
498 | #define CONFIG_CMD_FAT | |
499 | #define CONFIG_SUPPORT_VFAT | |
c9e34fe2 VG |
500 | #endif |
501 | ||
2ad6b513 | 502 | #ifdef CONFIG_COMPACT_FLASH |
396abba2 | 503 | #define CONFIG_CMD_IDE |
c9e34fe2 VG |
504 | #endif |
505 | ||
506 | #ifdef CONFIG_SATA_SIL3114 | |
396abba2 | 507 | #define CONFIG_CMD_SATA |
c31e1326 VG |
508 | #endif |
509 | ||
510 | #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) | |
396abba2 | 511 | #define CONFIG_CMD_EXT2 |
2ad6b513 TT |
512 | #endif |
513 | ||
514 | #ifdef CONFIG_PCI | |
396abba2 | 515 | #define CONFIG_CMD_PCI |
2ad6b513 TT |
516 | #endif |
517 | ||
2ad6b513 | 518 | /* Watchdog */ |
2ad6b513 | 519 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
2ad6b513 TT |
520 | |
521 | /* | |
522 | * Miscellaneous configurable options | |
523 | */ | |
396abba2 JH |
524 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
525 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
526 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
7a78f148 | 527 | |
6d0f6bcf | 528 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
05f91a65 | 529 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
7a78f148 | 530 | |
8ea5499a | 531 | #if defined(CONFIG_CMD_KGDB) |
396abba2 | 532 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
2ad6b513 | 533 | #else |
396abba2 | 534 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
2ad6b513 TT |
535 | #endif |
536 | ||
396abba2 JH |
537 | /* Print Buffer Size */ |
538 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
539 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
540 | /* Boot Argument Buffer Size */ | |
541 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
2ad6b513 TT |
542 | |
543 | /* | |
544 | * For booting Linux, the board info and command line data | |
9f530d59 | 545 | * have to be in the first 256 MB of memory, since this is |
2ad6b513 TT |
546 | * the maximum mapped by the Linux kernel during initialization. |
547 | */ | |
396abba2 JH |
548 | /* Initial Memory map for Linux*/ |
549 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
2ad6b513 | 550 | |
6d0f6bcf | 551 | #define CONFIG_SYS_HRCW_LOW (\ |
2ad6b513 TT |
552 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
553 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
554 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
555 | HRCWL_VCO_1X2 |\ | |
556 | HRCWL_CORE_TO_CSB_2X1) | |
557 | ||
6d0f6bcf JCPV |
558 | #ifdef CONFIG_SYS_LOWBOOT |
559 | #define CONFIG_SYS_HRCW_HIGH (\ | |
2ad6b513 | 560 | HRCWH_PCI_HOST |\ |
7a78f148 | 561 | HRCWH_32_BIT_PCI |\ |
2ad6b513 | 562 | HRCWH_PCI1_ARBITER_ENABLE |\ |
7a78f148 | 563 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
564 | HRCWH_CORE_ENABLE |\ |
565 | HRCWH_FROM_0X00000100 |\ | |
566 | HRCWH_BOOTSEQ_DISABLE |\ | |
567 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
568 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
569 | HRCWH_TSEC1M_IN_GMII |\ | |
396abba2 | 570 | HRCWH_TSEC2M_IN_GMII) |
2ad6b513 | 571 | #else |
6d0f6bcf | 572 | #define CONFIG_SYS_HRCW_HIGH (\ |
2ad6b513 TT |
573 | HRCWH_PCI_HOST |\ |
574 | HRCWH_32_BIT_PCI |\ | |
575 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
7a78f148 | 576 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
577 | HRCWH_CORE_ENABLE |\ |
578 | HRCWH_FROM_0XFFF00100 |\ | |
579 | HRCWH_BOOTSEQ_DISABLE |\ | |
580 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
581 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
582 | HRCWH_TSEC1M_IN_GMII |\ | |
396abba2 | 583 | HRCWH_TSEC2M_IN_GMII) |
2ad6b513 TT |
584 | #endif |
585 | ||
7a78f148 TT |
586 | /* |
587 | * System performance | |
588 | */ | |
6d0f6bcf | 589 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
396abba2 | 590 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
6d0f6bcf JCPV |
591 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
592 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
593 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
594 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
c31e1326 VG |
595 | #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ |
596 | #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ | |
2ad6b513 | 597 | |
7a78f148 TT |
598 | /* |
599 | * System IO Config | |
600 | */ | |
396abba2 JH |
601 | /* Needed for gigabit to work on TSEC 1 */ |
602 | #define CONFIG_SYS_SICRH SICRH_TSOBI1 | |
603 | /* USB DR as device + USB MPH as host */ | |
604 | #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) | |
2ad6b513 | 605 | |
1a2e203b KP |
606 | #define CONFIG_SYS_HID0_INIT 0x00000000 |
607 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE | |
2ad6b513 | 608 | |
6d0f6bcf | 609 | #define CONFIG_SYS_HID2 HID2_HBE |
31d82672 | 610 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
2ad6b513 | 611 | |
7a78f148 | 612 | /* DDR */ |
396abba2 | 613 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 614 | | BATL_PP_RW \ |
396abba2 JH |
615 | | BATL_MEMCOHERENCE) |
616 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
617 | | BATU_BL_256M \ | |
618 | | BATU_VS \ | |
619 | | BATU_VP) | |
2ad6b513 | 620 | |
7a78f148 | 621 | /* PCI */ |
2ad6b513 | 622 | #ifdef CONFIG_PCI |
396abba2 | 623 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 624 | | BATL_PP_RW \ |
396abba2 JH |
625 | | BATL_MEMCOHERENCE) |
626 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
627 | | BATU_BL_256M \ | |
628 | | BATU_VS \ | |
629 | | BATU_VP) | |
630 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 631 | | BATL_PP_RW \ |
396abba2 JH |
632 | | BATL_CACHEINHIBIT \ |
633 | | BATL_GUARDEDSTORAGE) | |
634 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
635 | | BATU_BL_256M \ | |
636 | | BATU_VS \ | |
637 | | BATU_VP) | |
2ad6b513 | 638 | #else |
6d0f6bcf JCPV |
639 | #define CONFIG_SYS_IBAT1L 0 |
640 | #define CONFIG_SYS_IBAT1U 0 | |
641 | #define CONFIG_SYS_IBAT2L 0 | |
642 | #define CONFIG_SYS_IBAT2U 0 | |
2ad6b513 TT |
643 | #endif |
644 | ||
645 | #ifdef CONFIG_MPC83XX_PCI2 | |
396abba2 | 646 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
72cd4087 | 647 | | BATL_PP_RW \ |
396abba2 JH |
648 | | BATL_MEMCOHERENCE) |
649 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
650 | | BATU_BL_256M \ | |
651 | | BATU_VS \ | |
652 | | BATU_VP) | |
653 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
72cd4087 | 654 | | BATL_PP_RW \ |
396abba2 JH |
655 | | BATL_CACHEINHIBIT \ |
656 | | BATL_GUARDEDSTORAGE) | |
657 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
658 | | BATU_BL_256M \ | |
659 | | BATU_VS \ | |
660 | | BATU_VP) | |
2ad6b513 | 661 | #else |
6d0f6bcf JCPV |
662 | #define CONFIG_SYS_IBAT3L 0 |
663 | #define CONFIG_SYS_IBAT3U 0 | |
664 | #define CONFIG_SYS_IBAT4L 0 | |
665 | #define CONFIG_SYS_IBAT4U 0 | |
2ad6b513 TT |
666 | #endif |
667 | ||
668 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
396abba2 | 669 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 670 | | BATL_PP_RW \ |
396abba2 JH |
671 | | BATL_CACHEINHIBIT \ |
672 | | BATL_GUARDEDSTORAGE) | |
673 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
674 | | BATU_BL_256M \ | |
675 | | BATU_VS \ | |
676 | | BATU_VP) | |
2ad6b513 TT |
677 | |
678 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
396abba2 | 679 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
72cd4087 | 680 | | BATL_PP_RW \ |
396abba2 JH |
681 | | BATL_MEMCOHERENCE \ |
682 | | BATL_GUARDEDSTORAGE) | |
683 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ | |
684 | | BATU_BL_256M \ | |
685 | | BATU_VS \ | |
686 | | BATU_VP) | |
6d0f6bcf JCPV |
687 | |
688 | #define CONFIG_SYS_IBAT7L 0 | |
689 | #define CONFIG_SYS_IBAT7U 0 | |
690 | ||
691 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
692 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
693 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
694 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
695 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
696 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
697 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
698 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
699 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
700 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
701 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
702 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
703 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
704 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
705 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
706 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
2ad6b513 | 707 | |
8ea5499a | 708 | #if defined(CONFIG_CMD_KGDB) |
2ad6b513 | 709 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
2ad6b513 TT |
710 | #endif |
711 | ||
2ad6b513 TT |
712 | /* |
713 | * Environment Configuration | |
714 | */ | |
715 | #define CONFIG_ENV_OVERWRITE | |
716 | ||
396abba2 | 717 | #define CONFIG_NETDEV "eth0" |
2ad6b513 | 718 | |
7a78f148 | 719 | #ifdef CONFIG_MPC8349ITX |
396abba2 | 720 | #define CONFIG_HOSTNAME "mpc8349emitx" |
7a78f148 | 721 | #else |
396abba2 | 722 | #define CONFIG_HOSTNAME "mpc8349emitxgp" |
be5e6181 TT |
723 | #endif |
724 | ||
7a78f148 | 725 | /* Default path and filenames */ |
8b3637c6 | 726 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
b3f44c21 | 727 | #define CONFIG_BOOTFILE "uImage" |
396abba2 JH |
728 | /* U-Boot image on TFTP server */ |
729 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
2ad6b513 | 730 | |
7a78f148 | 731 | #ifdef CONFIG_MPC8349ITX |
396abba2 | 732 | #define CONFIG_FDTFILE "mpc8349emitx.dtb" |
2ad6b513 | 733 | #else |
396abba2 | 734 | #define CONFIG_FDTFILE "mpc8349emitxgp.dtb" |
2ad6b513 TT |
735 | #endif |
736 | ||
05f91a65 | 737 | #define CONFIG_BOOTDELAY 6 |
7a78f148 | 738 | |
98883332 TT |
739 | #define CONFIG_BOOTARGS \ |
740 | "root=/dev/nfs rw" \ | |
5368c55d MV |
741 | " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ |
742 | " ip=" __stringify(CONFIG_IPADDR) ":" \ | |
743 | __stringify(CONFIG_SERVERIP) ":" \ | |
744 | __stringify(CONFIG_GATEWAYIP) ":" \ | |
745 | __stringify(CONFIG_NETMASK) ":" \ | |
396abba2 | 746 | CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \ |
5368c55d | 747 | " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE) |
98883332 | 748 | |
dd520bf3 | 749 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d | 750 | "console=" __stringify(CONFIG_CONSOLE) "\0" \ |
396abba2 JH |
751 | "netdev=" CONFIG_NETDEV "\0" \ |
752 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
53677ef1 | 753 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
5368c55d MV |
754 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
755 | " +$filesize; " \ | |
756 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
757 | " +$filesize; " \ | |
758 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
759 | " $filesize; " \ | |
760 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
761 | " +$filesize; " \ | |
762 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
763 | " $filesize\0" \ | |
05f91a65 | 764 | "fdtaddr=780000\0" \ |
396abba2 | 765 | "fdtfile=" CONFIG_FDTFILE "\0" |
bf0b542d | 766 | |
dd520bf3 | 767 | #define CONFIG_NFSBOOTCOMMAND \ |
7a78f148 | 768 | "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ |
396abba2 | 769 | " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ |
7a78f148 TT |
770 | " console=$console,$baudrate $othbootargs; " \ |
771 | "tftp $loadaddr $bootfile;" \ | |
772 | "tftp $fdtaddr $fdtfile;" \ | |
773 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d | 774 | |
dd520bf3 | 775 | #define CONFIG_RAMBOOTCOMMAND \ |
7a78f148 TT |
776 | "setenv bootargs root=/dev/ram rw" \ |
777 | " console=$console,$baudrate $othbootargs; " \ | |
778 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
779 | "tftp $loadaddr $bootfile;" \ | |
780 | "tftp $fdtaddr $fdtfile;" \ | |
781 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
2ad6b513 | 782 | |
2ad6b513 | 783 | #endif |