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42d1f039 | 1 | /* |
7c57f3e8 | 2 | * Copyright 2004, 2011 Freescale Semiconductor. |
42d1f039 WD |
3 | * (C) Copyright 2002,2003 Motorola,Inc. |
4 | * Xianghua Xiao <X.Xiao@motorola.com> | |
5 | * | |
3765b3e7 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
42d1f039 WD |
7 | */ |
8 | ||
0ac6f8b7 WD |
9 | /* |
10 | * mpc8560ads board configuration file | |
11 | * | |
12 | * Please refer to doc/README.mpc85xx for more info. | |
13 | * | |
14 | * Make sure you change the MAC address and other network params first, | |
92ac5208 | 15 | * search for CONFIG_SERVERIP, etc. in this file. |
42d1f039 WD |
16 | */ |
17 | ||
18 | #ifndef __CONFIG_H | |
19 | #define __CONFIG_H | |
20 | ||
21 | /* High Level Configuration Options */ | |
0ac6f8b7 WD |
22 | #define CONFIG_BOOKE 1 /* BOOKE */ |
23 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
9c4c5ae3 | 24 | #define CONFIG_CPM2 1 /* has CPM2 */ |
0ac6f8b7 | 25 | |
2ae18241 WD |
26 | /* |
27 | * default CCARBAR is at 0xff700000 | |
28 | * assume U-Boot is less than 0.5MB | |
29 | */ | |
30 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
31 | ||
842033e6 | 32 | #define CONFIG_PCI_INDIRECT_BRIDGE |
0151cbac | 33 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
53677ef1 | 34 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
ccc091aa | 35 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
42d1f039 | 36 | #define CONFIG_ENV_OVERWRITE |
004eca0c | 37 | #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ |
42d1f039 | 38 | |
0ac6f8b7 WD |
39 | /* |
40 | * sysclk for MPC85xx | |
41 | * | |
42 | * Two valid values are: | |
43 | * 33000000 | |
44 | * 66000000 | |
45 | * | |
46 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
9aea9530 WD |
47 | * is likely the desired value here, so that is now the default. |
48 | * The board, however, can run at 66MHz. In any event, this value | |
49 | * must match the settings of some switches. Details can be found | |
50 | * in the README.mpc85xxads. | |
0ac6f8b7 WD |
51 | */ |
52 | ||
9aea9530 WD |
53 | #ifndef CONFIG_SYS_CLK_FREQ |
54 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
42d1f039 WD |
55 | #endif |
56 | ||
0ac6f8b7 WD |
57 | /* |
58 | * These can be toggled for performance analysis, otherwise use default. | |
59 | */ | |
60 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
61 | #define CONFIG_BTB /* toggle branch predition */ | |
42d1f039 | 62 | |
6d0f6bcf | 63 | #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ |
0ac6f8b7 | 64 | |
6d0f6bcf JCPV |
65 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
66 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
42d1f039 | 67 | |
e46fedfe TT |
68 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
69 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
42d1f039 | 70 | |
8b625114 | 71 | /* DDR Setup */ |
5614e71b | 72 | #define CONFIG_SYS_FSL_DDR1 |
8b625114 JL |
73 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
74 | #define CONFIG_DDR_SPD | |
75 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
76 | ||
77 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
9aea9530 | 78 | |
6d0f6bcf JCPV |
79 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
80 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
9aea9530 | 81 | |
8b625114 JL |
82 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
83 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
84 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
9aea9530 | 85 | |
8b625114 JL |
86 | /* I2C addresses of SPD EEPROMs */ |
87 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
9aea9530 | 88 | |
8b625114 | 89 | /* These are used when DDR doesn't use SPD. */ |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ |
91 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ | |
92 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 | |
93 | #define CONFIG_SYS_DDR_TIMING_1 0x37344321 | |
94 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
95 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
96 | #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ | |
97 | #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ | |
42d1f039 | 98 | |
0ac6f8b7 WD |
99 | /* |
100 | * SDRAM on the Local Bus | |
101 | */ | |
6d0f6bcf JCPV |
102 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
103 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
42d1f039 | 104 | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
106 | #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
42d1f039 | 107 | |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ |
109 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
110 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
111 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
112 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
113 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
0ac6f8b7 | 114 | |
14d0a02a | 115 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
42d1f039 | 116 | |
6d0f6bcf JCPV |
117 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
118 | #define CONFIG_SYS_RAMBOOT | |
42d1f039 | 119 | #else |
6d0f6bcf | 120 | #undef CONFIG_SYS_RAMBOOT |
42d1f039 WD |
121 | #endif |
122 | ||
00b1883a | 123 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_FLASH_CFI |
125 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
0ac6f8b7 WD |
126 | |
127 | #undef CONFIG_CLOCKS_IN_MHZ | |
42d1f039 | 128 | |
0ac6f8b7 WD |
129 | /* |
130 | * Local Bus Definitions | |
131 | */ | |
132 | ||
133 | /* | |
134 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 135 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
0ac6f8b7 WD |
136 | * |
137 | * For BR2, need: | |
138 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
139 | * port-size = 32-bits = BR2[19:20] = 11 | |
140 | * no parity checking = BR2[21:22] = 00 | |
141 | * SDRAM for MSEL = BR2[24:26] = 011 | |
142 | * Valid = BR[31] = 1 | |
143 | * | |
144 | * 0 4 8 12 16 20 24 28 | |
145 | * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 | |
146 | * | |
6d0f6bcf | 147 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
0ac6f8b7 WD |
148 | * FIXME: the top 17 bits of BR2. |
149 | */ | |
150 | ||
6d0f6bcf | 151 | #define CONFIG_SYS_BR2_PRELIM 0xf0001861 |
0ac6f8b7 WD |
152 | |
153 | /* | |
6d0f6bcf | 154 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
0ac6f8b7 WD |
155 | * |
156 | * For OR2, need: | |
157 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
158 | * XAM, OR2[17:18] = 11 | |
159 | * 9 columns OR2[19-21] = 010 | |
160 | * 13 rows OR2[23-25] = 100 | |
161 | * EAD set for extra time OR[31] = 1 | |
162 | * | |
163 | * 0 4 8 12 16 20 24 28 | |
164 | * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 | |
165 | */ | |
166 | ||
6d0f6bcf | 167 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 |
0ac6f8b7 | 168 | |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
170 | #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ | |
171 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
172 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ | |
0ac6f8b7 | 173 | |
b0fe93ed KG |
174 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ |
175 | | LSDMR_RFCR5 \ | |
176 | | LSDMR_PRETOACT3 \ | |
177 | | LSDMR_ACTTORW3 \ | |
178 | | LSDMR_BL8 \ | |
179 | | LSDMR_WRC2 \ | |
180 | | LSDMR_CL3 \ | |
181 | | LSDMR_RFEN \ | |
0ac6f8b7 WD |
182 | ) |
183 | ||
184 | /* | |
185 | * SDRAM Controller configuration sequence. | |
186 | */ | |
b0fe93ed KG |
187 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
188 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
189 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
190 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
191 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
0ac6f8b7 | 192 | |
9aea9530 WD |
193 | /* |
194 | * 32KB, 8-bit wide for ADS config reg | |
195 | */ | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_BR4_PRELIM 0xf8000801 |
197 | #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 | |
198 | #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) | |
42d1f039 | 199 | |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
201 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 202 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
42d1f039 | 203 | |
25ddd1fb | 204 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 205 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
42d1f039 | 206 | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
208 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
42d1f039 WD |
209 | |
210 | /* Serial Port */ | |
0ac6f8b7 WD |
211 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
212 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
213 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ | |
42d1f039 | 214 | |
53677ef1 | 215 | #define CONFIG_BAUDRATE 115200 |
42d1f039 | 216 | |
6d0f6bcf | 217 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
42d1f039 WD |
218 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
219 | ||
20476726 JL |
220 | /* |
221 | * I2C | |
222 | */ | |
00f792e0 HS |
223 | #define CONFIG_SYS_I2C |
224 | #define CONFIG_SYS_I2C_FSL | |
225 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
226 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
227 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
228 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
42d1f039 | 229 | |
0ac6f8b7 | 230 | /* RapidIO MMU */ |
5af0fdd8 | 231 | #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ |
10795f42 | 232 | #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ |
5af0fdd8 | 233 | #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 |
6d0f6bcf | 234 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
0ac6f8b7 WD |
235 | |
236 | /* | |
237 | * General PCI | |
362dd830 | 238 | * Memory space is mapped 1-1, but I/O space must start from 0. |
0ac6f8b7 | 239 | */ |
5af0fdd8 | 240 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
10795f42 | 241 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
5af0fdd8 | 242 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 |
6d0f6bcf | 243 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
aca5f018 | 244 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 |
5f91ef6a | 245 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
246 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 |
247 | #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ | |
0ac6f8b7 WD |
248 | |
249 | #if defined(CONFIG_PCI) | |
0ac6f8b7 | 250 | #undef CONFIG_EEPRO100 |
42d1f039 | 251 | #undef CONFIG_TULIP |
0ac6f8b7 WD |
252 | |
253 | #if !defined(CONFIG_PCI_PNP) | |
254 | #define PCI_ENET0_IOADDR 0xe0000000 | |
255 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
53677ef1 | 256 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
42d1f039 | 257 | #endif |
0ac6f8b7 WD |
258 | |
259 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 260 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
0ac6f8b7 WD |
261 | |
262 | #endif /* CONFIG_PCI */ | |
263 | ||
ccc091aa | 264 | #ifdef CONFIG_TSEC_ENET |
0ac6f8b7 | 265 | |
ccc091aa | 266 | #ifndef CONFIG_MII |
0ac6f8b7 | 267 | #define CONFIG_MII 1 /* MII PHY management */ |
ccc091aa | 268 | #endif |
255a3577 KP |
269 | #define CONFIG_TSEC1 1 |
270 | #define CONFIG_TSEC1_NAME "TSEC0" | |
271 | #define CONFIG_TSEC2 1 | |
272 | #define CONFIG_TSEC2_NAME "TSEC1" | |
0ac6f8b7 WD |
273 | #define TSEC1_PHY_ADDR 0 |
274 | #define TSEC2_PHY_ADDR 1 | |
275 | #define TSEC1_PHYIDX 0 | |
276 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
277 | #define TSEC1_FLAGS TSEC_GIGABIT |
278 | #define TSEC2_FLAGS TSEC_GIGABIT | |
d9b94f28 JL |
279 | |
280 | /* Options are: TSEC[0-1] */ | |
281 | #define CONFIG_ETHPRIME "TSEC0" | |
0ac6f8b7 | 282 | |
ccc091aa AF |
283 | #endif /* CONFIG_TSEC_ENET */ |
284 | ||
53677ef1 | 285 | #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ |
0ac6f8b7 | 286 | |
53677ef1 | 287 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
0ac6f8b7 WD |
288 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
289 | ||
290 | #if (CONFIG_ETHER_INDEX == 2) | |
42d1f039 WD |
291 | /* |
292 | * - Rx-CLK is CLK13 | |
293 | * - Tx-CLK is CLK14 | |
294 | * - Select bus for bd/buffers | |
295 | * - Full duplex | |
296 | */ | |
d4590da4 MF |
297 | #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
298 | #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
6d0f6bcf JCPV |
299 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 |
300 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) | |
42d1f039 | 301 | #define FETH2_RST 0x01 |
0ac6f8b7 | 302 | #elif (CONFIG_ETHER_INDEX == 3) |
42d1f039 WD |
303 | /* need more definitions here for FE3 */ |
304 | #define FETH3_RST 0x80 | |
53677ef1 | 305 | #endif /* CONFIG_ETHER_INDEX */ |
0ac6f8b7 | 306 | |
ccc091aa AF |
307 | #ifndef CONFIG_MII |
308 | #define CONFIG_MII 1 /* MII PHY management */ | |
309 | #endif | |
310 | ||
0ac6f8b7 WD |
311 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
312 | ||
42d1f039 WD |
313 | /* |
314 | * GPIO pins used for bit-banged MII communications | |
315 | */ | |
316 | #define MDIO_PORT 2 /* Port C */ | |
be225442 LCM |
317 | #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ |
318 | (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) | |
319 | #define MDC_DECLARE MDIO_DECLARE | |
320 | ||
42d1f039 WD |
321 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
322 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) | |
323 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) | |
324 | ||
325 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ | |
326 | else iop->pdat &= ~0x00400000 | |
327 | ||
328 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ | |
329 | else iop->pdat &= ~0x00200000 | |
330 | ||
331 | #define MIIDELAY udelay(1) | |
0ac6f8b7 | 332 | |
42d1f039 WD |
333 | #endif |
334 | ||
0ac6f8b7 WD |
335 | /* |
336 | * Environment | |
337 | */ | |
6d0f6bcf | 338 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 339 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 340 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
0e8d1586 JCPV |
341 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
342 | #define CONFIG_ENV_SIZE 0x2000 | |
42d1f039 | 343 | #else |
6d0f6bcf | 344 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 345 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 346 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 347 | #define CONFIG_ENV_SIZE 0x2000 |
42d1f039 WD |
348 | #endif |
349 | ||
0ac6f8b7 | 350 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 351 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
42d1f039 | 352 | |
659e2f67 JL |
353 | /* |
354 | * BOOTP options | |
355 | */ | |
356 | #define CONFIG_BOOTP_BOOTFILESIZE | |
357 | #define CONFIG_BOOTP_BOOTPATH | |
358 | #define CONFIG_BOOTP_GATEWAY | |
359 | #define CONFIG_BOOTP_HOSTNAME | |
360 | ||
2835e518 JL |
361 | /* |
362 | * Command line configuration. | |
363 | */ | |
1c9aa76b | 364 | #define CONFIG_CMD_IRQ |
199e262e | 365 | #define CONFIG_CMD_REGINFO |
2835e518 JL |
366 | |
367 | #if defined(CONFIG_PCI) | |
368 | #define CONFIG_CMD_PCI | |
369 | #endif | |
370 | ||
371 | #if defined(CONFIG_ETHER_ON_FCC) | |
2835e518 JL |
372 | #endif |
373 | ||
0ac6f8b7 | 374 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
42d1f039 WD |
375 | |
376 | /* | |
377 | * Miscellaneous configurable options | |
378 | */ | |
6d0f6bcf | 379 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
5be58f5f KP |
380 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
381 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf | 382 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ |
0ac6f8b7 | 383 | |
2835e518 | 384 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 385 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
42d1f039 | 386 | #else |
6d0f6bcf | 387 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
42d1f039 | 388 | #endif |
0ac6f8b7 | 389 | |
6d0f6bcf JCPV |
390 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
391 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
392 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
42d1f039 WD |
393 | |
394 | /* | |
395 | * For booting Linux, the board info and command line data | |
a832ac41 | 396 | * have to be in the first 64 MB of memory, since this is |
42d1f039 WD |
397 | * the maximum mapped by the Linux kernel during initialization. |
398 | */ | |
a832ac41 KG |
399 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
400 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
42d1f039 | 401 | |
2835e518 | 402 | #if defined(CONFIG_CMD_KGDB) |
42d1f039 | 403 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
42d1f039 WD |
404 | #endif |
405 | ||
9aea9530 WD |
406 | /* |
407 | * Environment Configuration | |
408 | */ | |
42d1f039 | 409 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
10327dc5 | 410 | #define CONFIG_HAS_ETH0 |
e2ffd59b | 411 | #define CONFIG_HAS_ETH1 |
e2ffd59b | 412 | #define CONFIG_HAS_ETH2 |
5ce71580 | 413 | #define CONFIG_HAS_ETH3 |
42d1f039 WD |
414 | #endif |
415 | ||
0ac6f8b7 WD |
416 | #define CONFIG_IPADDR 192.168.1.253 |
417 | ||
418 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 419 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 420 | #define CONFIG_BOOTFILE "your.uImage" |
0ac6f8b7 WD |
421 | |
422 | #define CONFIG_SERVERIP 192.168.1.1 | |
423 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
424 | #define CONFIG_NETMASK 255.255.255.0 | |
425 | ||
426 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
427 | ||
0ac6f8b7 WD |
428 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
429 | ||
430 | #define CONFIG_BAUDRATE 115200 | |
431 | ||
9aea9530 | 432 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
6b44a44e AF |
433 | "netdev=eth0\0" \ |
434 | "consoledev=ttyCPM\0" \ | |
435 | "ramdiskaddr=1000000\0" \ | |
436 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
437 | "fdtaddr=400000\0" \ | |
438 | "fdtfile=mpc8560ads.dtb\0" | |
0ac6f8b7 | 439 | |
9aea9530 | 440 | #define CONFIG_NFSBOOTCOMMAND \ |
6b44a44e AF |
441 | "setenv bootargs root=/dev/nfs rw " \ |
442 | "nfsroot=$serverip:$rootpath " \ | |
443 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
444 | "console=$consoledev,$baudrate $othbootargs;" \ | |
445 | "tftp $loadaddr $bootfile;" \ | |
446 | "tftp $fdtaddr $fdtfile;" \ | |
447 | "bootm $loadaddr - $fdtaddr" | |
0ac6f8b7 WD |
448 | |
449 | #define CONFIG_RAMBOOTCOMMAND \ | |
6b44a44e AF |
450 | "setenv bootargs root=/dev/ram rw " \ |
451 | "console=$consoledev,$baudrate $othbootargs;" \ | |
452 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
453 | "tftp $loadaddr $bootfile;" \ | |
454 | "tftp $fdtaddr $fdtfile;" \ | |
455 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
0ac6f8b7 WD |
456 | |
457 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
42d1f039 WD |
458 | |
459 | #endif /* __CONFIG_H */ |